x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.
To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index f1d9977..d7b6836 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -25,8 +25,6 @@
/* Length of the public header on Intel microcode blobs */
#define UCODE_HEADER_LEN 0x30
-#ifndef __ASSEMBLY__
-
/*
* This register is documented in (for example) the Intel Atom Processor E3800
* Product Family Datasheet in "PCU - Power Management Controller (PMC)".
@@ -37,11 +35,11 @@
*/
#define IO_PORT_RESET 0xcf9
-enum {
- SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */
- RST_CPU = 1 << 2, /* initiate reset */
- FULL_RST = 1 << 3, /* full power cycle */
-};
+#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */
+#define RST_CPU (1 << 2) /* initiate reset */
+#define FULL_RST (1 << 3) /* full power cycle */
+
+#ifndef __ASSEMBLY__
static inline __attribute__((always_inline)) void cpu_hlt(void)
{