commit 8f5b30c1adad98a965a2e9101813005bde08798b
author Christian Marangi <ansuelsmth@gmail.com> Fri Jun 28 19:40:49 2024 +0200
committer Tom Rini <trini@konsulko.com> Thu Aug 01 15:32:18 2024 -0600
tree 16df47aa3e6e24ae43b692404c706292b58c0262
parent baa244cde21e96795446e16aa60eafdb5a222290

clk: mediatek: add support for gate ID at offset

Add support to clk_gate ops to reference the clk ID at an offset by
using the just introduced gates_offs value from the unified muxes +
gates implementation.

Gate clock that doesn't have gates_offs set won't be affected as the
offset will simply be 0 and won't be offset of any value.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

drivers/clk/mediatek/clk-mtk.c

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 986e735..1d5ae8f 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -530,8 +530,12 @@
 static int mtk_clk_gate_enable(struct clk *clk)
 {
 	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_gate *gate = &priv->gates[clk->id];
+	const struct mtk_gate *gate;
+
+	if (clk->id < priv->tree->gates_offs)
+		return -EINVAL;
 
+	gate = &priv->gates[clk->id - priv->tree->gates_offs];
 	return mtk_gate_enable(priv->base, gate);
 }
 
@@ -576,8 +580,12 @@
 static int mtk_clk_gate_disable(struct clk *clk)
 {
 	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_gate *gate = &priv->gates[clk->id];
+	const struct mtk_gate *gate;
 
+	if (clk->id < priv->tree->gates_offs)
+		return -EINVAL;
+
+	gate = &priv->gates[clk->id - priv->tree->gates_offs];
 	return mtk_gate_disable(priv->base, gate);
 }
 
@@ -597,8 +605,12 @@
 static ulong mtk_clk_gate_get_rate(struct clk *clk)
 {
 	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_gate *gate = &priv->gates[clk->id];
+	const struct mtk_gate *gate;
+
+	if (clk->id < priv->tree->gates_offs)
+		return -EINVAL;
 
+	gate = &priv->gates[clk->id - priv->tree->gates_offs];
 	/*
 	 * Assume xtal_rate to be declared if some gates have
 	 * XTAL as parent