dts: starfive: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.
Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c
index 6d2bfb3..f8af172 100644
--- a/drivers/clk/starfive/clk-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-jh7110-pll.c
@@ -374,13 +374,13 @@
if (sysreg == FDT_ADDR_T_NONE)
return -EINVAL;
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT),
starfive_jh7110_pll("pll0_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll0));
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT),
starfive_jh7110_pll("pll1_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll1));
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT),
+ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT),
starfive_jh7110_pll("pll2_out", "oscillator", reg,
(void __iomem *)sysreg, &starfive_jh7110_pll2));
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 191da75..6387e94 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -495,37 +495,37 @@
{
struct jh7110_clk_priv *priv = dev_get_priv(dev);
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB),
starfive_clk_gate(priv->reg,
"usb_apb", "apb_bus",
- OFFSET(JH7110_STGCLK_USB_APB)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB),
+ OFFSET(JH7110_STGCLK_USB0_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB),
starfive_clk_gate(priv->reg,
"usb_utmi_apb", "apb_bus",
- OFFSET(JH7110_STGCLK_USB_UTMI_APB)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI),
+ OFFSET(JH7110_STGCLK_USB0_UTMI_APB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI),
starfive_clk_gate(priv->reg,
"usb_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_USB_AXI)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM),
+ OFFSET(JH7110_STGCLK_USB0_AXI)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM),
starfive_clk_gate_divider(priv->reg,
"usb_lpm", "oscillator",
- OFFSET(JH7110_STGCLK_USB_LPM), 2));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB),
+ OFFSET(JH7110_STGCLK_USB0_LPM), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB),
starfive_clk_gate_divider(priv->reg,
"usb_stb", "oscillator",
- OFFSET(JH7110_STGCLK_USB_STB), 3));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125),
+ OFFSET(JH7110_STGCLK_USB0_STB), 3));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125),
starfive_clk_gate(priv->reg,
"usb_app_125", "usb_125m",
- OFFSET(JH7110_STGCLK_USB_APP_125)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK),
+ OFFSET(JH7110_STGCLK_USB0_APP_125)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK),
starfive_clk_divider(priv->reg, "usb_refclk", "oscillator",
- OFFSET(JH7110_STGCLK_USB_REFCLK), 2));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI),
+ OFFSET(JH7110_STGCLK_USB0_REFCLK), 2));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0),
starfive_clk_gate(priv->reg,
"pcie0_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB),
starfive_clk_gate(priv->reg,
"pcie0_apb", "apb_bus",
@@ -534,10 +534,10 @@
starfive_clk_gate(priv->reg,
"pcie0_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE0_TL)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0),
starfive_clk_gate(priv->reg,
"pcie1_axi", "stg_axiahb",
- OFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB),
starfive_clk_gate(priv->reg,
"pcie1_apb", "apb_bus",
@@ -548,14 +548,14 @@
OFFSET(JH7110_STGCLK_PCIE1_TL)));
/* Security clocks */
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB),
starfive_clk_gate(priv->reg,
"sec_ahb", "stg_axiahb",
- OFFSET(JH7110_STGCLK_SEC_HCLK)));
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ OFFSET(JH7110_STGCLK_SEC_AHB)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB),
starfive_clk_gate(priv->reg,
"sec_misc_ahb", "stg_axiahb",
- OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+ OFFSET(JH7110_STGCLK_SEC_MISC_AHB)));
return 0;
}