tree 915e01c99bc5346e74251e28e98315412a6df26f
parent 4443c5caf33ece7c3f512c2f5712b2a18e7fc350
author Michal Simek <michal.simek@xilinx.com> 1539771372 +0200
committer Michal Simek <michal.simek@xilinx.com> 1541581651 +0100

arm: zynq: Setup non zero SPL FIT load address

Default setup is 0 which is incorrect place because it points to OCM
which is allocated for SPL only in our case.
Use address in DDR.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>