tree 7dde154edcf6ae53d9f856dae6a2fa065bb3b28e
parent 7e02233062db5a67601ed49c8596b7a10894ddc6
author Tudor Ambarus <tudor.ambarus@microchip.com> 1635958030 +0200
committer Eugen Hristev <eugen.hristev@microchip.com> 1638860122 +0200

spi: atmel-quadspi: Add support for SAMA7G5 QSPI

sama7g5 QSPI has:
1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to
   200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported
2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to
   90 MHz DDR/133 MHz SDR

The QSPI controller of SAMA7G5 uses different clock domains, hence extra
synchronization operations must be performed before accessing some
registers. Differentiate between the versions of the IP using has_gclk.
Differentiate between QSPI0 and QSPI1 with has_octal.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>