tree fab7529d9b9ac0b7f28fcbcd358c2ca52633311e
parent 5c23a8217565a69121930438612af29fa355db09
author vijay rai <vijay.rai@freescale.com> 1403241329 +0530
committer York Sun <yorksun@freescale.com> 1406071554 -0700

powerpc/t1040qds: Initialize EPHY2 clock to RGMII only

Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>