commit 8df4407a94c42b7951b799b947d13a6b49b34b18
author developer <developer@mediatek.com> Tue Jan 14 18:43:00 2025 +0800
committer Tom Rini <trini@konsulko.com> Tue Jan 21 09:28:43 2025 -0600
tree d8d7bac4712c4a9e7fb3468b3d58a1c04c3ebb83
parent c4f83e49e6bf009db444ba6c42230a0fd8fc0486

board: mediatek: mt7629: Migrate to OF_UPSTREAM

Move differences in DT files between upstream Linux DT and U-Boot DT to
mt7629-rfb-u-boot.dtsi.
Remove old copies of mt7629-related clock bindings, .dts, and .dtsi files.
Update defconfig to switch the whole mt7629 SoC to use OF_UPSTREAM.

arch/arm/dts/mt7629-rfb-u-boot.dtsi

diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
index 4117047..667c9c8 100644
--- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -5,6 +5,59 @@
  * Author: Weijie Gao <weijie.gao@mediatek.com>
  */
 
+#include <dt-bindings/reset/mt7629-reset.h>
+
+/ {
+	dramc: dramc@10203000 {
+		compatible = "mediatek,mt7629-dramc";
+		reg = <0x10203000 0x600>,	/* EMI */
+		      <0x10213000 0x1000>,	/* DDRPHY */
+		      <0x10214000 0xd00>;	/* DRAMC_AO */
+		clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
+			 <&topckgen CLK_TOP_SYSPLL1_D8>,
+			 <&topckgen CLK_TOP_MEM_SEL>,
+			 <&topckgen CLK_TOP_DMPLL>;
+		clock-names = "phy", "phy_mux", "mem", "mem_mux";
+	};
+
+	mcucfg: syscon@10200000 {
+		compatible = "mediatek,mt7629-mcucfg", "syscon";
+		reg = <0x10200000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	timer0: timer@10004000 {
+		compatible = "mediatek,timer";
+		reg = <0x10004000 0x80>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
+			 <&topckgen CLK_TOP_10M_SEL>;
+		clock-names = "mux", "src";
+	};
+
+	snand: snand@1100d000 {
+		compatible = "mediatek,mt7629-snand";
+		reg = <0x1100d000 0x1000>,
+		      <0x1100e000 0x1000>;
+		reg-names = "nfi", "ecc";
+		clocks = <&pericfg CLK_PERI_NFI_PD>,
+			 <&pericfg CLK_PERI_SNFI_PD>,
+			 <&pericfg CLK_PERI_NFIECC_PD>;
+		clock-names = "nfi_clk", "pad_clk", "ecc_clk";
+		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+				  <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+					 <&topckgen CLK_TOP_UNIVPLL2_D8>;
+		status = "disabled";
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&watchdog>;
+	};
+
+};
+
 &infracfg {
 	bootph-all;
 };
@@ -35,8 +88,72 @@
 
 &uart0 {
 	bootph-all;
+	reg-shift = <2>;
+	assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+};
+
+&qspi {
+	bootph-all;
+	compatible = "mediatek,mtk-snor";
+	reg = <0x11014000 0x1000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_pins>;
+	status = "okay";
+
+	/delete-node/ flash@0;
+
+	spi-flash@0{
+		bootph-all;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
 };
 
-&snfi {
+&pio {
 	bootph-all;
+	snfi_pins: snfi-pins {
+		mux {
+			bootph-all;
+			function = "flash";
+			groups = "snfi";
+		};
+	};
+	snor_pins: snor-pins {
+		mux {
+			bootph-all;
+			function = "flash";
+			groups = "spi_nor";
+		};
+	};
+};
+
+&snand {
+	pinctrl-names = "default";
+	pinctrl-0 = <&snfi_pins>;
+	status = "okay";
+	quad-spi;
+	bootph-all;
+};
+
+&eth {
+	resets = <&ethsys ETHSYS_FE_RST>;
+	reset-names = "fe";
+	status = "okay";
+	mediatek,gmac-id = <0>;
+	phy-mode = "2500base-x";
+	mediatek,switch = "mt7531";
+	reset-gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
+	assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
+			  <&topckgen CLK_TOP_F10M_REF_SEL>,
+			  <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
+	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+				 <&topckgen CLK_TOP_SYSPLL4_D16>,
+				 <&topckgen CLK_TOP_SGMIIPLL_D2>;
+	fixed-link {
+		speed = <2500>;
+		full-duplex;
+	};
 };