sunxi: video: Add A64/H3/H5 HDMI driver
This commit adds support for HDMI output.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 88c3f13..6aa5e91 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -18,6 +18,8 @@
#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
+#define SUNXI_DE2_BASE 0x01000000
+
#ifdef CONFIG_MACH_SUN8I_A83T
#define SUNXI_CPUCFG_BASE 0x01700000
#endif
@@ -46,7 +48,9 @@
#define SUNXI_USB1_BASE 0x01c14000
#endif
#define SUNXI_SS_BASE 0x01c15000
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
#define SUNXI_HDMI_BASE 0x01c16000
+#endif
#define SUNXI_SPI2_BASE 0x01c17000
#define SUNXI_SATA_BASE 0x01c18000
#ifdef CONFIG_SUNXI_GEN_SUN4I
@@ -164,6 +168,10 @@
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE 0x01ee0000
+#endif
+
#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
new file mode 100644
index 0000000..b5875f9
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -0,0 +1,124 @@
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * Based on out of tree Linux DRM driver defines:
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DISPLAY2_H
+#define _SUNXI_DISPLAY2_H
+
+/* internal clock settings */
+struct de_clk {
+ u32 gate_cfg;
+ u32 bus_cfg;
+ u32 rst_cfg;
+ u32 div_cfg;
+ u32 sel_cfg;
+};
+
+/* global control */
+struct de_glb {
+ u32 ctl;
+ u32 status;
+ u32 dbuff;
+ u32 size;
+};
+
+/* alpha blending */
+struct de_bld {
+ u32 fcolor_ctl;
+ struct {
+ u32 fcolor;
+ u32 insize;
+ u32 offset;
+ u32 dum;
+ } attr[4];
+ u32 dum0[15];
+ u32 route;
+ u32 premultiply;
+ u32 bkcolor;
+ u32 output_size;
+ u32 bld_mode[4];
+ u32 dum1[4];
+ u32 ck_ctl;
+ u32 ck_cfg;
+ u32 dum2[2];
+ u32 ck_max[4];
+ u32 dum3[4];
+ u32 ck_min[4];
+ u32 dum4[3];
+ u32 out_ctl;
+};
+
+/* VI channel */
+struct de_vi {
+ struct {
+ u32 attr;
+ u32 size;
+ u32 coord;
+ u32 pitch[3];
+ u32 top_laddr[3];
+ u32 bot_laddr[3];
+ } cfg[4];
+ u32 fcolor[4];
+ u32 top_haddr[3];
+ u32 bot_haddr[3];
+ u32 ovl_size[2];
+ u32 hori[2];
+ u32 vert[2];
+};
+
+struct de_ui {
+ struct {
+ u32 attr;
+ u32 size;
+ u32 coord;
+ u32 pitch;
+ u32 top_laddr;
+ u32 bot_laddr;
+ u32 fcolor;
+ u32 dum;
+ } cfg[4];
+ u32 top_haddr;
+ u32 bot_haddr;
+ u32 ovl_size;
+};
+
+/*
+ * DE register constants.
+ */
+#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
+#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
+
+#define SUNXI_DE2_MUX_GLB_REGS 0x00000
+#define SUNXI_DE2_MUX_BLD_REGS 0x01000
+#define SUNXI_DE2_MUX_CHAN_REGS 0x02000
+#define SUNXI_DE2_MUX_CHAN_SZ 0x1000
+#define SUNXI_DE2_MUX_VSU_REGS 0x20000
+#define SUNXI_DE2_MUX_GSU1_REGS 0x30000
+#define SUNXI_DE2_MUX_GSU2_REGS 0x40000
+#define SUNXI_DE2_MUX_GSU3_REGS 0x50000
+#define SUNXI_DE2_MUX_FCE_REGS 0xa0000
+#define SUNXI_DE2_MUX_BWS_REGS 0xa2000
+#define SUNXI_DE2_MUX_LTI_REGS 0xa4000
+#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000
+#define SUNXI_DE2_MUX_ASE_REGS 0xa8000
+#define SUNXI_DE2_MUX_FCC_REGS 0xaa000
+#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000
+
+#define SUNXI_DE2_FORMAT_XRGB_8888 4
+#define SUNXI_DE2_FORMAT_RGB_565 10
+
+#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)
+
+#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1))
+
+#endif /* _SUNXI_DISPLAY2_H */