commit 8d56db90bc84eeae7c9d24dc2251a9dc2eb29f53
author Robert P. J. Day <rpjday@crashcourse.ca> Fri Jul 15 13:44:45 2016 -0400
committer Tom Rini <trini@konsulko.com> Sat Jul 16 09:43:12 2016 -0400
tree 7336b817a5d03f1594bc4b8c89c9545578f72d4c
parent c67c0d9c4f75165ecd8597f555c640800447c447

Various, unrelated tree-wide typo fixes.

    Fix a number of typos, including:

     * "compatble" -> "compatible"
     * "eanbeld" -> "enabled"
     * "envrionment" -> "environment"
     * "FTD" -> "FDT" (for "flattened device tree")
     * "ommitted" -> "omitted"
     * "overriden" -> "overridden"
     * "partiton" -> "partition"
     * "propogate" -> "propagate"
     * "resourse" -> "resource"
     * "rest in piece" -> "rest in peace"
     * "suport" -> "support"
     * "varible" -> "variable"

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>

arch/powerpc/cpu/ppc4xx/start.S

diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index b432b18..5647d71 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -144,7 +144,7 @@
 #endif
 
 /*
- * Unless otherwise overriden, enable two 128MB cachable instruction regions
+ * Unless otherwise overridden, enable two 128MB cachable instruction regions
  * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
  * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
  */