commit 8cb251add60bd6993bfd8de85e3c891fab05c8bf
author Stefan Roese <sr@denx.de> Sun Sep 12 06:21:37 2010 +0200
committer Stefan Roese <sr@denx.de> Thu Sep 23 09:02:05 2010 +0200
tree a5e131d0d7f62e41bd9bc1c767452b43b75bf82e
parent 95ca5fac843ceb179b17a1a4f93b66e6bce23140

ppc4xx: Big header cleanup part 2, mostly PPC405 related

This cleanup is done by creating header files for all SoC versions and
moving the SoC specific defines into these special headers. This way the
common header ppc405.h and ppc440.h can be cleaned up finally.

As a part from this cleanup, the GPIO definitions for PPC405EP are
corrected. The high and low parts of the registers (for example
CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in
the wrong order. This patch now fixes this issue by switching these
xxxH and xxxL values. This brings the GPIO 405EP port in sync with all
other PPC4xx ports.

Signed-off-by: Stefan Roese <sr@denx.de>

include/configs/G2000.h

diff --git a/include/configs/G2000.h b/include/configs/G2000.h
index d2883eb..4d29f21 100644
--- a/include/configs/G2000.h
+++ b/include/configs/G2000.h
@@ -367,12 +367,12 @@
  *
  * following GPIO setting changed for G20000, 080304
  */
-#define CONFIG_SYS_GPIO0_OSRH          0x40005555
-#define CONFIG_SYS_GPIO0_OSRL          0x40000110
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
-#define CONFIG_SYS_GPIO0_ISR1L         0x15555445
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_OSRL          0x40005555
+#define CONFIG_SYS_GPIO0_OSRH          0x40000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
 #define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 
 /*