ARM: dts: stm32: DT alignment with kernel v5.4-rc4
Device tree and binding alignment with kernel v5.4-rc4
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
index c9087f5..ba5cb74 100644
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for the STM32F7 RCC IP
*/
diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h
index b96b3c3..06e8476 100644
--- a/include/dt-bindings/mfd/stm32h7-rcc.h
+++ b/include/dt-bindings/mfd/stm32h7-rcc.h
@@ -12,6 +12,7 @@
#define STM32H7_RCC_AHB3_FMC 12
#define STM32H7_RCC_AHB3_QUADSPI 14
#define STM32H7_RCC_AHB3_SDMMC1 16
+#define STM32H7_RCC_AHB3_CPU 31
#define STM32H7_RCC_AHB3_CPU1 31
#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
@@ -56,7 +57,6 @@
#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
-
/* APB3 */
#define STM32H7_RCC_APB3_LTDC 3
#define STM32H7_RCC_APB3_DSI 4