commit 8c695515557ed6ea57b5ae2af4656ac0675f854e
author Stefan Roese <sr@denx.de> Mon Nov 07 13:43:06 2005 +0100
committer Stefan Roese <sr@denx.de> Mon Nov 07 13:43:06 2005 +0100
tree 2e8ac8dda39303adbc03412730e9a561f2ea0039
parent 259e119af755d7330e437b00baa66b3e08b0c5cd

Fix MPC85xx PCI support (pci_register_hose() before pci config access)
Patch by Stefan Roese, 07 Nov 2005

cpu/mpc85xx/pci.c

diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 069fe4e..a94493e 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -61,16 +61,6 @@
 			   (CFG_IMMR+0x8000),
 			   (CFG_IMMR+0x8004));
 
-	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
-	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-
 	pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
 	pcix->potear1  = 0x00000000;
 	pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
@@ -93,6 +83,16 @@
 	 */
 	pci_register_hose(hose);
 
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+
 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
 	/*
 	 * This is a SW workaround for an apparent HW problem