imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 494ddb0..ccd977f 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -187,7 +187,7 @@
}
}
-void cgc2_pll4_init(void)
+void cgc2_pll4_init(bool pll4_reset)
{
/* Disable PFD DIV and clear DIV */
writel(0x80808080, &cgc2_regs->pll4div_pfd0);
@@ -196,16 +196,18 @@
/* Gate off and clear PFD */
writel(0x80808080, &cgc2_regs->pll4pfdcfg);
- /* Disable PLL4 */
- writel(0x0, &cgc2_regs->pll4csr);
+ if (pll4_reset) {
+ /* Disable PLL4 */
+ writel(0x0, &cgc2_regs->pll4csr);
- /* Configure PLL4 to 528Mhz and clock source from SOSC */
- writel(22 << 16, &cgc2_regs->pll4cfg);
- writel(0x1, &cgc2_regs->pll4csr);
+ /* Configure PLL4 to 528Mhz and clock source from SOSC */
+ writel(22 << 16, &cgc2_regs->pll4cfg);
+ writel(0x1, &cgc2_regs->pll4csr);
- /* wait for PLL4 output valid */
- while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
- ;
+ /* wait for PLL4 output valid */
+ while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
+ ;
+ }
/* Enable all 4 PFDs */
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 4697157..69cccaf 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -101,7 +101,7 @@
writel(0xc0000000, PCC5_LPDDR4_ADDR);
/* enable pll4 and ddrclk*/
- cgc2_pll4_init();
+ cgc2_pll4_init(true);
cgc2_ddrclk_config(4, 1);
/* enable ddr pcc */