Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
For 2022.01
-----------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083
- Fix UART
- moved to binman (MX8 boards)
- Toradex: sync DTS with Linux
- Gateworks: fixes
- New boards : MSC SM2S iMX8MP
diff --git a/Kconfig b/Kconfig
index 43d4a48..67f4646 100644
--- a/Kconfig
+++ b/Kconfig
@@ -583,6 +583,17 @@
default 0x10000 if TARGET_TRICORDER
default 0x0
+config SYS_MONITOR_LEN
+ int "Maximum size in bytes reserved for U-Boot in memory"
+ default 1048576 if X86
+ default 0
+ help
+ Size of memory reserved for monitor code, used to determine
+ _at_compile_time_ (!) if the environment is embedded within the
+ U-Boot image, or in a separate flash sector, among other uses where
+ we need to set a maximum size of the U-Boot binary itself that will
+ be loaded.
+
config MP
bool "Support for multiprocessor"
help
diff --git a/README b/README
index ec1b50c..d75c3fb 100644
--- a/README
+++ b/README
@@ -298,7 +298,7 @@
Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
@@ -314,7 +314,7 @@
See Freescale App Note 4493 for more information about
this erratum.
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
@@ -330,7 +330,7 @@
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
- CONFIG_SYS_FSL_DDR_ADDR
+ CFG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV
@@ -339,7 +339,7 @@
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+ CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
@@ -435,15 +435,6 @@
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
-- Serial Download Echo Mode:
- CONFIG_LOADS_ECHO
- If defined to 1, all characters received during a
- serial download (using the "loads" command) are
- echoed back. This might be needed by some terminal
- emulations (like "cu"), but may as well just take
- time on others. This setting #define's the initial
- value of the "loads_echo" environment variable.
-
- Removal of commands
If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line
@@ -762,11 +753,6 @@
entering dfuMANIFEST state. Host waits this timeout, before
sending again an USB request to the device.
-- Journaling Flash filesystem support:
- CONFIG_SYS_JFFS2_FIRST_SECTOR,
- CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
- Define these for a default partition on a NOR device
-
- Keyboard Support:
See Kconfig help for available keyboard drivers.
@@ -1052,17 +1038,6 @@
You should define these to the GPIO value as given directly to
the generic GPIO functions.
- CONFIG_SYS_I2C_INIT_BOARD
-
- When a board is reset during an i2c bus transfer
- chips might think that the current transfer is still
- in progress. On some boards it is possible to access
- the i2c SCLK line directly, either by using the
- processor pin as a GPIO or by having a second pin
- connected to the bus. If this option is defined a
- custom i2c_init_board() routine in boards/xxx/board.c
- is run early in the boot sequence.
-
CONFIG_I2C_MULTI_BUS
This option allows the use of multiple I2C buses, each of which
@@ -1471,21 +1446,12 @@
the RAM base is not zero, or RAM is divided into banks,
this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_LOADS_BAUD_CHANGE:
- Enable temporary baudrate change while serial download
-
- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
-- CONFIG_SYS_MONITOR_LEN:
- Size of memory reserved for monitor code, used to
- determine _at_compile_time_ (!) if the environment is
- embedded within the U-Boot image, or in a separate
- flash sector.
-
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
@@ -1507,25 +1473,6 @@
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC).
-- CONFIG_SYS_NONCACHED_MEMORY:
- Size of non-cached memory area. This area of memory will be
- typically located right below the malloc() area and mapped
- uncached in the MMU. This is useful for drivers that would
- otherwise require a lot of explicit cache maintenance. For
- some drivers it's also impossible to properly maintain the
- cache. For example if the regions that need to be flushed
- are not a multiple of the cache-line size, *and* padding
- cannot be allocated between the regions to align them (i.e.
- if the HW requires a contiguous array of regions, and the
- size of each region is not cache-aligned), then a flush of
- one region may result in overwriting data that hardware has
- written to another region in the same cache-line. This can
- happen for example in network drivers where descriptors for
- buffers are typically smaller than the CPU cache-line (e.g.
- 16 bytes vs. 32 or 64 bytes).
-
- Non-cached memory is only supported on 32-bit ARM at present.
-
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
@@ -1751,9 +1698,6 @@
- CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing
-- CONFIG_SYS_MAMR_PTA:
- periodic timer for refresh
-
- CONFIG_SYS_SRIO:
Chip has SRIO or not
diff --git a/api/Kconfig b/api/Kconfig
index 382aa4a..eb8d5d0 100644
--- a/api/Kconfig
+++ b/api/Kconfig
@@ -5,4 +5,9 @@
help
This option enables the U-Boot API. See api/README for more information.
+config SYS_MMC_MAX_DEVICE
+ int "Maximum number of MMC devices exposed via the API"
+ depends on API
+ default 1
+
endmenu
diff --git a/api/api_storage.c b/api/api_storage.c
index adca44b..997e872 100644
--- a/api/api_storage.c
+++ b/api/api_storage.c
@@ -44,10 +44,6 @@
static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
-#ifndef CONFIG_SYS_MMC_MAX_DEVICE
-#define CONFIG_SYS_MMC_MAX_DEVICE 1
-#endif
-
void dev_stor_init(void)
{
#if defined(CONFIG_IDE)
diff --git a/arch/Kconfig b/arch/Kconfig
index e3a456a..ae39716 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -438,6 +438,30 @@
normal CP15 init (such as enabling the instruction cache) is still
performed.
+config SYS_HAS_NONCACHED_MEMORY
+ bool "Enable reserving a non-cached memory area for drivers"
+ depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
+ help
+ This is useful for drivers that would otherwise require a lot of
+ explicit cache maintenance. For some drivers it's also impossible to
+ properly maintain the cache. For example if the regions that need to
+ be flushed are not a multiple of the cache-line size, *and* padding
+ cannot be allocated between the regions to align them (i.e. if the
+ HW requires a contiguous array of regions, and the size of each
+ region is not cache-aligned), then a flush of one region may result
+ in overwriting data that hardware has written to another region in
+ the same cache-line. This can happen for example in network drivers
+ where descriptors for buffers are typically smaller than the CPU
+ cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
+
+config SYS_NONCACHED_MEMORY
+ hex "Size in bytes of the non-cached memory area"
+ depends on SYS_HAS_NONCACHED_MEMORY
+ default 0x100000
+ help
+ Size of non-cached memory area. This area of memory will be typically
+ located right below the malloc() area and mapped uncached in the MMU.
+
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 86b5b21..4e1fe28 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -15,8 +15,8 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 0b3e3b2..d530e06 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -228,7 +228,7 @@
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr);
}
@@ -237,7 +237,7 @@
int print_cpuinfo(void)
{
char buf1[32], buf2[32];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr);
@@ -316,7 +316,7 @@
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
icache_enable();
@@ -355,7 +355,7 @@
/* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr);
}
@@ -363,7 +363,7 @@
/* Release the secondary core from holdoff state and kick it */
void smp_kick_all_cpus(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 83f9882..c01cebb 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -92,7 +92,7 @@
int off;
int val;
const char *sysclk_path;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
@@ -105,7 +105,7 @@
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index caf51e1..f74d819 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -39,7 +39,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
@@ -74,7 +74,7 @@
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
@@ -103,14 +103,14 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR +
+ CFG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
RCWSR4_SRDS2_PRTCL_SHIFT);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 28a7945..b4d113d 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -31,7 +31,7 @@
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
out_le32(&scfg->sparecr[2], dest);
@@ -57,8 +57,8 @@
static void __secure ls1_deepsleep_irq_cfg(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */
@@ -120,8 +120,8 @@
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000);
@@ -155,9 +155,9 @@
static void __secure ls1_deep_sleep(u32 entry_point)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
@@ -213,8 +213,8 @@
#else
static void __secure ls1_sleep(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3956178..e7c4fbf 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -129,8 +129,8 @@
mov r1, r4
@ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR]
@@ -141,8 +141,8 @@
@ Reset target CPU
@ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+ movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
+ movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset
movw r5, #0
@@ -216,8 +216,8 @@
mov r1, r4
@ Get RCPM base address
- movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@@ -236,8 +236,8 @@
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
- movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 728efc4..1dafa3c 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -54,7 +54,7 @@
unsigned int get_soc_major_rev(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major;
svr = in_be32(&gur->svr);
@@ -113,7 +113,7 @@
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -129,7 +129,7 @@
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */
@@ -161,7 +161,7 @@
int arch_soc_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 487c0ed..c11341a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -96,11 +96,11 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
@@ -159,7 +159,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -168,7 +168,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@@ -204,7 +204,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -213,12 +213,12 @@
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -333,7 +333,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -342,7 +342,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -401,7 +401,7 @@
void cpu_name(char *name)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver;
svr = gur_in32(&gur->svr);
@@ -430,7 +430,7 @@
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
- * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@@ -443,7 +443,7 @@
/* global data is already setup, no allocation yet */
if (el == 3)
- gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
@@ -466,7 +466,7 @@
#ifdef CONFIG_ARCH_LS2080A
unsigned int i;
u32 svr, ver;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
@@ -775,7 +775,7 @@
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#endif
if (current_el() == 2) {
@@ -863,7 +863,7 @@
u32 initiator_type(u32 cluster, int init_id)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = 0;
@@ -876,7 +876,7 @@
u32 cpu_pos_mask(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0;
u32 cluster, type, mask = 0;
@@ -897,7 +897,7 @@
u32 cpu_mask(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type, mask = 0;
@@ -930,7 +930,7 @@
int fsl_qoriq_core_to_cluster(unsigned int core)
{
struct ccsr_gur __iomem *gur =
- (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster;
@@ -954,7 +954,7 @@
u32 fsl_qoriq_core_to_type(unsigned int core)
{
struct ccsr_gur __iomem *gur =
- (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type;
@@ -979,7 +979,7 @@
#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
@@ -988,7 +988,7 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
@@ -1179,9 +1179,9 @@
int timer_init(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_FSL_LSCH3
- u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+ u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
#endif
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
@@ -1230,7 +1230,7 @@
}
#if !CONFIG_IS_ENABLED(SYSRESET)
-__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void)
{
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 427de1c..ee73457 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -171,9 +171,9 @@
{
int offset, err;
u64 reg[8];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int val;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int align_64k = 0;
val = gur_in32(&gur->svr);
@@ -355,7 +355,7 @@
static void fdt_fixup_msi(void *blob)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int rev;
rev = gur_in32(&gur->svr);
@@ -620,7 +620,7 @@
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
@@ -635,7 +635,7 @@
fdt_fixup_kaslr(blob);
#endif
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index 60769e1..1541dfb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -40,7 +40,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]);
int i;
@@ -76,7 +76,7 @@
int get_serdes_protocol(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -101,7 +101,7 @@
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@@ -142,7 +142,7 @@
int setup_serdes_volt(u32 svdd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes *serdes1_base;
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes *serdes2_base;
@@ -168,7 +168,7 @@
if (svdd_cur == svdd_tar)
return 0;
- serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
+ serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_base = (void *)serdes1_base + 0x10000;
#endif
@@ -406,14 +406,14 @@
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 898ed09..6440ce7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -20,7 +20,7 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
@@ -29,7 +29,7 @@
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 181bd9c..c0efc34 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -86,7 +86,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = 0;
int i;
@@ -134,7 +134,7 @@
void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@@ -399,18 +399,18 @@
int setup_serdes_volt(u32 svdd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes __iomem *serdes1_base =
- (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes __iomem *serdes2_base =
- (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+ (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
struct ccsr_serdes __iomem *serdes3_base =
- (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
+ (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
#endif
u32 cfg_tmp;
@@ -585,7 +585,7 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@@ -593,7 +593,7 @@
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@@ -601,7 +601,7 @@
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
serdes_init(NXP_SRDS_3,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
FSL_CHASSIS3_SRDS3_REGSR,
FSL_CHASSIS3_SRDS3_PRTCL_MASK,
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@@ -611,7 +611,7 @@
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char scfg[16], snum[16];
int cfgr = 0;
u32 cfg;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 58080d0..137778d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -23,13 +23,13 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
- (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
- (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+ (void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+ (void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
};
struct ccsr_clk_ctrl __iomem *clk_ctrl =
- (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+ (void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[16] = {
[0] = 0, /* CC1 PPL / 1 */
@@ -68,7 +68,7 @@
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = get_board_sys_clk();
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 2d87281..e972603 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -27,7 +27,7 @@
void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
- ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) {
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 87410c7..4358c6e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -325,8 +325,8 @@
ENTRY(fsl_clear_ocram)
/* Clear OCRAM */
- ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
- ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
+ ldr x0, =CFG_SYS_FSL_OCRAM_BASE
+ ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
mov x2, #0
clear_loop:
str x2, [x0]
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 26f8a49..fe667f0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -53,7 +53,7 @@
bool soc_has_mac1(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
unsigned int version = SVR_SOC_VER(svr);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 7222119..ce0c46a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -48,8 +48,8 @@
#ifdef CONFIG_FSL_LSCH3
static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 mpidr = 0;
mpidr = ((cluster << 8) | core);
@@ -73,13 +73,13 @@
int fsl_layerscape_wake_seconday_cores(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3
- struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 svr, ver, cluster, type;
int j = 0, cluster_cores = 0;
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+ struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b9894d4..117b7a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -253,7 +253,7 @@
#endif
#ifdef CONFIG_FSL_LSCH3
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
@@ -261,7 +261,7 @@
loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+ struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 515dbe0..89a6262 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -80,7 +80,7 @@
bool soc_has_dp_ddr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A, LS2088A, LS2048A has DP_DDR */
@@ -94,7 +94,7 @@
bool soc_has_aiop(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */
@@ -249,13 +249,13 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
-#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
@@ -271,8 +271,8 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
#endif
#endif
@@ -412,7 +412,7 @@
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@@ -462,7 +462,7 @@
static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
- u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042);
#endif
}
@@ -473,7 +473,7 @@
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
if (current_el() < 3)
@@ -493,7 +493,7 @@
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* Skip if running at lower exception level */
@@ -526,21 +526,21 @@
static void erratum_a010539(void)
{
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 porsr1;
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
- out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
+ out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
}
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@@ -588,7 +588,7 @@
#ifdef CONFIG_SYS_FSL_DDR
static void ddr_enable_0v9_volt(bool en)
{
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
tmp = ddr_in32(&ddr->ddr_cdr1);
@@ -629,7 +629,7 @@
#ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecccr2;
out_be32(&scfg->pfeasbcr,
@@ -653,7 +653,7 @@
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
enum boot_src src;
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5824778..ff752c2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -24,7 +24,7 @@
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
@@ -32,9 +32,9 @@
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -95,7 +95,7 @@
#define EPU_EPGCR 0x700060000ULL
#elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
@@ -126,9 +126,9 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* LX2160A/LX2162A Soc Support */
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@@ -139,13 +139,13 @@
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -161,7 +161,7 @@
/* DCFG - GUR */
#elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
@@ -180,9 +180,9 @@
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -200,9 +200,9 @@
/* DCFG - GUR */
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define DCSR_DCFG_SBEESR2 0x20140534
#define DCSR_DCFG_MBEESR2 0x20140544
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c51b65e..4db4791 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -10,7 +10,7 @@
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
@@ -19,7 +19,7 @@
#endif
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
@@ -73,7 +73,7 @@
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 8af0d35..9cddb41 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -70,7 +70,7 @@
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
- offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+ offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@@ -83,7 +83,7 @@
#define SET_SDHC_ICID(streamid) \
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
- CONFIG_SYS_FSL_ESDHC_ADDR)
+ CFG_SYS_FSL_ESDHC_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@@ -102,14 +102,14 @@
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
- CONFIG_SYS_FSL_QMAN_ADDR, \
- CONFIG_SYS_FSL_QMAN_ADDR, false)
+ CFG_SYS_FSL_QMAN_ADDR, \
+ CFG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
- CONFIG_SYS_FSL_BMAN_ADDR, \
- CONFIG_SYS_FSL_BMAN_ADDR, false)
+ CFG_SYS_FSL_BMAN_ADDR, \
+ CFG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
@@ -119,8 +119,8 @@
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, \
- CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, \
+ CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
extern struct fman_icid_id_table fman_icid_tbl[];
extern int fman_icid_tbl_sz;
@@ -137,7 +137,7 @@
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, streamid, \
- offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
compataddr, GUR_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@@ -180,24 +180,24 @@
SET_ICID_ENTRY( \
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
(FSL_SEC_JR##jr_num##_OFFSET == \
- SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
? NULL \
: "fsl,sec-v4.0-job-ring"), \
streamid, \
SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, \
+ CFG_SYS_FSL_SEC_ADDR, \
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[];
extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2b73647..e8bd8d2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -14,18 +14,18 @@
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
-#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
-#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
-#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
+#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
+#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
@@ -65,7 +65,7 @@
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
@@ -165,24 +165,24 @@
unsigned long freq_qman;
};
-#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
+#define CFG_SYS_FSL_FM1_OFFSET 0xa00000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
-#define CONFIG_SYS_FSL_FM1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
+#define CFG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
-#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull
+#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull
+#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x720000ull
#define FSL_SEC_JR2_OFFSET 0x730000ull
#define FSL_SEC_JR3_OFFSET 0x740000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 570397b..f1ffb23 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -9,19 +9,19 @@
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CFG_SYS_FSL_DDR3_ADDR 0x08210000
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
#else
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#endif
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#ifndef CONFIG_NXP_LSCH3_2
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#else
@@ -29,8 +29,8 @@
#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
#endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
-#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
@@ -38,20 +38,20 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
+#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
0x18A0)
-#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
-#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
+#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
+#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
@@ -108,16 +108,16 @@
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
-#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
+#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull
+#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x07020000ull
#define FSL_SEC_JR2_OFFSET 0x07030000ull
#define FSL_SEC_JR3_OFFSET 0x07040000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 3d32b7a..f569162 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -47,6 +47,6 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
-#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 6595d97..20f4699 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -91,12 +91,12 @@
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
-#define CONFIG_SYS_FSL_SEC_OFFSET (0)
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET (0)
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 0e32828..e85918e 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -17,25 +17,25 @@
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
+#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
-#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
+#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
+#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
+#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index 93b0a26..fb5ded8 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -29,30 +29,30 @@
#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, 0)
+ CFG_SYS_FSL_SEC_OFFSET, 0)
struct liodn_id_table {
const char *compat;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 56b3a58..72944af 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -238,12 +238,12 @@
#endif
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 1e9d11b..c863cd9 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -215,12 +215,12 @@
#define FEC_QUIRK_ENET_MAC
#define SNVS_LPGPR 0x68
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index ffa170f..33a699f 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -228,12 +228,12 @@
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 04c4b20..b65bf87 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -40,7 +40,7 @@
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index ec8a875..9576b48 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -41,7 +41,7 @@
/* Enable HAB clock */
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 304a030..88f6fe0 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -30,9 +30,9 @@
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6191153..37d8565 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -18,9 +18,9 @@
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#endif
#endif
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index b729187..0e81cc8 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -21,21 +21,21 @@
{
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#else
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c
index 4f77a3d..a895506 100644
--- a/arch/arm/mach-mediatek/mt7981/init.c
+++ b/arch/arm/mach-mediatek/mt7981/init.c
@@ -8,6 +8,7 @@
#include <asm/armv8/mmu.h>
#include <asm/system.h>
#include <asm/global_data.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c
index 0fd4596..cf89e63 100644
--- a/arch/arm/mach-mediatek/mt7986/init.c
+++ b/arch/arm/mach-mediatek/mt7986/init.c
@@ -8,6 +8,7 @@
#include <asm/armv8/mmu.h>
#include <asm/system.h>
#include <asm/global_data.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c
index b7050df..5a21e9a 100644
--- a/arch/arm/mach-mediatek/mt8512/init.c
+++ b/arch/arm/mach-mediatek/mt8512/init.c
@@ -21,6 +21,7 @@
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8512-clk.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index a49cd1b..6416252 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -36,7 +36,7 @@
# Retrieve the scan chain lengths
fix_newlines_in_macros \
${in_bsp_dir}/generated/iocsr_config_${soc}.h |
- grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
+ grep 'CFG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
echo ""
@@ -115,7 +115,7 @@
# Retrieve the pll config and zap parenthesis
fix_newlines_in_macros \
${in_bsp_dir}/generated/pll_config.h |
- sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
+ sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
cat << EOF
@@ -128,7 +128,7 @@
# Filter out only the macros which are actually used by the code
#
grep_sdram_config() {
- egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
+ egrep "#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
}
#
@@ -161,7 +161,7 @@
fix_newlines_in_macros \
${in_bsp_dir}/generated/sdram/sdram_config.h |
sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
- sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
+ sed -n '/CFG_HPS/ !b; :next {/CFG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
sort -u | grep_sdram_config
echo ""
diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c
index f810fad..ce86f04 100644
--- a/arch/arm/mach-socfpga/wrap_iocsr_config.c
+++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c
@@ -17,19 +17,19 @@
switch (chain_id) {
case 0:
*table = iocsr_scan_chain0_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+ *table_len = CFG_HPS_IOCSR_SCANCHAIN0_LENGTH;
break;
case 1:
*table = iocsr_scan_chain1_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+ *table_len = CFG_HPS_IOCSR_SCANCHAIN1_LENGTH;
break;
case 2:
*table = iocsr_scan_chain2_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+ *table_len = CFG_HPS_IOCSR_SCANCHAIN2_LENGTH;
break;
case 3:
*table = iocsr_scan_chain3_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+ *table_len = CFG_HPS_IOCSR_SCANCHAIN3_LENGTH;
break;
default:
return -EINVAL;
diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c
index bd631e0..0c40ae98 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config.c
@@ -8,116 +8,116 @@
#include <qts/pll_config.h>
#define MAIN_VCO_BASE ( \
- (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
+ (CFG_HPS_MAINPLLGRP_VCO_DENOM << \
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
+ (CFG_HPS_MAINPLLGRP_VCO_NUMER << \
CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
)
#define PERI_VCO_BASE ( \
- (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
+ (CFG_HPS_PERPLLGRP_VCO_PSRC << \
CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
+ (CFG_HPS_PERPLLGRP_VCO_DENOM << \
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
+ (CFG_HPS_PERPLLGRP_VCO_NUMER << \
CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
)
#define SDR_VCO_BASE ( \
- (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
+ (CFG_HPS_SDRPLLGRP_VCO_SSRC << \
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
+ (CFG_HPS_SDRPLLGRP_VCO_DENOM << \
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
+ (CFG_HPS_SDRPLLGRP_VCO_NUMER << \
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
)
static const struct cm_config cm_default_cfg = {
/* main group */
MAIN_VCO_BASE,
- (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+ (CFG_HPS_MAINPLLGRP_MPUCLK_CNT <<
CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+ (CFG_HPS_MAINPLLGRP_MAINCLK_CNT <<
CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+ (CFG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+ (CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+ (CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+ (CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+ (CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+ (CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+ (CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+ (CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+ (CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+ (CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+ (CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+ (CFG_HPS_MAINPLLGRP_L4SRC_L4MP <<
CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+ (CFG_HPS_MAINPLLGRP_L4SRC_L4SP <<
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */
PERI_VCO_BASE,
- (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+ (CFG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+ (CFG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+ (CFG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+ (CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+ (CFG_HPS_PERPLLGRP_PERBASECLK_CNT <<
CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+ (CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+ (CFG_HPS_PERPLLGRP_DIV_USBCLK <<
CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+ (CFG_HPS_PERPLLGRP_DIV_SPIMCLK <<
CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+ (CFG_HPS_PERPLLGRP_DIV_CAN0CLK <<
CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+ (CFG_HPS_PERPLLGRP_DIV_CAN1CLK <<
CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+ (CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+ (CFG_HPS_PERPLLGRP_SRC_QSPI <<
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+ (CFG_HPS_PERPLLGRP_SRC_NAND <<
CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+ (CFG_HPS_PERPLLGRP_SRC_SDMMC <<
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */
SDR_VCO_BASE,
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+ (CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+ (CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+ (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+ (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+ (CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+ (CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+ (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+ (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
/* altera group */
- CONFIG_HPS_ALTERAGRP_MPUCLK,
+ CFG_HPS_ALTERAGRP_MPUCLK,
};
const struct cm_config * const cm_get_default_config(void)
@@ -128,19 +128,19 @@
const unsigned int cm_get_osc_clk_hz(const int osc)
{
if (osc == 1)
- return CONFIG_HPS_CLK_OSC1_HZ;
+ return CFG_HPS_CLK_OSC1_HZ;
else if (osc == 2)
- return CONFIG_HPS_CLK_OSC2_HZ;
+ return CFG_HPS_CLK_OSC2_HZ;
else
return 0;
}
const unsigned int cm_get_f2s_per_ref_clk_hz(void)
{
- return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ return CFG_HPS_CLK_F2S_PER_REF_HZ;
}
const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
{
- return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+ return CFG_HPS_CLK_F2S_SDR_REF_HZ;
}
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 4ea32e7..cd3a0f6 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -12,180 +12,180 @@
static const struct socfpga_sdram_config sdram_config = {
.ctrl_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
.dram_timing1 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
.dram_timing2 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
.dram_timing3 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
.dram_timing4 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
.lowpwr_timing =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
.dram_odt =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
SDR_CTRLGRP_DRAMODT_READ_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
.extratime1 =
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+ (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+ (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+ (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
#endif
.dram_addrw =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
- ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ ((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
.dram_if_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
.dram_dev_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
.dram_intr =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
.lowpwr_eq =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+ (CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
.static_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ (CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ (CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
.ctrl_width =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
.cport_width =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
.cport_wmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
.cport_rmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
.rfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+ (CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
.wfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+ (CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
.cport_rdwr =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
.port_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+ (CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
- .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+ .fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
.fifo_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ (CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ (CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
.mp_priority =
- (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+ (CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
.mp_weight0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
.mp_weight1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
.mp_weight2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
.mp_weight3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
.mp_pacing0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
.mp_pacing1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
.mp_pacing2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
.mp_pacing3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
.mp_threshold0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
.mp_threshold1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+ (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
.mp_threshold2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
- .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+ .phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
};
static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
@@ -202,7 +202,7 @@
.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
.idle_loop1 = RW_MGR_IDLE_LOOP1,
.idle_loop2 = RW_MGR_IDLE_LOOP2,
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
.emr = RW_MGR_EMR,
.emr2 = RW_MGR_EMR2,
.emr3 = RW_MGR_EMR3,
@@ -213,7 +213,7 @@
.mr_user = RW_MGR_MR_USER,
.mr_dll_reset = RW_MGR_MR_DLL_RESET,
.emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE,
-#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
+#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
.activate_1 = RW_MGR_ACTIVATE_1,
.idle = RW_MGR_IDLE,
.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
@@ -287,7 +287,7 @@
};
static const struct socfpga_sdram_misc_config misc_config = {
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
.afi_clk_freq = AFI_CLK_FREQ,
#endif
.afi_rate_ratio = AFI_RATE_RATIO,
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3b518c2..c355a95 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -40,6 +40,10 @@
Enable BATs (block address translation registers) 4-7 on machines
that support them.
+config SYS_INIT_RAM_LOCK
+ bool "Lock some portion of L1 for initial ram stack"
+ depends on MPC83xx || MPC85xx
+
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 27f069a..24d3f1f 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -113,6 +113,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select SUPPORT_TPL
+ select SYS_L2_SIZE_256KB
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
@@ -123,6 +124,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select SUPPORT_TPL
+ select SYS_L2_SIZE_256KB
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
@@ -132,6 +134,7 @@
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
+ select SYS_L2_SIZE_256KB
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
@@ -141,6 +144,7 @@
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
+ select SYS_L2_SIZE_256KB
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
@@ -150,6 +154,7 @@
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P2020
+ select SYS_L2_SIZE_512KB
imply CMD_EEPROM
imply CMD_SATA
imply SATA_SIL
@@ -160,6 +165,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select FSL_CORENET
select PHYS_64BIT
+ select SYS_L3_SIZE_1024KB
imply CMD_SATA
imply FSL_SATA
@@ -177,6 +183,7 @@
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
+ select SYS_L3_SIZE_256KB
imply CMD_EEPROM
imply PANIC_HANG
@@ -186,6 +193,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_256KB
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -193,6 +201,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_256KB
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -201,6 +210,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_256KB
imply PANIC_HANG
config TARGET_T2080QDS
@@ -211,6 +221,7 @@
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+ select SYS_L3_SIZE_512KB
imply CMD_SATA
config TARGET_T2080RDB
@@ -219,6 +230,7 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select SYS_L3_SIZE_512KB
imply CMD_SATA
imply PANIC_HANG
@@ -228,6 +240,7 @@
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ select SYS_L3_SIZE_512KB
imply CMD_SATA
imply PANIC_HANG
@@ -239,6 +252,7 @@
bool "Support kmcent2"
select VENDOR_KM
select FSL_CORENET
+ select SYS_L3_SIZE_256KB
endchoice
@@ -1277,9 +1291,35 @@
default 1
endif
+config SYS_L2_SIZE_256KB
+ bool
+
+config SYS_L2_SIZE_512KB
+ bool
+
+config SYS_L2_SIZE
+ int
+ default 262144 if SYS_L2_SIZE_256KB
+ default 524288 if SYS_L2_SIZE_512KB
+
config BACKSIDE_L2_CACHE
bool
+config SYS_L3_SIZE_256KB
+ bool
+
+config SYS_L3_SIZE_512KB
+ bool
+
+config SYS_L3_SIZE_1024KB
+ bool
+
+config SYS_L3_SIZE
+ int
+ default 262144 if SYS_L3_SIZE_256KB
+ default 524288 if SYS_L3_SIZE_512KB
+ default 1048576 if SYS_L3_SIZE_512KB
+
config SYS_PPC64
bool
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
index b972cf3..7921334 100644
--- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -76,7 +76,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
index 34b58bb..e53dd43 100644
--- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -40,7 +40,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ff73596..ed89011 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -84,7 +84,7 @@
static void check_erratum_a4580(uint32_t svr)
{
const serdes_corenet_t __iomem *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 14d5c56..49a1aac 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -59,7 +59,7 @@
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
/*
@@ -98,7 +98,7 @@
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (SVR_SOC_VER(svr) == SVR_T4080) {
ccsr_rcpm_t *rcpm =
- (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
FSL_CORENET_DEVDISR2_DTSEC1_9);
@@ -124,7 +124,7 @@
puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n");
#endif
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
printf("CPU%d: ", pic->whoami);
} else {
puts("CPU: ");
@@ -319,7 +319,7 @@
val |= 0x70000000;
mtspr(DBCR0,val);
#else
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Call board-specific preparation for reset */
board_reset_prepare();
@@ -436,7 +436,7 @@
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
unsigned int x = 10;
unsigned int i;
@@ -540,16 +540,16 @@
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 90f024d..47bea51 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -160,7 +160,7 @@
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
@@ -217,7 +217,7 @@
char cpc_subarg[16];
bool have_hwconfig = false;
int cpc_args = 0;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
/* Extract hwconfig from environment */
ret = env_get_f("hwconfig", buffer, sizeof(buffer));
@@ -271,7 +271,7 @@
static void invalidate_cpc(void)
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
@@ -300,9 +300,9 @@
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
- (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
- (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */
@@ -313,7 +313,7 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
void fsl_erratum_a007212_workaround(void)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_pll_ratio;
u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
@@ -379,13 +379,13 @@
{
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
#endif
#ifdef CONFIG_ARCH_MPC8548
- ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
/*
@@ -455,7 +455,7 @@
{
int i = 0;
u32 cluster, svr = get_svr();
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
/* only the L2 of first cluster should be enabled as expected on T4080,
@@ -476,7 +476,7 @@
do {
int j, cluster_valid = 0;
- l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+ l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
cluster = in_be32(&gur->tp_cluster[i].lower);
@@ -516,9 +516,9 @@
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_L2_CACHE
- ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
- struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+ struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
#endif
puts ("L2: ");
@@ -664,7 +664,7 @@
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
- ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
@@ -821,7 +821,7 @@
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
{
struct ccsr_usb_phy __iomem *usb_phy1 =
- (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+ (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
fsl_erratum_a006261_workaround(usb_phy1);
@@ -833,7 +833,7 @@
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
{
struct ccsr_usb_phy __iomem *usb_phy2 =
- (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+ (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
fsl_erratum_a006261_workaround(usb_phy2);
@@ -859,7 +859,7 @@
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
struct ccsr_usb_phy __iomem *usb_phy =
- (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+ (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
setbits_be32(&usb_phy->pllprg[1],
CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
@@ -928,11 +928,11 @@
fsl_sata_reg_t *reg;
/* first SATA controller */
- reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
+ reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR;
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
/* second SATA controller */
- reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
+ reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR;
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index e6d3058..18bfa2a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -85,10 +85,10 @@
{
u32 mas0, mas1, mas2, mas3, mas7;
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#ifdef CONFIG_A003399_NOR_WORKAROUND
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
u32 *dst, *src;
void (*setup_ifc_sram)(void);
int i;
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 61d8aa7..1161938 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -164,7 +164,7 @@
static inline void ft_fixup_l3cache(void *blob, int off)
{
u32 line_size, num_ways, size, num_sets;
- cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
@@ -222,7 +222,7 @@
/* return size in kilobytes */
static inline u32 l2cache_size(void)
{
- volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
u32 ver = SVR_SOC_VER(get_svr());
@@ -299,7 +299,7 @@
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
#else
struct ccsr_cluster_l2 *l2cache =
- (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+ (struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
#endif
u32 size, line_size, num_ways, num_sets;
@@ -466,11 +466,11 @@
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_DPAA_FMAN
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
sysinfo.freq_fman[1]);
#endif
#endif
@@ -509,7 +509,7 @@
#if defined(CONFIG_ARCH_P4080)
static void fdt_fixup_usb(void *fdt)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
int off;
@@ -532,7 +532,7 @@
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
int nodeoff;
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_ARCH_T2080)
@@ -611,7 +611,7 @@
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index da8e0b6..3a6ce32 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -21,10 +21,10 @@
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
@@ -104,13 +104,13 @@
ret |= serdes2_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
if (!serdes3_prtcl_map[NONE])
fsl_serdes_init();
ret |= serdes3_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
if (!serdes4_prtcl_map[NONE])
fsl_serdes_init();
@@ -122,7 +122,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
@@ -139,13 +139,13 @@
cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
case FSL_SRDS_3:
cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
case FSL_SRDS_4:
cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -193,7 +193,7 @@
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 cfg;
int lane;
@@ -351,28 +351,28 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
serdes_init(FSL_SRDS_3,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
serdes_init(FSL_SRDS_4,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2b4912b..437ecde 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -108,8 +108,8 @@
int serdes_lane_enabled(int lane)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank;
int word = lanes[lane].lpd / 32;
@@ -133,7 +133,7 @@
int is_serdes_configured(enum srds_prtcl device)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Is serdes enabled at all? */
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -169,7 +169,7 @@
u32 prtcl;
const ccsr_gur_t *gur;
- gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
/* Is serdes enabled at all? */
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
@@ -251,13 +251,13 @@
if (unlikely(device == NONE))
return;
- gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
/* Is serdes enabled at all? */
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
return;
- regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
__serdes_reset_rx(regs, prtcl, device);
@@ -466,7 +466,7 @@
static void wait_for_rstdone(unsigned int bank)
{
serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned long long end_tick;
u32 rstctl;
@@ -491,7 +491,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
#ifdef CONFIG_ARCH_P5040
@@ -527,7 +527,7 @@
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
@@ -601,7 +601,7 @@
serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
break;
default:
- srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
/* We don't need bank 4, so power it down */
setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c
index 4ad7626..bcbdfac 100644
--- a/arch/powerpc/cpu/mpc85xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc85xx/interrupts.c
@@ -25,7 +25,7 @@
void interrupt_init_cpu(unsigned *decrementer_count)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
#ifdef CONFIG_POST
/*
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 34974c9..9ad48d4 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -76,7 +76,7 @@
static void setup_sec_liodn_base(void)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
u32 base;
if (!IS_E_PROCESSOR(get_svr()))
@@ -101,12 +101,12 @@
switch(dev) {
case FSL_HW_PORTAL_FMAN1:
- fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM1_ADDR;
break;
#if (CONFIG_SYS_NUM_FMAN == 2)
case FSL_HW_PORTAL_FMAN2:
- fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM2_ADDR;
break;
#endif
default:
@@ -130,7 +130,7 @@
static void setup_pme_liodn_base(void)
{
#ifdef CONFIG_SYS_DPAA_PME
- ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+ ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_PME].id[1];
@@ -141,7 +141,7 @@
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
static void setup_raide_liodn_base(void)
{
- struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+ struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
/* setup raid engine liodn base for data/desc ; both set to 47 */
u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
@@ -155,7 +155,7 @@
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) {
/* write the RMan block number */
@@ -168,7 +168,7 @@
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 84eb8b4..f109ecb 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -50,7 +50,7 @@
int cpu_reset(u32 nr)
{
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr);
/* the dummy read works around an errata on early 85xx MP PICs */
(void)in_be32(&pic->pir);
@@ -87,7 +87,7 @@
#ifdef CONFIG_FSL_CORENET
int cpu_disable(u32 nr)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->coredisrl, 1 << nr);
@@ -95,7 +95,7 @@
}
int is_core_disabled(int nr) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 coredisrl = in_be32(&gur->coredisrl);
return (coredisrl & (1 << nr));
@@ -103,7 +103,7 @@
#else
int cpu_disable(u32 nr)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
switch (nr) {
case 0:
@@ -121,7 +121,7 @@
}
int is_core_disabled(int nr) {
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
switch (nr) {
@@ -264,10 +264,10 @@
u32 mask = cpu_mask();
struct law_entry e;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
- pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
+ rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
+ pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami);
cpu_up_mask = 1 << whoami;
@@ -336,9 +336,9 @@
u32 up, cpu_up_mask, whoami;
u32 *table = (u32 *)&__spin_table;
volatile u32 bpcr;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 devdisr;
int timeout = 10;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 111692f..cbcb57f 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -89,8 +89,8 @@
void fsl_serdes_init(void)
{
- void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
+ void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR;
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
u32 srds1_io_sel, srds2_io_sel;
u32 tmp;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index f3b5450..a48f3c1 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -52,7 +52,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 38f30af..479ee08 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -32,7 +32,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index 8cba422..56e5ef6 100644
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -51,7 +51,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 6b8e447..47f13e3 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -50,8 +50,8 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index bf5cac6..7a8f653 100644
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -35,7 +35,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index f36b1b6..8c5d82a 100644
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -40,7 +40,7 @@
void fsl_serdes_init(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index c5b1443..3cf41ca 100644
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -20,7 +20,7 @@
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
&(gur->qe_par_io);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 6686b7c..31d0481 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -24,16 +24,16 @@
void get_sys_info(sys_info_t *sys_info)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
- volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
unsigned int dsp_cpu;
uint rcw_tmp1, rcw_tmp2;
#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
@@ -575,7 +575,7 @@
{
sys_info_t sys_info;
#ifdef CONFIG_ARCH_MPC8544
- volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR;
#endif
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index bdd7338..47df3c2 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -15,7 +15,7 @@
ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9d44fa4..5341756 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -80,7 +80,7 @@
/* Definitions from C header file asm/immap_85xx.h */
-#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
#define MPC85xx_L2CTL 0x000
#define MPC85xx_L2CTL_L2E 0x80000000
@@ -127,13 +127,13 @@
.org 0x80 /* Start of configuration */
.Lconf_pair_start:
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
+ .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */
.long CONFIG_SYS_INIT_L2_ADDR
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
+ .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */
.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
+ .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */
.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */
@@ -966,7 +966,7 @@
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
- erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 97ed24a..8f451b4 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -260,7 +260,7 @@
void ExtIntException(struct pt_regs *regs)
{
- volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
+ volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
uint vect;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 0985fb2..7f20190 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -104,7 +104,7 @@
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
static inline u32 init_type(u32 cluster, int init_id)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = in_be32(&gur->tp_ityp[idx]);
@@ -116,7 +116,7 @@
u32 compute_ppc_cpumask(void)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type, mask = 0;
@@ -140,7 +140,7 @@
#ifdef CONFIG_HETROGENOUS_CLUSTERS
u32 compute_dsp_cpumask(void)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int i = CONFIG_DSP_CLUSTER_START, count = 0;
u32 cluster, type, dsp_mask = 0;
@@ -163,7 +163,7 @@
int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int count = 0, i = CONFIG_DSP_CLUSTER_START;
u32 cluster;
@@ -186,7 +186,7 @@
int fsl_qoriq_core_to_cluster(unsigned int core)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster;
@@ -235,7 +235,7 @@
*/
__weak u32 cpu_mask(void)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */
@@ -252,7 +252,7 @@
#ifdef CONFIG_HETROGENOUS_CLUSTERS
__weak u32 cpu_dsp_mask(void)
{
- ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
+ ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 24bbe3b..dd27416 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -20,7 +20,7 @@
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
@@ -301,7 +301,7 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* check RCW to get which port is used for boot */
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
u32 bootloc = in_be32(&gur->rcwsr[6]);
/*
* in SRIO or PCIE boot we need to set specail LAWs for
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c73cf93..c815d19 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -33,12 +33,12 @@
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
#endif
#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+ #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
#define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
- #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+ #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
@@ -79,9 +79,9 @@
int idx, first, last;
u32 i;
unsigned long long end_tick;
- struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
>> (12 - port * 4)) & 0x3;
init_lane = (in_be32((void *)&srio_regs->lp_serial
@@ -291,7 +291,7 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@@ -343,7 +343,7 @@
void srio_boot_master_release_slave(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index f753ddf..b94faa5 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -45,9 +45,7 @@
extern void flush_dcache(void);
extern void invalidate_dcache(void);
extern void invalidate_icache(void);
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
-#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d3d4e9c..25d1b48 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -17,10 +17,10 @@
#include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
@@ -59,30 +59,30 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_NUM_FMAN 2
@@ -91,11 +91,11 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_NUM_FMAN 2
@@ -104,7 +104,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
@@ -118,7 +118,7 @@
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
@@ -131,17 +131,17 @@
#endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRDS_3
-#define CONFIG_SYS_FSL_SRDS_4
+#define CFG_SYS_FSL_SRDS_3
+#define CFG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
@@ -154,21 +154,21 @@
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CONFIG_MAX_DSP_CPUS 2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -184,8 +184,7 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_SYS_FSL_NUM_CC_PLL 2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@@ -202,15 +201,15 @@
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
@@ -224,7 +223,7 @@
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
+#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 7ced50c..de85bcf 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -18,22 +18,22 @@
#define SET_SRIO_LIODN_1(port, idA) \
{ .id = { idA }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
- + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
}
#define SET_SRIO_LIODN_2(port, idA, idB) \
{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
.reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
- + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
.reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
- + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+ + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
}
#define SET_SRIO_LIODN_BASE(port, id_a) \
{ .id = { id_a }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ (port - 1) * 0x200 \
- + CONFIG_SYS_FSL_SRIO_ADDR, \
+ + CFG_SYS_FSL_SRIO_ADDR, \
}
struct liodn_id_table {
@@ -90,69 +90,69 @@
#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
SET_LIODN_ENTRY_1(compat, liodn, \
- offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+ offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \
compatoff)
#define SET_USB_LIODN(usbNum, compat, liodn) \
SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
- CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+ CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
#define SET_SATA_LIODN(sataNum, liodn) \
SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
- CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+ CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
#define SET_PCI_LIODN(compat, pciNum, liodn) \
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
- CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+ CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
SET_LIODN_ENTRY_1(compat, liodn,\
- offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
- CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+ offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, compat, liodn) \
SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
- CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+ CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
#define SET_SDHC_LIODN(sdhcNum, liodn) \
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
- CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+ CFG_SYS_MPC85xx_ESDHC_OFFSET)
#define SET_QE_LIODN(liodn) \
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
- CONFIG_SYS_MPC85xx_QE_OFFSET)
+ CFG_SYS_MPC85xx_QE_OFFSET)
#define SET_TDM_LIODN(liodn) \
SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
- CONFIG_SYS_MPC85xx_TDM_OFFSET)
+ CFG_SYS_MPC85xx_TDM_OFFSET)
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, \
offsetof(struct ccsr_qman, liodnr) + \
- CONFIG_SYS_FSL_QMAN_OFFSET, \
- CONFIG_SYS_FSL_QMAN_OFFSET)
+ CFG_SYS_FSL_QMAN_OFFSET, \
+ CFG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,bman", liodn, \
offsetof(struct ccsr_bman, liodnr) + \
- CONFIG_SYS_FSL_BMAN_OFFSET, \
- CONFIG_SYS_FSL_BMAN_OFFSET)
+ CFG_SYS_FSL_BMAN_OFFSET, \
+ CFG_SYS_FSL_BMAN_OFFSET)
#define SET_PME_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
- CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
- CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+ CFG_SYS_FSL_CORENET_PME_OFFSET, \
+ CFG_SYS_FSL_CORENET_PME_OFFSET)
#define SET_PMAN_LIODN(num, liodn) \
SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
offsetof(struct ccsr_pman, ppa1) + \
- CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
- CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+ CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+ CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
/* -1 from portID due to how immap has the registers */
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
- CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+ CFG_SYS_FSL_FM##fmNum##_OFFSET + \
offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
#ifdef CONFIG_SYS_FMAN_V3
@@ -160,31 +160,31 @@
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
#else
/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
#endif
/*
* handle both old and new versioned SEC properties:
@@ -193,44 +193,44 @@
#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, 0)
+ CFG_SYS_FSL_SEC_OFFSET, 0)
#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
liodnA, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
- CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+ CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
- CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+ CFG_SYS_FSL_RAID_ENGINE_OFFSET)
#define SET_RMAN_LIODN(ibNum, liodn) \
SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
offsetof(struct ccsr_rman, mmitdr) + \
- CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
- CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
+ CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
+ CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index c731347..8e18202 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -861,15 +861,15 @@
};
};
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
-#define CONFIG_SYS_FSL_DDR_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
-#define CONFIG_SYS_MPC83xx_DMA_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
-#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
+#define CFG_SYS_FSL_DDR_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
+#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
+#define CFG_SYS_MPC83xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET)
+#define CFG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
+#define CFG_SYS_MPC83xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7e88779..c9ced54 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -963,7 +963,7 @@
u32 prtoccsr; /* Port Response Time-out CCSR */
u8 res1[20];
u32 pgccsr; /* Port General CSR */
- struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Logical error reporting registers */
@@ -993,7 +993,7 @@
/* Physical error reporting registers */
struct rio_phys_err {
- struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Implementation Space: General Port-Common */
@@ -1033,7 +1033,7 @@
/* Implementation Space: register */
struct rio_implement {
struct rio_impl_common com;
- struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Revision Control Register */
@@ -1061,13 +1061,13 @@
/* ATMU window registers */
struct rio_atmu_win {
- struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+ struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM];
u8 res0[64];
- struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+ struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM];
};
struct rio_atmu {
- struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
#ifdef CONFIG_SYS_FSL_RMU
@@ -1154,7 +1154,7 @@
struct rio_atmu atmu;
#ifdef CONFIG_SYS_FSL_RMU
u8 res5[8192];
- struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+ struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM];
u8 res6[512];
struct rio_dbell dbell;
u8 res7[100];
@@ -1162,7 +1162,7 @@
#endif
#ifdef CONFIG_SYS_FSL_SRIO_LIODN
u8 res5[8192];
- struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS];
#endif
};
#endif
@@ -2431,17 +2431,17 @@
#endif
#ifdef CONFIG_FSL_CORENET
-#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#ifdef CONFIG_SYS_PMAN
-#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
-#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
-#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
+#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
+#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
+#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#endif
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
-#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
-#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
-#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
+#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
+#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
+#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
/* In SFPv3, OSPR register is now at offset 0x200.
* * So directly mapping sfp register map to this address */
@@ -2450,97 +2450,97 @@
#else
#define CONFIG_SYS_SFP_OFFSET 0xE8000
#endif
-#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
-#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
-#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
-#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
-#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
-#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
-#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
-#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
-#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
-#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
-#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
-#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
-#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
+#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
+#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
+#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
+#define CFG_SYS_FSL_CPC_OFFSET 0x10000
+#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000
+#define CFG_SYS_FSL_PAMU_OFFSET 0x20000
+#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000
+#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000
+#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000
+#define CFG_SYS_MPC85xx_DMA_OFFSET CFG_SYS_MPC85xx_DMA1_OFFSET
+#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x110000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
+#define CFG_SYS_MPC85xx_LBC_OFFSET 0x124000
+#define CFG_SYS_MPC85xx_IFC_OFFSET 0x124000
+#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000
+#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000
+#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
!defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
#else
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
-#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
+#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
#endif
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
+#define CFG_SYS_MPC85xx_USB1_OFFSET 0x210000
+#define CFG_SYS_MPC85xx_USB2_OFFSET 0x211000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
+#define CFG_SYS_FSL_SEC_OFFSET 0x300000
+#define CFG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
-#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
-#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
-#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
-#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
-#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
-#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
-#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
-#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
-#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
-#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
-#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
-#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
-#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
-#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
-#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
-#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
-#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
-#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
-#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
-#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
-#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
+#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000
+#define CFG_SYS_FSL_QMAN_OFFSET 0x318000
+#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000
+#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
+#define CFG_SYS_FSL_FM1_OFFSET 0x400000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
+#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
+#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
+#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
+#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
+#define CFG_SYS_FSL_FM2_OFFSET 0x500000
+#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
+#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
+#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
+#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
+#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
+#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
+#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
+#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
-#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
-#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
-#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
-#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
+#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000
+#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000
+#define CFG_SYS_MPC85xx_LBC_OFFSET 0x5000
+#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
+#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x7000
+#define CFG_SYS_MPC85xx_PCI1_OFFSET 0x8000
+#define CFG_SYS_MPC85xx_PCIX_OFFSET 0x8000
+#define CFG_SYS_MPC85xx_PCI2_OFFSET 0x9000
+#define CFG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
+#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
+#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
#if defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
#else
-#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
+#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
#endif
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
-#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
-#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
-#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
-#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
-#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
+#define CFG_SYS_MPC85xx_GPIO_OFFSET 0xF000
+#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x18000
+#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x19000
+#define CFG_SYS_MPC85xx_IFC_OFFSET 0x1e000
+#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
+#define CFG_SYS_MPC85xx_DMA_OFFSET 0x21000
+#define CFG_SYS_MPC85xx_USB1_OFFSET 0x22000
+#define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000
+#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
+#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
#ifdef CONFIG_TSECV2
#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
#elif defined(CONFIG_TSECV2_1)
@@ -2549,131 +2549,131 @@
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
+#define CFG_SYS_FSL_SEC_OFFSET 0x80000
+#define CFG_SYS_FSL_JR0_OFFSET 0x81000
#else
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
+#define CFG_SYS_FSL_SEC_OFFSET 0x30000
+#define CFG_SYS_FSL_JR0_OFFSET 0x31000
#endif
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
+#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
+#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
-#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
-#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
-#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
+#define CFG_SYS_FSL_QMAN_OFFSET 0x88000
+#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000
+#define CFG_SYS_FSL_FM1_OFFSET 0x100000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
-#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
+#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000
+#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
+#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
-#define CONFIG_SYS_FSL_CPC_ADDR \
- (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_ADDR \
- (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
-#define CONFIG_SYS_FSL_QMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_BMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
-#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
-#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_FSL_DDR_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_FSL_DDR2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_FSL_DDR3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+#define CFG_SYS_FSL_CPC_ADDR \
+ (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+#define CFG_SYS_FSL_SCFG_ADDR \
+ (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+#define CFG_SYS_FSL_QMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
+#define CFG_SYS_FSL_BMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET)
+#define CFG_SYS_FSL_CORENET_PME_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET)
+#define CFG_SYS_FSL_RAID_ENGINE_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
+#define CFG_SYS_FSL_CORENET_RMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
+#define CFG_SYS_MPC85xx_GUTS_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
+#define CFG_SYS_FSL_CORENET_CCM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CLK_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CFG_SYS_FSL_CORENET_RCPM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CFG_SYS_MPC85xx_ECM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
+#define CFG_SYS_FSL_DDR_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
+#define CFG_SYS_FSL_DDR2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CFG_SYS_FSL_DDR3_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_IFC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
-#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_FM1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_FM2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
-#define CONFIG_SYS_FSL_SRIO_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET)
+#define CFG_SYS_MPC85xx_ESPI_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET)
+#define CFG_SYS_MPC85xx_PCIX2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CFG_SYS_MPC85xx_GPIO_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET)
+#define CFG_SYS_MPC85xx_SATA1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET)
+#define CFG_SYS_MPC85xx_SATA2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET)
+#define CFG_SYS_MPC85xx_L2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET)
+#define CFG_SYS_MPC85xx_DMA_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET)
+#define CFG_SYS_MPC85xx_ESDHC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CFG_SYS_MPC8xxx_PIC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CFG_SYS_MPC85xx_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET)
+#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
+#define CFG_SYS_FSL_SRIO_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PAMU_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
#define CONFIG_SYS_PCI2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET)
#define CONFIG_SYS_PCIE1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
#define CONFIG_SYS_PCIE2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
#define CONFIG_SYS_PCIE3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET)
#define CONFIG_SYS_PCIE4_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
#define CONFIG_SYS_SFP_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
@@ -2739,8 +2739,8 @@
u32 l2erraddr; /* 0xe54 L2 cache error address */
u32 l2errctl; /* 0xe58 L2 cache error control */
};
-#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#define CFG_SYS_FSL_CLUSTER_1_L2 \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
@@ -2752,9 +2752,9 @@
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
-#define CONFIG_SYS_MPC85xx_SCFG \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
-#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+#define CFG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET)
+#define CFG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
/* The supplement configuration unit register */
struct ccsr_scfg {
u32 dpslpcr; /* 0x000 Deep Sleep Control register */
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index feebe15..0ed6bec 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -20,7 +20,7 @@
static inline void mpc85xx_gpio_set(unsigned int mask,
unsigned int dir, unsigned int val)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* First mask off the unwanted parts of "dir" and "val" */
dir &= mask;
@@ -56,7 +56,7 @@
static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
{
- ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* Read the requested values */
return in_be32(&gpio->gpdat) & mask;
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 0faf34c..09e3d10 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -132,7 +132,7 @@
int ret;
ret = ut_run_list("spl", NULL, tests, count,
- state->select_unittests, 1, false);
+ state->select_unittests, 1, false, NULL);
/* continue execution into U-Boot */
}
}
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 1b60914..2051207 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -68,10 +68,6 @@
reg = <0x10002000 0x1000>;
};
- host-fs {
- compatible = "sandbox,bootdev-host";
- };
-
i2c_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c
index 74dd115..6cc8c23 100644
--- a/board/advantech/imx8mp_rsb3720a1/spl.c
+++ b/board/advantech/imx8mp_rsb3720a1/spl.c
@@ -129,7 +129,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(1);
diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c
index 5fd6021..22ed639 100644
--- a/board/advantech/imx8qm_rom7720_a1/spl.c
+++ b/board/advantech/imx8qm_rom7720_a1/spl.c
@@ -64,7 +64,7 @@
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
-static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
@@ -108,7 +108,7 @@
* mmc1 USDHC2
* mmc2 USDHC3
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h
index 69a92de..f201ad3 100644
--- a/board/altera/arria5-socdk/qts/iocsr_config.h
+++ b/board/altera/arria5-socdk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h
index 6c83254..7fe290b 100644
--- a/board/altera/arria5-socdk/qts/pll_config.h
+++ b/board/altera/arria5-socdk/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 41
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 350000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1050000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 1066000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 350000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 100000000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 0
+#define CFG_HPS_ALTERAGRP_MAINCLK 2
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
index 927a7a4..1d032e1 100644
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h
index 81c507b..a571fb3 100644
--- a/board/altera/cyclone5-socdk/qts/iocsr_config.h
+++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index ae5cfab..a46d124 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 370000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 8adbfec..e3a8cfb 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h
index e233d02..dbcc1d7 100644
--- a/board/aries/mcvevk/qts/iocsr_config.h
+++ b/board/aries/mcvevk/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h
index 4fa868e..62cf679 100644
--- a/board/aries/mcvevk/qts/pll_config.h
+++ b/board/aries/mcvevk/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 100000000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 1953125
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 3125000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 100000000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h
index fd72926..c6a24f5 100644
--- a/board/aries/mcvevk/qts/sdram_config.h
+++ b/board/aries/mcvevk/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c
index dbc03c9..770ca8b 100644
--- a/board/bosch/acc/acc.c
+++ b/board/bosch/acc/acc.c
@@ -562,7 +562,7 @@
* mmc0 USDHC2
* mmc1 USDHC4
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc2_pads);
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
index 3ee1335..9733a33 100644
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -90,7 +90,7 @@
* mmc0 USDHC1
* mmc2 USDHC3 (eMMC)
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
cl_som_imx7_usdhc1_pads_set();
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index c54bffd..847ac33 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -622,7 +622,7 @@
int i;
cm_fx6_set_usdhc_iomux();
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++)
enable_usdhc_clk(1, i);
}
#endif
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
index c211cb5..c0a8a49 100644
--- a/board/congatec/cgtqmx8/cgtqmx8.c
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -114,7 +114,7 @@
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
-static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
@@ -173,7 +173,7 @@
* mmc1 (external SD card) USDHC2
* mmc2 (onboard µSD) USDHC3
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
/* onboard eMMC */
diff --git a/board/devboards/dbm-soc1/qts/iocsr_config.h b/board/devboards/dbm-soc1/qts/iocsr_config.h
index 99ed62b..56b2130 100644
--- a/board/devboards/dbm-soc1/qts/iocsr_config.h
+++ b/board/devboards/dbm-soc1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/devboards/dbm-soc1/qts/pll_config.h b/board/devboards/dbm-soc1/qts/pll_config.h
index f6ffa08..104e324 100644
--- a/board/devboards/dbm-soc1/qts/pll_config.h
+++ b/board/devboards/dbm-soc1/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/devboards/dbm-soc1/qts/sdram_config.h b/board/devboards/dbm-soc1/qts/sdram_config.h
index 2022969..2c4559b 100644
--- a/board/devboards/dbm-soc1/qts/sdram_config.h
+++ b/board/devboards/dbm-soc1/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h
index 18b9c6c..c24b5cb 100644
--- a/board/ebv/socrates/qts/iocsr_config.h
+++ b/board/ebv/socrates/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h
index 71d3674..eaa18c1 100644
--- a/board/ebv/socrates/qts/pll_config.h
+++ b/board/ebv/socrates/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 100000000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 666666666
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 100000000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
index 2f8465b..318ef0c 100644
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 7339408..f5bed6c 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -35,7 +35,7 @@
bool is_warm_boot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -57,7 +57,7 @@
{
u64 *src, *dst;
int i;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
@@ -71,7 +71,7 @@
void ls1_psci_resume_fixup(void)
{
u32 tmp;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef QIXIS_BASE
void *qixis_base = (void *)QIXIS_BASE;
@@ -114,7 +114,7 @@
{
u32 start_addr;
void (*kernel_resume)(void);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
if (!is_warm_boot())
return 0;
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index ad72353..d31ad02 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -28,9 +28,9 @@
#endif
#if defined(CONFIG_MPC85xx)
-#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
+#define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#else
-#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
+#define CONFIG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR
#endif
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 7a23d8f..3424d49 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -83,7 +83,7 @@
int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE);
u32 flash_addr, addr;
@@ -114,7 +114,7 @@
*/
int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
@@ -130,7 +130,7 @@
#if defined(CONFIG_ESBC_HDR_LS)
static int get_ie_info_addr(uintptr_t *ie_addr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* For LS-CH3, the address of IE Table is
* stated in Scratch13 and scratch14 of DCFG.
* Bootrom validates this table while validating uboot.
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index a6ee87d..f754cf4 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -9,7 +9,7 @@
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
- void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ void *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
u32 icid;
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index d2bb173..71922aa 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -24,7 +24,7 @@
bool is_warm_boot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -46,7 +46,7 @@
{
u64 *src, *dst;
int i;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
/* get the address of ddr date from SPARECR3 */
src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
@@ -80,7 +80,7 @@
{
u32 start_addr;
void (*kernel_resume)(void);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
if (!is_warm_boot())
return 0;
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index ee8ed61..a95d15c 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -180,7 +180,7 @@
void set_devices_ns_access(unsigned long index, u16 val)
{
- u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+ u32 *base = (u32 *)CFG_SYS_FSL_CSU_ADDR;
u32 *reg;
uint32_t tmp;
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index d2c9bbb..5ec3f2a 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -539,10 +539,10 @@
{
int re_enable = disable_interrupts();
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
u8 vid;
u32 fusesr;
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index b28056b..bea9ddc 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -121,7 +121,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
index 27f69ab..38267ac 100644
--- a/board/freescale/ls1012aqds/eth.c
+++ b/board/freescale/ls1012aqds/eth.c
@@ -133,7 +133,7 @@
struct mii_dev *bus;
static const char *mdio_name;
struct pfe_mdio_info mac_mdio_info;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u8 data8;
struct pfe_eth_dev *priv = dev_get_priv(dev);
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 361bd5c..3f70fbc 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -213,7 +213,7 @@
struct pfe_prop_val prop_val;
void *l_blob = blob;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index 565f800..5c66127 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -80,7 +80,7 @@
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index 3ed6100..8605d06 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -38,7 +38,7 @@
puts("Board: LS1021AIOT\n");
#ifndef CONFIG_QSPI_BOOT
- struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cpldrev;
cpldrev = in_be32(&dcfg->gpporcr1);
@@ -51,7 +51,7 @@
void ddrmc_init(void)
{
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -111,7 +111,7 @@
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 2eaad9e..d0674d0 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -160,7 +160,7 @@
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@@ -185,7 +185,7 @@
void board_init_f(ulong dummy)
{
#ifdef CONFIG_NAND_BOOT
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
@@ -234,7 +234,7 @@
void config_etseccm_source(int etsec_gtx_125_mux)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
switch (etsec_gtx_125_mux) {
case GE0_CLK125:
@@ -308,7 +308,7 @@
int config_serdes_mux(void)
{
- struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cfg;
cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index 245c9df..4325439 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -28,7 +28,7 @@
static void ddrmc_init(void)
{
#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -130,7 +130,7 @@
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/*
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index fa87df7..33027ad 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -143,7 +143,7 @@
void ddrmc_init(void)
{
- struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@@ -288,7 +288,7 @@
int config_serdes_mux(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -383,7 +383,7 @@
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index 7bfbacd..6783ebe 100644
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -261,7 +261,7 @@
void fdt_fixup_board_enet(void *fdt)
{
int i;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
@@ -302,7 +302,7 @@
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 7ac2c1a..b02f649 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -430,9 +430,9 @@
int board_early_init_f(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
@@ -475,7 +475,7 @@
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -529,7 +529,7 @@
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
-#ifdef CONFIG_SYS_FSL_SERDES
+#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
@@ -596,6 +596,6 @@
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
index fa59116..00ff602 100644
--- a/board/freescale/ls1043ardb/eth.c
+++ b/board/freescale/ls1043ardb/eth.c
@@ -21,7 +21,7 @@
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 8c91f07..799900e 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -188,7 +188,7 @@
int board_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
@@ -230,7 +230,7 @@
int config_board_mux(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
if (hwconfig("qe-hdlc")) {
diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c
index 06ccfe9..71c4c21 100644
--- a/board/freescale/ls1046afrwy/eth.c
+++ b/board/freescale/ls1046afrwy/eth.c
@@ -20,7 +20,7 @@
struct memac_mdio_info dtsec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
@@ -70,7 +70,7 @@
int i, prop;
int offset, nodeoff;
const char *path;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index 5a298cd..f6e5c12 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -146,7 +146,7 @@
void config_board_mux(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
/*
* USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c
index 13207a1..88265a3 100644
--- a/board/freescale/ls1046aqds/eth.c
+++ b/board/freescale/ls1046aqds/eth.c
@@ -268,7 +268,7 @@
{
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
u8 brdcfg12;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index aa6e30e..dfdc9f0 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -300,9 +300,9 @@
int board_early_init_f(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
@@ -347,7 +347,7 @@
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@@ -395,7 +395,7 @@
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-#ifdef CONFIG_SYS_FSL_SERDES
+#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
@@ -479,6 +479,6 @@
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
index a3e147a..04fa57f 100644
--- a/board/freescale/ls1046ardb/eth.c
+++ b/board/freescale/ls1046ardb/eth.c
@@ -22,7 +22,7 @@
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
@@ -84,7 +84,7 @@
int i, prop;
int offset, nodeoff;
const char *path;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 05269fc..1d12d91 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -80,7 +80,7 @@
int board_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_NXP_ESBC
/*
@@ -146,7 +146,7 @@
void config_board_mux(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c
index 140733d..8fe643f 100644
--- a/board/freescale/ls1088a/eth_ls1088aqds.c
+++ b/board/freescale/ls1088a/eth_ls1088aqds.c
@@ -471,7 +471,7 @@
*/
static void initialize_dpmac_to_slot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -524,7 +524,7 @@
void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
{
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -576,7 +576,7 @@
void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
{
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -615,7 +615,7 @@
void ls1088a_handle_phy_interface_xsgmii(int i)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@@ -639,7 +639,7 @@
static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
struct mii_dev *bus;
@@ -682,7 +682,7 @@
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ CFG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
@@ -807,7 +807,7 @@
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char expected_dts[100];
char srds_s1_str[2];
u32 srds_s1, cfg;
diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c
index 1ba5e94..5792070 100644
--- a/board/freescale/ls1088a/eth_ls1088ardb.c
+++ b/board/freescale/ls1088a/eth_ls1088ardb.c
@@ -25,7 +25,7 @@
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct memac_mdio_controller *reg;
u32 srds_s1, cfg;
@@ -35,14 +35,14 @@
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 0157377..ae81740 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -1031,7 +1031,7 @@
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
void *env_sf_get_env_addr(void)
{
- return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+ return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
#endif
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 7db3789..6da6e5c 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -502,7 +502,7 @@
*/
static void initialize_dpmac_to_slot(void)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -656,7 +656,7 @@
{
int lane, slot;
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -799,7 +799,7 @@
{
int lane = 0, slot;
struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -864,7 +864,7 @@
void ls2080a_handle_phy_interface_xsgmii(int i)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -898,7 +898,7 @@
{
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@@ -920,7 +920,7 @@
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ CFG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
@@ -930,7 +930,7 @@
sizeof(struct memac_mdio_info));
memac_mdio1_info->regs =
(struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ CFG_SYS_FSL_WRIOP1_MDIO2;
memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */
@@ -1053,7 +1053,7 @@
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 21b4c16..7034bc6 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -29,7 +29,7 @@
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
struct memac_mdio_controller *reg;
@@ -37,14 +37,14 @@
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index fb0699c..aa2d65b 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -242,7 +242,7 @@
ulong *cs4340_get_fw_addr(void)
{
#ifdef CONFIG_TFABOOT
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
#endif
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
@@ -318,7 +318,7 @@
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 val;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
index 1819b27..374d052 100644
--- a/board/freescale/lx2160a/eth_lx2160aqds.c
+++ b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -459,7 +459,7 @@
size_t len;
struct mii_dev *bus;
const struct phy_config *phy_config;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2, srds_s3;
srds_s1 = in_le32(&gur->rcwsr[28]) &
@@ -476,14 +476,14 @@
sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/
fm_memac_mdio_init(bis, &mdio_info);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@@ -670,9 +670,9 @@
priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO1;
else
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
@@ -929,7 +929,7 @@
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
u32 srds_s1, srds_s2, srds_s3;
diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c
index 15cbc58..8a9c60f 100644
--- a/board/freescale/lx2160a/eth_lx2160ardb.c
+++ b/board/freescale/lx2160a/eth_lx2160ardb.c
@@ -48,21 +48,21 @@
struct memac_mdio_controller *reg;
int i, interface;
struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c
index ac6218e..25fee89 100644
--- a/board/freescale/lx2160a/eth_lx2162aqds.c
+++ b/board/freescale/lx2160a/eth_lx2162aqds.c
@@ -480,7 +480,7 @@
size_t len;
struct mii_dev *bus;
const struct phy_config *phy_config;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
srds_s1 = in_le32(&gur->rcwsr[28]) &
@@ -493,14 +493,14 @@
sprintf(srds, "%d_%d", srds_s1, srds_s2);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/
fm_memac_mdio_init(bis, &mdio_info);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@@ -679,9 +679,9 @@
priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO1;
else
- reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
@@ -946,7 +946,7 @@
int board_fit_config_name_match(const char *name)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 5f0cc9e..4376755 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -180,7 +180,7 @@
const char dspi1_path[] = "/soc/spi@2110000";
const char dspi2_path[] = "/soc/spi@2120000";
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
u32 sdhc2_base_pmux;
u32 iic5_pmux;
@@ -385,7 +385,7 @@
int config_board_mux(void)
{
u8 reg11, reg5, reg13;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
u32 sdhc2_base_pmux;
u32 iic5_pmux;
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 8886d8b..e4c951f 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -33,8 +33,8 @@
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
@@ -68,7 +68,7 @@
void
local_bus_init(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index a9800ed..4f27d3e 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -124,7 +124,7 @@
return ret;
}
- if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+ if (!i2c_probe(CFG_SYS_FSL_PMIC_I2C_ADDR)) {
ret = pmic_init(I2C_0);
if (ret)
return ret;
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index c796330..c39df46 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -82,7 +82,7 @@
int board_early_init_f(void)
{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Clock configuration to access CPLD using IFC(GPCM) */
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
@@ -131,7 +131,7 @@
int config_board_mux(int ctrl_type)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u8 tmp;
#if CONFIG_IS_ENABLED(DM_I2C)
@@ -668,7 +668,7 @@
int misc_init_r(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index 8869500..0db11f4 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -28,7 +28,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
console_init_f();
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index a956c5a..a262d5c 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -20,7 +20,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index b301491..2999c85 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -149,7 +149,7 @@
void board_gpio_init(void)
{
#ifdef CONFIG_QE
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
/* Enable VSC7385 switch */
@@ -159,7 +159,7 @@
setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
#else
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/*
* GPIO10 DDR Reset, open drain
@@ -197,7 +197,7 @@
int board_early_init_f(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
#ifndef SDHC_WP_IS_GPIO
@@ -227,7 +227,7 @@
int checkboard(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u8 in, out, invert, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
@@ -370,7 +370,7 @@
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
ccsr_gur_t *gur __attribute__((unused)) =
- (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_TSEC1
@@ -418,7 +418,7 @@
static void fix_max6370_watchdog(void *blob)
{
int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370");
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 gpioval = in_be32(&pgpio->gpdat);
/*
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index eda84bf..e7d4428 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -29,7 +29,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/*
* Call board_early_init_f() as early as possible as it workarounds
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index 72beead..e467c7a 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -19,7 +19,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 2a84e9b..1b12630 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -66,7 +66,7 @@
int board_early_init_f(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
setbits_be32(&gur->ddrclkdr, 0x000f000f);
@@ -81,7 +81,7 @@
void board_config_lanes_mux(void)
{
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
@@ -167,7 +167,7 @@
int misc_init_r(void)
{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 4f04d2e..be42efa 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -33,7 +33,7 @@
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index af15da5..3ba94fe 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -29,7 +29,7 @@
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
/* GPIO1_14, 0: eMMC, 1: SD */
@@ -40,7 +40,7 @@
int board_mmc_getwp(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
val &= GPIO1_SD_SEL;
@@ -52,7 +52,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index 539a5c7..f777f5a 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -49,7 +49,7 @@
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -99,7 +99,7 @@
#ifdef CONFIG_TARGET_T1024RDB
static void board_mux_lane(void)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
u8 reg = CPLD_READ(misc_ctl_status);
@@ -222,7 +222,7 @@
int board_mmc_getcd(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
/* GPIO1_14, 0: eMMC, 1: SD/MMC */
@@ -233,7 +233,7 @@
int board_mmc_getwp(struct mmc *mmc)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
u32 val = in_be32(&pgpio->gpdat);
val &= GPIO1_SD_SEL;
@@ -243,8 +243,8 @@
static u32 t1023rdb_ctrl(u32 ctrl_type)
{
- ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 val;
u8 tmp;
int bus_num = I2C_PCA6408_BUS_NUM;
@@ -274,7 +274,7 @@
setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO3_GET_VERSION:
- pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+ pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
+ GPIO3_OFFSET);
val = in_be32(&pgpio->gpdat);
val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
@@ -323,7 +323,7 @@
setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO3_GET_VERSION:
- pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+ pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR
+ GPIO3_OFFSET);
val = in_be32(&pgpio->gpdat);
val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 3ae5d72..bb6641b 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -142,7 +142,7 @@
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
- CONFIG_SYS_MPC85xx_SCFG;
+ CFG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
(0x80000000));
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index dfaff1a..c7fb427 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -33,7 +33,7 @@
u32 porsr1, pinctl;
u32 svr = get_svr();
#endif
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
if (IS_SVR_REV(svr, 1, 0)) {
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 7800434..7d3fd29 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -93,7 +93,7 @@
int misc_init_r(void)
{
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 2d7fc8b..555985b 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -189,10 +189,10 @@
const char *phyconn;
int off;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
#endif
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
@@ -413,7 +413,7 @@
*/
static void initialize_lane_to_slot(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -459,7 +459,7 @@
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
u32 srds_s1;
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index e934a3c..8b68329 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -67,7 +67,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 1da3a71..82710cf 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -88,7 +88,7 @@
int brd_mux_lane_to_slot(void)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 60fe084..3f9b1fa 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -27,7 +27,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 34ffaa6..4041b3d 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -43,7 +43,7 @@
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index c7d5de3..72d3b80 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -33,7 +33,7 @@
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c
index eec3f3d..83de5bf 100644
--- a/board/google/imx8mq_phanbell/spl.c
+++ b/board/google/imx8mq_phanbell/spl.c
@@ -97,7 +97,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h
index 1d2774a..e54af2c 100644
--- a/board/is1/qts/iocsr_config.h
+++ b/board/is1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h
index 218ab35..0a5f5dd 100644
--- a/board/is1/qts/pll_config.h
+++ b/board/is1/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 59
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 375000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1500000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 488281
+#define CFG_HPS_CLK_SDMMC_HZ 1953125
+#define CFG_HPS_CLK_QSPI_HZ 375000000
+#define CFG_HPS_CLK_SPIM_HZ 12500000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 2573171..d8521a7 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 9f78443..b8f0578 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -11,6 +11,9 @@
menu "KM Board Setup"
+config SYS_I2C_INIT_BOARD
+ def_bool y if ARM
+
config HUSH_INIT_VAR
def_bool y
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index 4486538..6a17110 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -45,7 +45,7 @@
int board_early_init_f(void)
{
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
bool cpuwd_flag = false;
/* board specific IFC configuration: increased bus turnaround time */
@@ -220,9 +220,9 @@
int misc_init_r(void)
{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
- ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
+ ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* check SERDES bank 0 reference clock */
u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0);
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
index ed8142d..3719bcf 100644
--- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
+++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
@@ -50,8 +50,8 @@
int board_early_init_f(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */
diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h
index 7640c56..9f05fce 100644
--- a/board/keymile/secu1/qts/iocsr_config.h
+++ b/board/keymile/secu1/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00100000,
diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h
index f0c3186..7bc704a 100644
--- a/board/keymile/secu1/qts/pll_config.h
+++ b/board/keymile/secu1/qts/pll_config.h
@@ -6,78 +6,78 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 39
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 24
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 1
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 14
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 40000000
-#define CONFIG_HPS_CLK_OSC2_HZ 40000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
-#define CONFIG_HPS_CLK_USBCLK_HZ 12500000
-#define CONFIG_HPS_CLK_NAND_HZ 31250000
-#define CONFIG_HPS_CLK_SDMMC_HZ 3125000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 40000000
+#define CFG_HPS_CLK_OSC2_HZ 40000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 600000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 1953125
+#define CFG_HPS_CLK_USBCLK_HZ 12500000
+#define CFG_HPS_CLK_NAND_HZ 31250000
+#define CFG_HPS_CLK_SDMMC_HZ 3125000
+#define CFG_HPS_CLK_QSPI_HZ 3125000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h
index b0ff86e..a0ce0b2 100644
--- a/board/keymile/secu1/qts/sdram_config.h
+++ b/board/keymile/secu1/qts/sdram_config.h
@@ -8,76 +8,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x11
diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c
index ef32568..f6fd170 100644
--- a/board/kontron/pitx_imx8m/spl.c
+++ b/board/kontron/pitx_imx8m/spl.c
@@ -132,7 +132,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c
index 3ae8bf6..bae0e70 100644
--- a/board/kontron/sl-mx6ul/spl.c
+++ b/board/kontron/sl-mx6ul/spl.c
@@ -105,7 +105,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index 56eae3b..b1f6881 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -539,7 +539,7 @@
* mmc0 Soldered on board eMMC device
* mmc1 MicroSD card
*/
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
SETUP_IOMUX_PADS(usdhc3_pads);
@@ -554,7 +554,7 @@
break;
default:
printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ index + 1, CFG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c
index d20c9c5..fed0fbc 100644
--- a/board/msc/sm2s_imx8mp/spl.c
+++ b/board/msc/sm2s_imx8mp/spl.c
@@ -111,7 +111,7 @@
* mmc0 (sd) USDHC2
* mmc1 (emmc) USDHC3
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(1);
diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c
index 5cd4d05..3cf14e2 100644
--- a/board/myir/mys_6ulx/spl.c
+++ b/board/myir/mys_6ulx/spl.c
@@ -155,7 +155,7 @@
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index fea4aa3..b6d459f 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -156,7 +156,7 @@
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c
index a068f76..1bfd948 100644
--- a/board/purism/librem5/spl.c
+++ b/board/purism/librem5/spl.c
@@ -204,7 +204,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
log_debug("Initializing FSL USDHC port %d\n", i);
switch (i) {
case 0:
diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c
index c32a06f..b9a6745 100644
--- a/board/ronetix/imx8mq-cm/spl.c
+++ b/board/ronetix/imx8mq-cm/spl.c
@@ -89,7 +89,7 @@
* mmc0 USDHC1
* mmc1 USDHC2
*/
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 49d4024..943b498 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -176,10 +176,6 @@
return err;
}
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_i2c_init(gd->fdt_blob);
-#endif
-
return exynos_early_init_f();
}
#endif
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index ba25ba2..535f8e1 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -33,16 +33,6 @@
return 0;
}
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-void i2c_init_board(void)
-{
- gpio_request(S5PC110_GPIO_J43, "i2c_clk");
- gpio_request(S5PC110_GPIO_J40, "i2c_data");
- gpio_direction_output(S5PC110_GPIO_J43, 1);
- gpio_direction_output(S5PC110_GPIO_J40, 1);
-}
-#endif
-
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c
index 4b56f52..b29da2c 100644
--- a/board/seeed/npi_imx6ull/spl.c
+++ b/board/seeed/npi_imx6ull/spl.c
@@ -154,7 +154,7 @@
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index d358a20..04527cf 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -26,7 +26,7 @@
phys_size_t fixed_sdram(void)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 33b7261..eaba875 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -35,7 +35,7 @@
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
char buf[64];
int f;
int i = env_get_f("serial#", buf, sizeof(buf));
@@ -139,7 +139,7 @@
void local_bus_init (void)
{
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
uint lbc_mhz;
@@ -175,7 +175,7 @@
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* set and reset the GPIO pin 2 which will reset the W83782G chip */
out_8((unsigned char*)&gur->gpoutdr, 0x3F );
diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h
index 8c78aec..4059ed5 100644
--- a/board/softing/vining_fpga/qts/iocsr_config.h
+++ b/board/softing/vining_fpga/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h
index fa04618..40bc8f7 100644
--- a/board/softing/vining_fpga/qts/pll_config.h
+++ b/board/softing/vining_fpga/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 488281
-#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
-#define CONFIG_HPS_CLK_QSPI_HZ 320000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 250000000
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 488281
+#define CFG_HPS_CLK_SDMMC_HZ 1953125
+#define CFG_HPS_CLK_QSPI_HZ 320000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h
index ec067eb..27e3f3b 100644
--- a/board/softing/vining_fpga/qts/sdram_config.h
+++ b/board/softing/vining_fpga/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h
index b3b167fa7..2622b96 100644
--- a/board/sr1500/qts/iocsr_config.h
+++ b/board/sr1500/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00100000,
diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h
index 02f068f..885fe91 100644
--- a/board/sr1500/qts/pll_config.h
+++ b/board/sr1500/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 12500000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 12500000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index d25354b..3438221 100644
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de0-nano-soc/qts/iocsr_config.h b/board/terasic/de0-nano-soc/qts/iocsr_config.h
index 6ff5bd5..b856474 100644
--- a/board/terasic/de0-nano-soc/qts/iocsr_config.h
+++ b/board/terasic/de0-nano-soc/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h
index e439336..36d8fd1 100644
--- a/board/terasic/de0-nano-soc/qts/pll_config.h
+++ b/board/terasic/de0-nano-soc/qts/pll_config.h
@@ -6,78 +6,78 @@
#ifndef _PRELOADER_PLL_CONFIG_H_
#define _PRELOADER_PLL_CONFIG_H_
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3613281
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 3613281
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 0504dd6..3fb2f2a 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -5,80 +5,80 @@
#ifndef __SDRAM_CONFIG_H
#define __SDRAM_CONFIG_H
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h
index c65183e..359fd0e 100644
--- a/board/terasic/de1-soc/qts/iocsr_config.h
+++ b/board/terasic/de1-soc/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h
index 4544f92..2811e04 100644
--- a/board/terasic/de1-soc/qts/pll_config.h
+++ b/board/terasic/de1-soc/qts/pll_config.h
@@ -6,85 +6,85 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h
index c60426f..7b0ff2c 100644
--- a/board/terasic/de1-soc/qts/sdram_config.h
+++ b/board/terasic/de1-soc/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h
index bc5b7a0..a889d3d 100644
--- a/board/terasic/de10-nano/qts/iocsr_config.h
+++ b/board/terasic/de10-nano/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h
index 854936b..192ffb4 100644
--- a/board/terasic/de10-nano/qts/pll_config.h
+++ b/board/terasic/de10-nano/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 3125000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 3125000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h
index 26910ef..abf29f2 100644
--- a/board/terasic/de10-nano/qts/sdram_config.h
+++ b/board/terasic/de10-nano/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/de10-standard/qts/iocsr_config.h b/board/terasic/de10-standard/qts/iocsr_config.h
index c062b55..4aed74e 100644
--- a/board/terasic/de10-standard/qts/iocsr_config.h
+++ b/board/terasic/de10-standard/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/de10-standard/qts/pll_config.h b/board/terasic/de10-standard/qts/pll_config.h
index b08a977..c1ecd4b 100644
--- a/board/terasic/de10-standard/qts/pll_config.h
+++ b/board/terasic/de10-standard/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 370000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 4
+#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de10-standard/qts/sdram_config.h b/board/terasic/de10-standard/qts/sdram_config.h
index 630b551..1bfa427 100644
--- a/board/terasic/de10-standard/qts/sdram_config.h
+++ b/board/terasic/de10-standard/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h
index b8cb5f0..7b72ae9 100644
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -6,10 +6,10 @@
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h
index f6ffa08..104e324 100644
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -6,79 +6,79 @@
#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+#define CFG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CFG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CFG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CFG_HPS_PERPLLGRP_SRC_NAND 2
+#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000
-#define CONFIG_HPS_CLK_OSC2_HZ 25000000
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
-#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
-#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
-#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
-#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
-#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
-#define CONFIG_HPS_CLK_NAND_HZ 50000000
-#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 400000000
-#define CONFIG_HPS_CLK_SPIM_HZ 200000000
-#define CONFIG_HPS_CLK_CAN0_HZ 12500000
-#define CONFIG_HPS_CLK_CAN1_HZ 12500000
-#define CONFIG_HPS_CLK_GPIODB_HZ 32000
-#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
-#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+#define CFG_HPS_CLK_OSC1_HZ 25000000
+#define CFG_HPS_CLK_OSC2_HZ 25000000
+#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CFG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CFG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CFG_HPS_CLK_PERVCO_HZ 1000000000
+#define CFG_HPS_CLK_SDRVCO_HZ 800000000
+#define CFG_HPS_CLK_EMAC0_HZ 1953125
+#define CFG_HPS_CLK_EMAC1_HZ 250000000
+#define CFG_HPS_CLK_USBCLK_HZ 200000000
+#define CFG_HPS_CLK_NAND_HZ 50000000
+#define CFG_HPS_CLK_SDMMC_HZ 200000000
+#define CFG_HPS_CLK_QSPI_HZ 400000000
+#define CFG_HPS_CLK_SPIM_HZ 200000000
+#define CFG_HPS_CLK_CAN0_HZ 12500000
+#define CFG_HPS_CLK_CAN1_HZ 12500000
+#define CFG_HPS_CLK_GPIODB_HZ 32000
+#define CFG_HPS_CLK_L4_MP_HZ 100000000
+#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+#define CFG_HPS_ALTERAGRP_MPUCLK 1
+#define CFG_HPS_ALTERAGRP_MAINCLK 3
+#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 96cc357..efdbc85 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -7,76 +7,76 @@
#define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
-#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
+#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index 8d2642f..96d0185 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -322,7 +322,7 @@
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC1, SD1 */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index ab2ab58..475250d 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -290,7 +290,7 @@
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
{USDHC1_BASE_ADDR},
};
diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c
index a15b81b..e6403ca 100644
--- a/board/traverse/ten64/ten64.c
+++ b/board/traverse/ten64/ten64.c
@@ -61,7 +61,7 @@
static u32 ten64_get_board_rev(void)
{
- struct ccsr_gur *dcfg = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur *dcfg = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 board_rev_in = in_le32(&dcfg->gpporcr1);
return board_rev_in;
}
diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index 91d470f..17b1ae7 100644
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -159,7 +159,7 @@
{
int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 0983d10..717e02a 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -487,7 +487,7 @@
* mmc0 SOM MicroSD
* mmc1 Carrier board MicroSD
*/
- for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
SETUP_IOMUX_PADS(usdhc3_pads);
@@ -504,7 +504,7 @@
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
- index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ index + 1, CFG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index 20e88d4..c36b2af 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -13,7 +13,7 @@
unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#elif defined(CONFIG_MPC86xx)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -36,7 +36,7 @@
*/
unsigned long get_board_ddr_clk(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
index b268103..9d92103 100644
--- a/board/xes/common/fsl_8xxx_misc.c
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -28,7 +28,7 @@
uint get_board_derivative(void)
{
#if defined(CONFIG_MPC85xx)
- volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#elif defined(CONFIG_MPC86xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 1054064..1092fb9 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1200,11 +1200,31 @@
Load a binary over memory mapped.
config CMD_LOADS
- bool "loads"
+ bool "loads - Load a file over serial in S-Record format"
default y
help
Load an S-Record file over serial line
+config LOADS_ECHO
+ bool "Echo all characters received during a loads back to console"
+ depends on CMD_LOADS
+ help
+ If enabled, all characters received during a serial download (using
+ the "loads" command) are echoed back. This might be needed by some
+ terminal emulations (like "cu"), but may as well just take time on
+ others. This sets the initial value of the "loads_echo" environment
+ variable to 1.
+
+config CMD_SAVES
+ bool "saves - Save a file over serial in S-Record format"
+ help
+ Provides a way to save a binary file using the Motorola S-Record
+ format over the serial line.
+
+config SYS_LOADS_BAUD_CHANGE
+ bool "Enable a temporary baudrate change during loads/saves command"
+ depends on CMD_LOADS || CMD_SAVES
+
config CMD_LOADXY_TIMEOUT
int "loadxy_timeout"
range 0 2000
@@ -1404,12 +1424,6 @@
Attachment, where AT refers to an IBM AT (Advanced Technology)
computer released in 1984.
-config CMD_SAVES
- bool "saves - Save a file over serial in S-Record format"
- help
- Provides a way to save a binary file using the Motorola S-Record
- format over the serial line.
-
config CMD_SCSI
bool "scsi - Access to SCSI devices"
default y if SCSI
diff --git a/cmd/blob.c b/cmd/blob.c
index e2efae7..7c77c41 100644
--- a/cmd/blob.c
+++ b/cmd/blob.c
@@ -84,7 +84,7 @@
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();
diff --git a/cmd/host.c b/cmd/host.c
index f0d989a..fb1cb1f 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -8,12 +8,12 @@
#include <dm.h>
#include <fs.h>
#include <part.h>
-#include <sandboxblockdev.h>
+#include <sandbox_host.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
#include <linux/errno.h>
-static int host_curr_device = -1;
-
static int do_host_load(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -42,10 +42,10 @@
char *const argv[])
{
bool removable = false;
- const char *dev_str;
+ struct udevice *dev;
+ const char *label;
char *file;
- char *ep;
- int dev;
+ int ret;
/* Skip 'bind' */
argc--;
@@ -61,101 +61,158 @@
if (argc > 2)
return CMD_RET_USAGE;
- dev_str = argv[0];
- dev = hextoul(dev_str, &ep);
- if (*ep) {
- printf("** Bad device specification %s **\n", dev_str);
+ label = argv[0];
+ file = argc > 1 ? argv[1] : NULL;
+
+ ret = host_create_attach_file(label, file, removable, &dev);
+ if (ret) {
+ printf("Cannot create device / bind file\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+/**
+ * parse_host_label() - Parse a device label or sequence number
+ *
+ * This shows an error if it returns NULL
+ *
+ * @label: String containing the label or sequence number
+ * Returns: Associated device, or NULL if not found
+ */
+static struct udevice *parse_host_label(const char *label)
+{
+ struct udevice *dev;
+
+ dev = host_find_by_label(label);
+ if (!dev) {
+ int devnum;
+ char *ep;
+
+ devnum = hextoul(label, &ep);
+ if (*ep ||
+ uclass_find_device_by_seq(UCLASS_HOST, devnum, &dev)) {
+ printf("No such device '%s'\n", label);
+ return NULL;
+ }
+ }
+
+ return dev;
+}
+
+static int do_host_unbind(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct udevice *dev;
+ const char *label;
+ int ret;
+
+ if (argc < 2)
return CMD_RET_USAGE;
+
+ label = argv[1];
+ dev = parse_host_label(label);
+ if (!dev)
+ return CMD_RET_FAILURE;
+
+ ret = host_detach_file(dev);
+ if (ret) {
+ printf("Cannot detach file (err=%d)\n", ret);
+ return CMD_RET_FAILURE;
}
- file = argc > 1 ? argv[1] : NULL;
+
+ ret = device_unbind(dev);
+ if (ret) {
+ printf("Cannot attach file\n");
+ ret = device_unbind(dev);
+ if (ret)
+ printf("Cannot unbind device '%s'\n", dev->name);
+ return CMD_RET_FAILURE;
+ }
- return !!host_dev_bind(dev, file, removable);
+ return 0;
}
+static void show_host_dev(struct udevice *dev)
+{
+ struct host_sb_plat *plat = dev_get_plat(dev);
+ struct blk_desc *desc;
+ struct udevice *blk;
+ int ret;
+
+ printf("%3d ", dev_seq(dev));
+ if (!plat->fd) {
+ printf("Not bound to a backing file\n");
+ return;
+ }
+ ret = blk_get_from_parent(dev, &blk);
+ if (ret) /* cannot happen */
+ return;
+
+ desc = dev_get_uclass_plat(blk);
+ printf("%12lu %-15s %s\n", (unsigned long)desc->lba, plat->label,
+ plat->filename);
+}
+
static int do_host_info(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- if (argc < 1 || argc > 2)
+ struct udevice *dev;
+
+ if (argc < 1)
return CMD_RET_USAGE;
- int min_dev = 0;
- int max_dev = SANDBOX_HOST_MAX_DEVICES - 1;
+
+ dev = NULL;
if (argc >= 2) {
- char *ep;
- char *dev_str = argv[1];
- int dev = hextoul(dev_str, &ep);
- if (*ep) {
- printf("** Bad device specification %s **\n", dev_str);
- return CMD_RET_USAGE;
- }
- min_dev = dev;
- max_dev = dev;
+ dev = parse_host_label(argv[1]);
+ if (!dev)
+ return CMD_RET_FAILURE;
}
- int dev;
- printf("%3s %12s %s\n", "dev", "blocks", "path");
- for (dev = min_dev; dev <= max_dev; dev++) {
- struct blk_desc *blk_dev;
- int ret;
- printf("%3d ", dev);
- ret = host_get_dev_err(dev, &blk_dev);
- if (ret) {
- if (ret == -ENOENT)
- puts("Not bound to a backing file\n");
- else if (ret == -ENODEV)
- puts("Invalid host device number\n");
+ printf("%3s %12s %-15s %s\n", "dev", "blocks", "label", "path");
+ if (dev) {
+ show_host_dev(dev);
+ } else {
+ struct uclass *uc;
- continue;
- }
- struct host_block_dev *host_dev;
-
-#ifdef CONFIG_BLK
- host_dev = dev_get_plat(blk_dev->bdev);
-#else
- host_dev = blk_dev->priv;
-#endif
- printf("%12lu %s\n", (unsigned long)blk_dev->lba,
- host_dev->filename);
+ uclass_id_foreach_dev(UCLASS_HOST, dev, uc)
+ show_host_dev(dev);
}
+
return 0;
}
static int do_host_dev(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- int dev;
- char *ep;
- struct blk_desc *blk_dev;
- int ret;
+ struct udevice *dev;
+ const char *label;
if (argc < 1 || argc > 3)
return CMD_RET_USAGE;
if (argc == 1) {
- if (host_curr_device < 0) {
+ struct host_sb_plat *plat;
+
+ dev = host_get_cur_dev();
+ if (!dev) {
printf("No current host device\n");
- return 1;
+ return CMD_RET_FAILURE;
}
- printf("Current host device %d\n", host_curr_device);
+ plat = dev_get_plat(dev);
+ printf("Current host device: %d: %s\n", dev_seq(dev),
+ plat->label);
return 0;
}
- dev = hextoul(argv[1], &ep);
- if (*ep) {
- printf("** Bad device specification %s **\n", argv[2]);
- return CMD_RET_USAGE;
- }
-
- ret = host_get_dev_err(dev, &blk_dev);
- if (ret) {
- if (ret == -ENOENT)
- puts("Not bound to a backing file\n");
- else if (ret == -ENODEV)
- puts("Invalid host device number\n");
+ label = argv[1];
+ dev = parse_host_label(argv[1]);
+ if (!dev)
+ return CMD_RET_FAILURE;
- return 1;
- }
+ host_set_cur_dev(dev);
- host_curr_device = dev;
return 0;
}
@@ -165,6 +222,7 @@
U_BOOT_CMD_MKENT(save, 6, 0, do_host_save, "", ""),
U_BOOT_CMD_MKENT(size, 3, 0, do_host_size, "", ""),
U_BOOT_CMD_MKENT(bind, 4, 0, do_host_bind, "", ""),
+ U_BOOT_CMD_MKENT(unbind, 4, 0, do_host_unbind, "", ""),
U_BOOT_CMD_MKENT(info, 3, 0, do_host_info, "", ""),
U_BOOT_CMD_MKENT(dev, 0, 1, do_host_dev, "", ""),
};
@@ -178,8 +236,7 @@
argc--;
argv++;
- c = find_cmd_tbl(argv[0], cmd_host_sub,
- ARRAY_SIZE(cmd_host_sub));
+ c = find_cmd_tbl(argv[0], cmd_host_sub, ARRAY_SIZE(cmd_host_sub));
if (c)
return c->cmd(cmdtp, flag, argc, argv);
@@ -196,10 +253,11 @@
"host save hostfs - <addr> <filename> <bytes> [<offset>] - "
"save a file to host\n"
"host size hostfs - <filename> - determine size of file on host\n"
- "host bind [-r] <dev> [<filename>] - bind \"host\" device to file\n"
+ "host bind [-r] <label> [<filename>] - bind \"host\" device to file\n"
" -r = mark as removable\n"
- "host info [<dev>] - show device binding & info\n"
- "host dev [<dev>] - Set or retrieve the current host device\n"
+ "host unbind <label> - unbind file from \"host\" device\n"
+ "host info [<label>] - show device binding & info\n"
+ "host dev [<label>] - set or retrieve the current host device\n"
"host commands use the \"hostfs\" device. The \"host\" device is used\n"
"with standard IO commands such as fatls or ext2load"
);
diff --git a/common/board_f.c b/common/board_f.c
index 7c26e23..e6117a7 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -475,8 +475,8 @@
{
/*
* The value of gd->start_addr_sp must match the value of malloc_start
- * calculated in boatrd_f.c:initr_malloc(), which is passed to
- * board_r.c:mem_malloc_init() and then used by
+ * calculated in board_r.c:initr_malloc(), which is passed to
+ * dlmalloc.c:mem_malloc_init() and then used by
* cache.c:noncached_init()
*
* These calculations must match the code in cache.c:noncached_init()
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 6f2014b..22d2a06 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -46,10 +46,6 @@
#ifndef CONFIG_SYS_UBOOT_START
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
#endif
-#ifndef CONFIG_SYS_MONITOR_LEN
-/* Unknown U-Boot size, let's assume it will not be more than 200 KB */
-#define CONFIG_SYS_MONITOR_LEN (200 * 1024)
-#endif
u32 *boot_params_ptr = NULL;
@@ -232,11 +228,17 @@
return map_sysmem(CONFIG_TEXT_BASE + offset, 0);
}
+#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
ulong u_boot_pos = spl_get_image_pos();
+#if CONFIG_SYS_MONITOR_LEN != 0
spl_image->size = CONFIG_SYS_MONITOR_LEN;
+#else
+ /* Unknown U-Boot size, let's assume it will not be more than 200 KB */
+ spl_image->size = 200 * 1024;
+#endif
/*
* Binman error cases: address of the end of the previous region or the
@@ -254,6 +256,7 @@
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
}
+#endif
#if CONFIG_IS_ENABLED(LOAD_FIT_FULL)
/* Parse and load full fitImage in SPL */
diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig
index e1f7504..dd88d10 100644
--- a/configs/10m50_defconfig
+++ b/configs/10m50_defconfig
@@ -9,6 +9,7 @@
CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard"
CONFIG_SYS_LOAD_ADDR=0xcc000000
CONFIG_ENV_ADDR=0xF4080000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0xCFF80000
# CONFIG_AUTOBOOT is not set
diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig
index b094d3d..3d62512 100644
--- a/configs/3c120_defconfig
+++ b/configs/3c120_defconfig
@@ -9,6 +9,7 @@
CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard"
CONFIG_SYS_LOAD_ADDR=0xd4000000
CONFIG_ENV_ADDR=0xE2880000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0xD7F80000
# CONFIG_AUTOBOOT is not set
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 6727932..ee92ac4 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -11,6 +11,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index 99f5785..2ac6803 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -9,6 +9,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index f9d17b1..8f390cb 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 8c90435..ec11da5 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
index bccadcc..8ce10d6 100644
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 0a9de5e..e38110b 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -11,6 +11,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 38daf33..4e48047 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -9,6 +9,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
index d73e64c..113d54d 100644
--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
@@ -11,6 +11,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index 8a6bb88..1e1c30e 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -12,6 +12,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 5de6c2d..e76e6dd 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -12,6 +12,7 @@
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
index 6e9bdc2..1d3cf31 100644
--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
@@ -13,6 +13,7 @@
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig
index e051745..97d0b9c 100644
--- a/configs/A20-Olimex-SOM204-EVB_defconfig
+++ b/configs/A20-Olimex-SOM204-EVB_defconfig
@@ -12,6 +12,7 @@
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index 351a454..49c9250 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -16,5 +16,6 @@
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DCDC1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 9a18af8..4f01188 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index 7bf3dfc..d5cf1f4 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 7d81f12..2b9d3a8 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,6 +8,7 @@
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 4c7154b..f3e6944 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 18ee81b..0bd163a 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -12,6 +12,7 @@
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 6c2a1f6..2814d77 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -9,6 +9,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig
index bad38a6..0e73265 100644
--- a/configs/Bananapi_m2m_defconfig
+++ b/configs/Bananapi_m2m_defconfig
@@ -10,6 +10,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 94fd747..1137599 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -11,6 +11,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index cd9bdbf..03b2e03 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -7,6 +7,7 @@
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_CHIP_DIP_SCAN=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_DFU_RAM=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index 2917960..0e7d5e7 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
@@ -19,6 +20,7 @@
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index 1cd39d4..73983b1 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -7,6 +7,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 02b3e69..4f964f1 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 270bd7d..470d3f3 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index ab5e53f..2c1b3d2 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -8,6 +8,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index 04ed79a..c17edba 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -12,5 +12,6 @@
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index c017b12..0081675 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -8,6 +8,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index c85468e..a424634 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -13,6 +13,7 @@
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 13f9589..b44b9a7 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -15,6 +15,7 @@
CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index a9bbe8b..d31e867 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index fc1f26b..3e15d77 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 24e8b5b..0617192 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -9,6 +9,7 @@
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 482e0fb..d745a68 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,6 +15,7 @@
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index 99df9cf..6474c9e 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -8,6 +8,7 @@
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index f97dc13..c943fd3 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -10,6 +10,7 @@
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index 9815348..5e9732e 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -5,4 +5,5 @@
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_MONITOR_LEN=786432
# CONFIG_NETDEVICES is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index e3e30a4..469dcc1 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -10,6 +10,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 1fda0db..c4a3f2d 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -8,6 +8,7 @@
CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 49dcfa0..80eb661 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -6,6 +6,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig
index 255a4f1..fd219cb 100644
--- a/configs/M5208EVBE_defconfig
+++ b/configs/M5208EVBE_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0x2000
CONFIG_TARGET_M5208EVBE=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig
index b5842c7..1b7b156 100644
--- a/configs/M5235EVB_Flash32_defconfig
+++ b/configs/M5235EVB_Flash32_defconfig
@@ -9,6 +9,7 @@
CONFIG_TARGET_M5235EVB=y
CONFIG_NORFLASH_PS32BIT=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig
index 3e9cacc..fffcddd 100644
--- a/configs/M5235EVB_defconfig
+++ b/configs/M5235EVB_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5235EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig
index 5c6bd24..b192839 100644
--- a/configs/M5249EVB_defconfig
+++ b/configs/M5249EVB_defconfig
@@ -8,6 +8,7 @@
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5249EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index 2510774..581023f 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -8,6 +8,7 @@
CONFIG_ENV_ADDR=0xFF804000
CONFIG_TARGET_M5253DEMO=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xFF800400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index fda10e7..5e7d401 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5272C3=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index 49caafc..e7e799b 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5275EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index 4519e56..5521cce 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_M5282EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig
index fa32e14..6586f04 100644
--- a/configs/M53017EVB_defconfig
+++ b/configs/M53017EVB_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0x40000
CONFIG_TARGET_M53017EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig
index 0c2fbaf..bf1d70f 100644
--- a/configs/M5329AFEE_defconfig
+++ b/configs/M5329AFEE_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig
index f4b9b2d..b83b542 100644
--- a/configs/M5329BFEE_defconfig
+++ b/configs/M5329BFEE_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5329EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig
index 922f345..181f79b 100644
--- a/configs/M5373EVB_defconfig
+++ b/configs/M5373EVB_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0x4000
CONFIG_TARGET_M5373EVB=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index 307f2be..6c41d7c 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -19,6 +19,7 @@
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_DER=0x2002000F
+CONFIG_SYS_MONITOR_LEN=327680
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_MONITOR_BASE=0x04000000
CONFIG_BOOTDELAY=5
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index 3ed962d..0a4681b 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index ebbbac3..675b2de 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -9,6 +9,7 @@
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_MPC837XERDB=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_5_1=y
@@ -146,6 +147,7 @@
CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
@@ -156,6 +158,8 @@
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 3833596..e5c45a1 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -7,12 +7,14 @@
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_PCIE1=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
@@ -27,6 +29,8 @@
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_PCI=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index bdfd91f..85ec76a 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -7,11 +7,13 @@
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_PCIE1=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
@@ -26,6 +28,8 @@
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_PCI=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index ef92c7b..852ac9a 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -7,12 +7,14 @@
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_TARGET_MPC8548CDS_LEGACY=y
CONFIG_PCIE1=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
@@ -27,6 +29,8 @@
CONFIG_CMD_IMLS=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_PCI=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index 071169f..915a74d 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,6 +10,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index e77b007..d01532f 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 3c5312d..e3ada32 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN4I=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index c697d28..d1bc200 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -7,6 +7,7 @@
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index f5b6d90..3424b97 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -8,6 +8,7 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 2b9bca1..11ba786 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -7,6 +7,7 @@
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 77cb464..1b04ebc 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -9,6 +9,7 @@
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index b07dbbd..114c2fe 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,6 +9,7 @@
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index be6dd41..b24ef02 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -7,6 +7,7 @@
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index c5d1f40..2b96f6b 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -12,5 +12,6 @@
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_SUN8I_RSB=y
CONFIG_AXP809_POWER=y
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index e8bc148..72745f2 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,6 +6,7 @@
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index b660234..94060ab 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -9,11 +9,13 @@
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index c89a9a1..b4d5fef 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -12,6 +12,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 8757dcb..4319738 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -14,6 +14,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index a234a54..e15ca5e 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -60,6 +62,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index d3080f0..dcf74f5 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -13,6 +14,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -30,6 +32,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 333bf0c..230c6d0 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
@@ -19,6 +20,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -51,6 +53,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index b1a323e..982420d 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -53,6 +55,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index d212cbd..b3af445 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -14,12 +14,14 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -59,6 +61,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index c7f2670..537d8bf 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -6,12 +6,14 @@
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -29,6 +31,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index e0e0615..dd91209 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -12,12 +12,14 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -50,6 +52,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 2a9dd64..ff7cfa2 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -14,12 +14,14 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -52,6 +54,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 135cd03..a61f4d0 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -61,6 +63,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index f684ee1..92a7e09 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -13,6 +14,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -31,6 +33,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 85af079..84e2d3c 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
@@ -19,6 +20,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -52,6 +54,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index ce85806..b883b81 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -54,6 +56,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 953ceee..7f7870d 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -14,12 +14,14 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -60,6 +62,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index b11d016..3e16470 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -6,12 +6,14 @@
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -30,6 +32,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index aab7903..e985f8c 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -12,12 +12,14 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -51,6 +53,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 665d3a9..9f4ae14 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -14,12 +14,14 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -53,6 +55,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 6d0160b..3f93b31 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -61,6 +63,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 43def85..3b3cf1e 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -19,6 +20,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -53,6 +55,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 31e4606..aba5b9c 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -55,6 +57,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 2553c6c..ce0ba0e 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -14,6 +15,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -33,6 +35,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index f7e5141..f3fc4c8 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -20,6 +21,7 @@
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -60,6 +62,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 8092737..25eb5d5 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -18,6 +19,7 @@
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -52,6 +54,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 4418eb3..054320f 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -20,6 +21,7 @@
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -54,6 +56,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 6db4ae1..aae886b 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -13,6 +14,7 @@
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -32,6 +34,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index a4086a3..cc02fe6 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -20,6 +21,7 @@
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -60,6 +62,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 6ca5d18..dc82da8 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -18,6 +19,7 @@
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -52,6 +54,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 79ed4f5..7b80ede 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -20,6 +21,7 @@
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -54,6 +56,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 175d586..5fecb66 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -13,6 +14,7 @@
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -32,6 +34,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index cd9dd70..9162774 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -61,6 +63,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 458ab58..fd143b6 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -19,6 +20,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -53,6 +55,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index b28872c..edb8b99 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -21,6 +22,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -55,6 +57,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index bafd17c..b1dbca6 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -14,6 +15,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PHYS_64BIT=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -33,6 +35,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 66f2596..1269d22 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -20,6 +21,7 @@
CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -60,6 +62,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index ad98dde..b5394d0 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -18,6 +19,7 @@
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -52,6 +54,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 09619d5..431ca31 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -20,6 +21,7 @@
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -54,6 +56,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 5f34999..1ee46f9 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
@@ -13,6 +14,7 @@
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -32,6 +34,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 3b65d84..2ba5666 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -5,6 +5,7 @@
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -14,6 +15,7 @@
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -37,6 +39,8 @@
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 272724e..9a2796f 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -5,6 +5,7 @@
CONFIG_ENV_OFFSET=0xCF400
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -14,6 +15,7 @@
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -37,6 +39,8 @@
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 6250d0c..8cb00d5 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -15,6 +16,7 @@
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -39,6 +41,8 @@
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index f67aa80..c0bd16b 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -15,6 +16,7 @@
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -35,6 +37,8 @@
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index 7004588..73ef73c 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -16,6 +16,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index c8c8d5b..9fa0fda 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -16,6 +16,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 238b007..a1d62fc 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -10,6 +10,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 4eb5300..eb172c7 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CMD_DFU=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index aba9527..fa967bc 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -7,6 +7,7 @@
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 5116fab..ab70eff 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -15,6 +15,7 @@
CONFIG_AXP_GPIO=y
CONFIG_SATAPWR="PD25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index bb62ae9..53cead2 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -12,3 +12,4 @@
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_USB3_VBUS_PIN="PL8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 71aa43a..2aada04 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -22,6 +23,7 @@
CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -67,6 +69,8 @@
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index cb31652..e5661b0 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -22,6 +23,7 @@
CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -66,6 +68,8 @@
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index fb3ba55..320f22e 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -24,6 +25,7 @@
CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -69,6 +71,8 @@
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index fa3b5b2..1f571b6 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -6,6 +6,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -16,6 +17,7 @@
CONFIG_PCIE3=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -41,6 +43,8 @@
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 0a1d405..4088d40 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -21,6 +22,7 @@
CONFIG_PCIE3=y
CONFIG_PCIE4=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -60,6 +62,8 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 30e2b6f..5a6f9a8 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -21,6 +22,7 @@
CONFIG_PCIE3=y
CONFIG_PCIE4=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -59,6 +61,8 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 44694cd..2d03b4e 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -23,6 +24,7 @@
CONFIG_PCIE3=y
CONFIG_PCIE4=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -62,6 +64,8 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 064aba2..8f283fa 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -15,6 +16,7 @@
CONFIG_PCIE3=y
CONFIG_PCIE4=y
CONFIG_SYS_FSL_NUM_CC_PLLS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -34,6 +36,8 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 44afe11..beb0259 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -28,6 +29,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -64,6 +66,8 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 91236b2..7ee5fb4 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -28,6 +29,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -63,6 +65,8 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 9b3ffe5..c050e31 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -3,6 +3,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -23,6 +24,7 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -38,6 +40,8 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 7ed03d2..0ff651a 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -30,6 +31,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -66,6 +68,8 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index efa8d45..98065da 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -4,6 +4,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -22,6 +23,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -38,6 +40,8 @@
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index c9df2d1..88e943d 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -22,6 +23,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -38,6 +40,8 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index e53e4ff..23f6ee6 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -27,6 +28,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 46e603b..c2d95c1 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -27,6 +28,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index b64eafc..2194ff6 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -29,6 +30,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 98ac77c..7f57b00 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -21,6 +22,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 3f0489d..5d4573a 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -10,6 +10,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -28,6 +29,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 86cade4..7ca9a8b 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -28,6 +29,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index cf4bf31..39fcd2d 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -13,6 +13,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -30,6 +31,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index e01dbc5..8d1011d 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -22,6 +23,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 8540abd..9b08267 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
@@ -25,6 +26,7 @@
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SYS_FSL_NUM_CC_PLLS=5
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -60,6 +62,8 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 689b644..662edc3 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -5,6 +5,7 @@
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -19,6 +20,7 @@
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SYS_FSL_NUM_CC_PLLS=5
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -35,6 +37,8 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index b021b0a..d7912e1 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,6 +20,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index 101ce57..8e729b8 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index f401ac7..2eb1331 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,6 +12,7 @@
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index e0687bf..fb87747 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,6 +7,7 @@
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index f1ceb8b..31e79ac 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,6 +19,7 @@
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 6701ecc..625f729 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,5 +16,6 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig
index 8ec9eb3..c3eaaa7 100644
--- a/configs/a64-olinuxino-emmc_defconfig
+++ b/configs/a64-olinuxino-emmc_defconfig
@@ -6,6 +6,7 @@
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig
index 16cef18..7632302 100644
--- a/configs/a64-olinuxino_defconfig
+++ b/configs/a64-olinuxino_defconfig
@@ -6,6 +6,7 @@
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index cbfc97d..d876602 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -10,6 +10,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 201f754..1c0b534 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -14,6 +14,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_SYS_MONITOR_BASE=0x88000000
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index f7ac0b5..dc584a6 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -15,6 +15,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_SYS_MONITOR_BASE=0x88000000
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 64be1ee..ec62994 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -11,6 +11,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SYS_MONITOR_BASE=0x88000000
CONFIG_BOOTDELAY=3
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index b43e8f4..e4d6fc2 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 4d3d02d..45332e2 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -17,6 +17,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTDELAY=10
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi"
CONFIG_SPL_MAX_SIZE=0xec00
diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig
index ae44b66..66c245f 100644
--- a/configs/amarula_a64_relic_defconfig
+++ b/configs/amarula_a64_relic_defconfig
@@ -7,6 +7,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index 14a6187..b8e8bc4 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_ADDR=0xFFC1F000
CONFIG_TARGET_AMCORE=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=126976
CONFIG_SYS_MONITOR_BASE=0xFFC00400
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 70ef62a..6c27901 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 2c0e165..68655cf 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=1
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 587af46..b50665b 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
index d920ab4..afbcb86 100644
--- a/configs/astro_mcf5373l_defconfig
+++ b/configs/astro_mcf5373l_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0x1FF8000
CONFIG_TARGET_ASTRO_MCF5373L=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x00000400
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 15dbeca..e7d32f0 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -18,6 +18,7 @@
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_ENV_ADDR=0x107E0000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 68faaa9..794cf0e 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -19,6 +19,7 @@
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_ENV_ADDR=0x107E0000
CONFIG_DEBUG_UART=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 9b767e9..19297be 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 95e18a1..661f656 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 901460b..9ecf42f 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -15,6 +15,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index b855038..a2c0616 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -15,6 +15,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index a12b3ff..372b8ab 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index c1dd6df..cab2dcb 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -19,6 +19,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 357cab9..b9d7246 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 270aecc..728a72c 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index a3f65be..53417bc 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -19,6 +19,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index b89dd8e..9268ceb 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -9,6 +9,7 @@
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig
index 0fbb619..12ea6a3 100644
--- a/configs/bananapi_m1_plus_defconfig
+++ b/configs/bananapi_m1_plus_defconfig
@@ -9,6 +9,7 @@
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_NETCONSOLE=y
CONFIG_SCSI_AHCI=y
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index 588eea2..63f9c14 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -9,6 +9,7 @@
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SCSI_AHCI=y
CONFIG_SYS_64BIT_LBA=y
diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig
index 26ced59..2bd5a70 100644
--- a/configs/bananapi_m2_plus_h3_defconfig
+++ b/configs/bananapi_m2_plus_h3_defconfig
@@ -7,6 +7,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig
index fb6c945..926cf6f 100644
--- a/configs/bananapi_m2_plus_h5_defconfig
+++ b/configs/bananapi_m2_plus_h5_defconfig
@@ -7,6 +7,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig
index ac3f8f5..b351d50 100644
--- a/configs/bananapi_m2_zero_defconfig
+++ b/configs/bananapi_m2_zero_defconfig
@@ -6,3 +6,4 @@
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig
index 5463b04..74fa637 100644
--- a/configs/bananapi_m64_defconfig
+++ b/configs/bananapi_m64_defconfig
@@ -7,6 +7,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 24f619c..0967367 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig
index 42925ea..7d8f216 100644
--- a/configs/beelink_gs1_defconfig
+++ b/configs/beelink_gs1_defconfig
@@ -8,6 +8,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig
index 6206d90..68acb6b 100644
--- a/configs/beelink_x2_defconfig
+++ b/configs/beelink_x2_defconfig
@@ -6,5 +6,6 @@
CONFIG_DRAM_CLK=567
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index f82b233..bed7370 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -18,6 +18,7 @@
CONFIG_ENV_ADDR=0x40000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 87aa930..9bfa759 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index f716f62..58d75a5 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index becb0a7..06987ab 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -12,6 +12,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SMP=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SYS_MONITOR_LEN=2097152
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 932351d..59ae29a 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -20,6 +20,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index e7640f5..ffa8070 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -19,6 +19,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index eaa3faf..ca453ac 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -20,6 +20,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index a472470..92018fb 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -20,6 +20,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index ecb3c9c..95f7b09 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -14,6 +14,7 @@
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ARCH_JZ47XX=y
CONFIG_SYS_MIPS_TIMER_FREQ=1200000000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index c55c6c5..f3ee559 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -21,6 +21,7 @@
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index b787b1a..ea75966 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -25,6 +25,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd"
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index eaeddc8..0a5ce20 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -25,6 +25,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTCOMMAND="mmc dev 0; if mmc rescan; then if run loadbootscript; then run bootscript; fi; fi; mmc dev 1; if mmc rescan; then run emmcboot; fi;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 4eaedf6..2fdb882 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_TARGET_COBRA5272=y
CONFIG_MCFTMR=y
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFFE00400
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 78a170d..aa24dea 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -26,6 +26,7 @@
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=1
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 224de94..95fef40 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index a616eae..a69acd9 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 5d3636e3..a7496c8 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO2_VOLT=1800
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index c9afb9d..094b216 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -12,6 +12,7 @@
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SYS_MONITOR_LEN=2097152
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 40ca9fe..30454a3 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -86,6 +86,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index cc46f4e..ea8bc8a 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 6a2bb86..6630069 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -18,6 +18,7 @@
CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20
+CONFIG_SYS_MONITOR_LEN=393216
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 2c3dc31..8347b67 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -12,6 +12,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 3763532..04a5447 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -29,6 +29,7 @@
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index e1067b6..1b29264 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 9daa9a4..dbd917b 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -29,6 +29,7 @@
CONFIG_ENV_OFFSET_REDUND=0x130000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 1f05460..7508702 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_OFFSET_REDUND=0x130000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index 60910c3..d81782f 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 13c9944..f904bb3 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -9,6 +9,7 @@
CONFIG_TARGET_EB_CPU5282=y
CONFIG_MCFTMR=y
CONFIG_SYS_BARGSIZE=1024
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xFF000400
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index 52b29b2..2ce6ff9 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -8,6 +8,7 @@
CONFIG_TARGET_EB_CPU5282=y
CONFIG_MCFTMR=y
CONFIG_SYS_BARGSIZE=1024
+CONFIG_SYS_MONITOR_LEN=131072
CONFIG_SYS_MONITOR_BASE=0xF0000418
CONFIG_BOOTDELAY=5
CONFIG_BOOT_RETRY=y
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index 8238a1b..be83201 100644
--- a/configs/edison_defconfig
+++ b/configs/edison_defconfig
@@ -10,6 +10,7 @@
CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_EDISON=y
CONFIG_SMP=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0x01101000
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig
index a3b43df..e482f3c 100644
--- a/configs/emlid_neutis_n5_devboard_defconfig
+++ b/configs/emlid_neutis_n5_devboard_defconfig
@@ -8,4 +8,5 @@
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 7bc3ac2..ee731f3 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -98,6 +98,7 @@
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=3
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 5cacfd4..c3d0bc2 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -31,9 +31,9 @@
CONFIG_CMD_UNZIP=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SAVES=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
-CONFIG_CMD_SAVES=y
CONFIG_CMD_SPI=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 1a05311..7c0b856 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 12e80ca..63c53a0 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb"
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 599eeb9..03ba9dd 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -17,6 +17,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index db04e27..703cd08 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -25,6 +25,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=0
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 4c565a7..3974e3d 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -10,6 +10,7 @@
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_ENV_ADDR=0xFE080000
CONFIG_MPC83xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_GAZERBEAM=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
@@ -113,6 +114,7 @@
CONFIG_SYS_MEMTEST_START=0x00001000
CONFIG_SYS_MEMTEST_END=0x07e00000
CONFIG_SYS_BARGSIZE=1024
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
@@ -139,6 +141,8 @@
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_AXI=y
# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 8e0b218..55222eb 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig
index c468446..e836227 100644
--- a/configs/grpeach_defconfig
+++ b/configs/grpeach_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_LOAD_ADDR=0x20400000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="ignore_loglevel"
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 1a5fe06..4069cf1 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 8ec6751..cabe09e 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -25,6 +25,7 @@
CONFIG_ENV_OFFSET_REDUND=0xD1400
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 597d289..f58abd9 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -25,6 +25,7 @@
CONFIG_ENV_OFFSET_REDUND=0xD1400
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 54195fb..a41b3c4 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -25,6 +25,7 @@
CONFIG_ENV_OFFSET_REDUND=0x1080000
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 29f9652..cf3e7ce 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -10,6 +10,7 @@
CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_AXP_DLDO4_VOLT=3300
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 353d1a3..5a3c509 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index 086715f..a6523b1 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -13,6 +13,7 @@
# CONFIG_SPL is not set
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig
index 1fd6d6d..3e99904 100644
--- a/configs/hikey960_defconfig
+++ b/configs/hikey960_defconfig
@@ -29,6 +29,7 @@
CONFIG_ENV_EXT4_INTERFACE="mmc"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=1024
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_PINCTRL=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 257dd89..d75a799 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,6 +7,7 @@
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 436e3a8..67474a8 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 6978f8b..23d41b7 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 2c8ecb5..d51561e 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index 9a90252..8057df5 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -17,6 +17,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_CONS_INDEX=5
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index c759d7e..80441b3 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -17,6 +17,7 @@
CONFIG_VIDEO_LCD_POWER="PH22"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_CMD_UNZIP=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 25eda11..997c2df 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -11,6 +11,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index 1f10375..5a3f009 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -16,6 +16,7 @@
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index 23bd92b..b29b315 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -26,6 +26,7 @@
# CONFIG_CMD_DEKBLOB is not set
CONFIG_BUILD_TARGET=""
# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index e5228ba..8af23c1 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index d90e42c..90eb153 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -23,6 +23,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index e8cbf67..9f6d29a 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index e497d28ff..ee2c597 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -20,6 +20,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index 0880cc7..c597a18 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -20,6 +20,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index eeb0ef7..b4e65d0 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -20,6 +20,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
index 75718e5..ede7380 100644
--- a/configs/imx7_cm_defconfig
+++ b/configs/imx7_cm_defconfig
@@ -21,6 +21,7 @@
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run boot${boot-mode}"
CONFIG_DEFAULT_FDT_FILE="ask"
# CONFIG_BOARD_EARLY_INIT_F is not set
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index bb10581..80b801f 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -17,6 +17,7 @@
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index 548fb7b..e8e9d23 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -19,6 +19,7 @@
CONFIG_ENV_OFFSET_REDUND=0x204000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 18d605e..846efa5 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index 9fe30e2..2814d3b 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 991bd1a..f1e48bb 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -24,6 +24,7 @@
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 737f578..93f6631 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_LTO=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index a18c2ca..3ccd268 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -25,6 +25,7 @@
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x60000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 158627b..5d1f30a 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -19,6 +19,7 @@
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index 66e85ed..7c43dcf 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 06775b3..65031ab 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 94a8e85..ba6856e 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index b2c2663..c73f7d7 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index b695a69..47f4e15 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index 34893fc..5092ec12 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -20,6 +20,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index c574bb2..e238122 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index b40ffea..777b01a 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 1ff1909..560b445 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 6c31a33..d785915 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index 79eb8b0..f679fbe 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -22,6 +22,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 872465b..ecc28c8 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -30,6 +30,7 @@
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index f8b903d..91ec39d 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -22,6 +22,7 @@
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 3e1c195..48436ff 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
@@ -24,6 +25,7 @@
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 20f4a8c..3cba4e2 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
@@ -24,6 +25,7 @@
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 5a4abbd..220b2a2 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index 7a92fcc..ad42237 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 252565d..274cdb9 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 16cd4cc..7169e4d 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -21,6 +21,7 @@
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 962c469..4c15c7f 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -20,6 +20,7 @@
CONFIG_SYS_LOAD_ADDR=0x80480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=0
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 10e315c..64da123 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index f81120b..64f7787 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index 3ade9fe..086098e 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index d5d2dc3..0f70e95 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index bd6c45b..5c61766 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 4485f93..d21d17f 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,6 +13,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index 1769256..a614821 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig
index 71f399b..ea1f858 100644
--- a/configs/integratorcp_cm1136_defconfig
+++ b/configs/integratorcp_cm1136_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_ADDR=0x24F00000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig
index 7585d6d..19c72c7 100644
--- a/configs/integratorcp_cm920t_defconfig
+++ b/configs/integratorcp_cm920t_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_ADDR=0x24F00000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig
index 6f8c196..e0ba572 100644
--- a/configs/integratorcp_cm926ejs_defconfig
+++ b/configs/integratorcp_cm926ejs_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_ADDR=0x24F00000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig
index 6efa39f..e4e960e 100644
--- a/configs/integratorcp_cm946es_defconfig
+++ b/configs/integratorcp_cm946es_defconfig
@@ -12,6 +12,7 @@
CONFIG_ENV_ADDR=0x24F00000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SYS_MONITOR_BASE=0x27F40000
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 0ff666b..2e6b045 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -8,6 +8,7 @@
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 1187974..b391a86 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 977348e..9bf2e86 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -79,6 +79,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index afba285..afa4dc1 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -54,6 +54,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 6c45639..cbf948f 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -79,6 +79,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 33624ba..2480547 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -54,6 +54,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index e28054b..f4c8c5e 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -79,6 +79,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 8f8bb54..051cd23 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -57,6 +57,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 86c7aa5..48ac85b 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -8,6 +8,7 @@
CONFIG_SYS_CLK_FREQ=66666666
CONFIG_ENV_ADDR=0xebf20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
@@ -18,6 +19,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_IVM_BUS=2
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -34,6 +36,8 @@
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 9b3fee7..298ff16 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMCOGE5NE=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_VCO_DIV_4=y
@@ -159,6 +160,7 @@
CONFIG_LCRR_CLKDIV_4=y
CONFIG_83XX_PCICLK=0x3ef1480
CONFIG_KM_DEF_NETDEV="eth1"
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -180,6 +182,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 0aba19b..9386f2c 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -10,6 +10,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMETER1=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_VCO_DIV_4=y
@@ -129,6 +130,7 @@
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -150,6 +152,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index b3f993d..1733066 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMOPTI2=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
@@ -142,6 +143,7 @@
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -162,6 +164,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index d3e85c0..c281611 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMSUPX5=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
@@ -122,6 +123,7 @@
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -142,6 +144,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index cf2f59b..e099f74 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMTEPR2=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
@@ -142,6 +143,7 @@
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -162,6 +164,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 9252375..b4e6bae 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index 05c09ae..d2726b1 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 9112956..f044334 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -29,6 +29,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index b297201..6a11e51 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -19,6 +19,7 @@
CONFIG_ENV_OFFSET_REDUND=0x102000
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index cc5f4c5..472d8da 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index d5304bc..8be8421 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -23,6 +23,7 @@
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig
index 8725fe6..d19e337 100644
--- a/configs/libretech_all_h3_cc_h2_plus_defconfig
+++ b/configs/libretech_all_h3_cc_h2_plus_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig
index 5275fdc..4f3ab90 100644
--- a/configs/libretech_all_h3_cc_h3_defconfig
+++ b/configs/libretech_all_h3_cc_h3_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig
index 9627401..a912829 100644
--- a/configs/libretech_all_h3_cc_h5_defconfig
+++ b/configs/libretech_all_h3_cc_h5_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=672
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig
index cb7ffb4..f1f177c 100644
--- a/configs/libretech_all_h3_it_h5_defconfig
+++ b/configs/libretech_all_h3_it_h5_defconfig
@@ -7,6 +7,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig
index c3aa4b1..1dbcaa8 100644
--- a/configs/libretech_all_h5_cc_h5_defconfig
+++ b/configs/libretech_all_h5_cc_h5_defconfig
@@ -7,6 +7,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPI_FLASH_XMC=y
CONFIG_SUN8I_EMAC=y
CONFIG_SPI=y
diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig
index 12a43c1..e7663e1 100644
--- a/configs/licheepi_nano_defconfig
+++ b/configs/licheepi_nano_defconfig
@@ -7,6 +7,7 @@
CONFIG_DRAM_ZQ=0
# CONFIG_VIDEO_SUNXI is not set
CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 06f9fd7..adf65b3 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=1
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 450f254..c67f329 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -23,6 +23,7 @@
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_RAMBOOT_PBL=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index c766708..14aa19f 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -29,6 +29,7 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 9c3d2a8..4a642f4 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -30,6 +30,7 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index eb5e332..1b5d822 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -29,6 +29,7 @@
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_RAMBOOT_PBL=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 60f0795..9695164 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -23,6 +23,7 @@
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 0c42bcf..cb3d158 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1064960
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index eee355c..c53827c 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 9e936da..46ab9a2 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 2d2f6d2..29cbac3 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -37,6 +37,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index fc0e7fa..14931f7 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -38,6 +38,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 8a617a0..2284463 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -37,6 +37,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 372e1d1..6b9971f 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -24,6 +24,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1064960
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index d66ca18..0aa046a 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -28,6 +28,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index aec4df9..a6c33de 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -25,6 +25,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1064960
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 69a69aa..ddf280a 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -29,6 +29,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index b17742b..75851ad 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -37,6 +37,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=655360
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 316e4cd..3124644 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -38,6 +38,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index e206f9e..344899e 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -37,6 +37,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 7f8cb69..d9c716e 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -29,6 +29,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index c43f462..ac2cede 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -31,6 +31,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 4da4f64..6074b6b 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -28,6 +28,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1064960
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 1026ca1..07b0777 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -29,6 +29,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index a2bc106..0a7541d 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -31,6 +31,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index 81d9192..d9f2781 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -32,6 +32,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 2bb9fdf..504db13 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -31,6 +31,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1064960
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index b897988..8053bc1 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -32,6 +32,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index e13c28c..8899fd9 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -17,6 +17,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index d8d034c..a9f52ae 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -18,6 +18,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 2584d1a..0b70e7b 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -21,6 +21,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 78daa29..648a539 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -16,6 +16,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 133230d..318822b 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -23,6 +23,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index b6eb0a7..8ae8b52 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 36cc4fb..d548bca 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -22,6 +22,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 034b57a..a49fe87 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -26,6 +26,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index a6aaaf2..58bae66 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -22,6 +22,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 144974f..4c1e742 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -20,6 +20,7 @@
# CONFIG_QIXIS_I2C_ACCESS is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index eba1d02..6e1fe90 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -21,6 +21,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index c02edad..8441814 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -23,6 +23,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0
# CONFIG_SYS_MALLOC_F is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index cd213d6..93be74d 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -23,6 +23,7 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index a8af8ed..c2bf451 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -25,6 +25,7 @@
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 9ad8fc3..ea3f2ac 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -24,6 +24,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 9bbeb3a..9be7ac9 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -26,6 +26,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index c33b342..e82e623 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -25,6 +25,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 3e610a5..10ed60a 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index d10431e..42b6421 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
index aaf890d..ad1b123 100644
--- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -24,6 +24,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index c3ca105..ee37dfd 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -26,6 +26,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
index f64a55e..0fe96e3 100644
--- a/configs/lx2162aqds_tfa_verified_boot_defconfig
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -26,6 +26,7 @@
CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=958464
CONFIG_MP=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 93e40b6..43ffc3c 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -19,6 +19,7 @@
# CONFIG_CMD_BMODE is not set
CONFIG_ENV_ADDR=0x8040000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 76e4eb3..cb5324b 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index ba5bd8a..0811e70 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb"
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 0e4cdc4..646594b 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,6 +9,7 @@
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_REALTEK=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 21f7a6e..ffcb932 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,6 +7,7 @@
CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index 416565e..1186a53 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index 965a9cd..9c31b33 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index 6691eb3..09187dd 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -20,6 +20,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_BOOT_GET_CMDLINE=y
CONFIG_SYS_BARGSIZE=2048
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig
index ee30f48..5291bb3 100644
--- a/configs/mt7621_nand_rfb_defconfig
+++ b/configs/mt7621_nand_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_MIPS=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig
index 9987cc5..70280ad 100644
--- a/configs/mt7621_rfb_defconfig
+++ b/configs/mt7621_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_MIPS=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_MALLOC_LEN=0x100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index a0d33c0..3f18add 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig
index 82397b2..c56b4bb 100644
--- a/configs/mt7623a_unielec_u7623_02_defconfig
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x81e00000
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index 34960c0..e36943b 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x81e00000
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index b5dbbea..d7669d5 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_ARCH_TIMER=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MEDIATEK=y
diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig
index 557c8e7..4832a22 100644
--- a/configs/mt7981_emmc_rfb_defconfig
+++ b/configs/mt7981_emmc_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig
index f9776ffc..c397527 100644
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig
index 5e0c8c8..17592dc 100644
--- a/configs/mt7981_sd_rfb_defconfig
+++ b/configs/mt7981_sd_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig
index e3ded76..1363f9d 100644
--- a/configs/mt7986_rfb_defconfig
+++ b/configs/mt7986_rfb_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig
index 6d29885..354159d 100644
--- a/configs/mt7986a_bpir3_emmc_defconfig
+++ b/configs/mt7986a_bpir3_emmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig
index 222987a..db7ef98 100644
--- a/configs/mt7986a_bpir3_sd_defconfig
+++ b/configs/mt7986a_bpir3_sd_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig
index 772306c..888da16 100644
--- a/configs/mt8512_bm1_emmc_defconfig
+++ b/configs/mt8512_bm1_emmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=13000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig
index d75e299..43c166d 100644
--- a/configs/mt8518_ap1_emmc_defconfig
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=13000000
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 45bc0a6..0904bd1 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -21,6 +21,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index bf6aff8..2aa15ce 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -22,6 +22,7 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 26cee0ea..766ce0e 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 85dc039..02ad43b 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 1f1bff1..598d72c 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 0b9c100..a9979f6 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index f252893..2a632ff8 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -16,6 +16,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig
index 70fc257..ed11e0a 100644
--- a/configs/nanopi_a64_defconfig
+++ b/configs/nanopi_a64_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig
index dc2dbd6..9419eaf 100644
--- a/configs/nanopi_m1_defconfig
+++ b/configs/nanopi_m1_defconfig
@@ -5,5 +5,6 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index 37b7817..89065f0 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -8,6 +8,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig
index 95dd56a..d76d37f 100644
--- a/configs/nanopi_neo2_defconfig
+++ b/configs/nanopi_neo2_defconfig
@@ -7,6 +7,7 @@
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index 806d95c..09a6bfa 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=408
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index c025519..6110cfd 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=408
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig
index 924ff38..d462b63 100644
--- a/configs/nanopi_neo_plus2_defconfig
+++ b/configs/nanopi_neo_plus2_defconfig
@@ -9,6 +9,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig
index 27cf172..5c332ca 100644
--- a/configs/nanopi_r1s_h5_defconfig
+++ b/configs/nanopi_r1s_h5_defconfig
@@ -9,6 +9,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 0f69a17..f6690b4 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -25,6 +25,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttymxc1,115200 "
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index e2e8beb..b140ec8 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x81000100
diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig
index 7ce63ba..ca31394 100644
--- a/configs/oceanic_5205_5inmfd_defconfig
+++ b/configs/oceanic_5205_5inmfd_defconfig
@@ -10,6 +10,7 @@
CONFIG_MMC0_CD_PIN=""
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_SPI=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index f4ffe12..5fdc397 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -83,6 +83,7 @@
CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index 7ff8d2b..061464d 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -89,6 +89,7 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index dbf5617..97c2c83 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -87,6 +87,7 @@
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index bfd23fc..1afa6a3 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -84,6 +84,7 @@
CONFIG_SYS_64BIT_LBA=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=8192
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OCTEONTX=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index f57eb1e..6e1c29b 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -20,6 +20,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43dfff10
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index e350e22..93daa46 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -17,6 +17,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index adf9856..de33825 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -17,6 +17,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTCOMMAND="run autoboot"
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 0f73cf8..9d84209 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -13,6 +13,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 92b390c..891e144 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -13,6 +13,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then setenv boot mmc; setenv addr_fit 0x8b000000; run update_to_fit; run mmcboot; fi; run envboot; run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index e9419a4..e2c6dfc 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -17,6 +17,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index d7574f0..3237c42 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -17,6 +17,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_SYS_MONITOR_BASE=0x10000000
CONFIG_BOOTCOMMAND="run autoboot"
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 1ab91ea..51c78dc 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -83,6 +83,7 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
+CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 2d0a065..cdb246f 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -20,6 +20,7 @@
CONFIG_ENV_OFFSET_REDUND=0x180000
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index 7aaa519..000ab3e 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -7,6 +7,7 @@
CONFIG_DRAM_CLK=672
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig
index ebecf49..3debe90 100644
--- a/configs/orangepi_3_defconfig
+++ b/configs/orangepi_3_defconfig
@@ -8,6 +8,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PHY_SUN50I_USB3=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig
index 75c97d6..37d3cf7 100644
--- a/configs/orangepi_lite2_defconfig
+++ b/configs/orangepi_lite2_defconfig
@@ -7,5 +7,6 @@
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index 96bbd1b..25f5a4f 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -5,5 +5,6 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 1064b4a..094f8d1 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig
index 55a8b00..9a2abfa 100644
--- a/configs/orangepi_one_plus_defconfig
+++ b/configs/orangepi_one_plus_defconfig
@@ -7,5 +7,6 @@
CONFIG_MMC0_CD_PIN="PF6"
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 777af8c..356ae7c 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -8,6 +8,7 @@
CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 905ff7b..4d3fa77 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -5,6 +5,7 @@
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index f845138..dcdec8d 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=624
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 138a6a7..e27b329 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -7,6 +7,7 @@
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 76de72a..5c7f073 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -9,6 +9,7 @@
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SATAPWR="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig
index 95a82e2..80de7da 100644
--- a/configs/orangepi_prime_defconfig
+++ b/configs/orangepi_prime_defconfig
@@ -7,6 +7,7 @@
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig
index 4496aa4..d645168 100644
--- a/configs/orangepi_r1_defconfig
+++ b/configs/orangepi_r1_defconfig
@@ -7,6 +7,7 @@
# CONFIG_VIDEO_DE2 is not set
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig
index 3b78ad7..1e26970 100644
--- a/configs/orangepi_win_defconfig
+++ b/configs/orangepi_win_defconfig
@@ -7,6 +7,7 @@
CONFIG_MACPWR="PD14"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig
index ceef51b..877eccf 100644
--- a/configs/orangepi_zero2_defconfig
+++ b/configs/orangepi_zero2_defconfig
@@ -11,6 +11,7 @@
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index f7f3bfb..5700c1b 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -7,6 +7,7 @@
# CONFIG_VIDEO_DE2 is not set
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig
index 9583d24..6a02624 100644
--- a/configs/orangepi_zero_plus2_defconfig
+++ b/configs/orangepi_zero_plus2_defconfig
@@ -9,6 +9,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig
index 55a2513..d003612 100644
--- a/configs/orangepi_zero_plus2_h3_defconfig
+++ b/configs/orangepi_zero_plus2_h3_defconfig
@@ -8,6 +8,7 @@
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig
index f3ecf35..1628099 100644
--- a/configs/orangepi_zero_plus_defconfig
+++ b/configs/orangepi_zero_plus_defconfig
@@ -7,6 +7,7 @@
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index aafefab..0aaf899 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -21,6 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index e807491..6ffe922 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80080000
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index ca630a4..ea62e18 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=19200000
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index bc3fb3e..fb1cc68 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80080000
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 8b1d2b2..682be7d 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=19200000
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index 4a2f622..c5925b1 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=19200000
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index 0160546..8e16afd 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=19200000
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index d56c450..b5c60da 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -11,6 +11,7 @@
CONFIG_USB1_VBUS_PIN="PD12"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 558375d..135e740 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 459bfb0..65ddeb2 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -25,6 +25,7 @@
CONFIG_SPL_SPI=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmcboot;run nandboot"
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index 25f6cad..ed55f7b 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -29,6 +29,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -52,6 +53,8 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index 6c51d3d..64ddaf8 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -50,6 +51,8 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 72d87bf..ad08e35 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -29,6 +29,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -52,6 +53,8 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index d144b89..01a6198 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -50,6 +51,8 @@
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_BOOTP_BOOTFILESIZE=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 7dbaa8f..fab2550 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 0c1cad8..248631b 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 025eb32..8a27418 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index b5eea3c..987a206 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -16,6 +16,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 5a734c0..95b659a 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 529444f..863c749 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -16,6 +16,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007ffff
+CONFIG_SYS_MONITOR_LEN=196608
CONFIG_TIMESTAMP=y
CONFIG_BOOTDELAY=5
CONFIG_BOOTCOMMAND="run distro_bootcmd || run legacy_bootcmd"
diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig
index 4f352fc..1593101 100644
--- a/configs/pico-dwarf-imx6ul_defconfig
+++ b/configs/pico-dwarf-imx6ul_defconfig
@@ -21,6 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb"
diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index e0148f0..8213578 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -23,6 +23,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
CONFIG_SPL_MAX_SIZE=0xe000
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index f6f4053..0a53f1c 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -22,6 +22,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb"
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 97d9895..759866c 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -23,6 +23,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
CONFIG_SPL_MAX_SIZE=0xe000
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 8aa33f4..9b3f76d 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -20,6 +20,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 936f083..ac95b8c 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -22,6 +22,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index a94f03e..8631f81 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -21,6 +21,7 @@
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index a694d86..a84954d 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -23,6 +23,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_SPL_MAX_SIZE=0xe000
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index 8867317..1b49eb2 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -21,6 +21,7 @@
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index e0148f0..8213578 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig
@@ -23,6 +23,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb"
CONFIG_SPL_MAX_SIZE=0xe000
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index b247310..f1986ec 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -22,6 +22,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb"
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index f8509e2..dec4280 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -23,6 +23,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=715776
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
CONFIG_SPL_MAX_SIZE=0xe000
diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig
index 7e7c2d7..d8f7188 100644
--- a/configs/pine64-lts_defconfig
+++ b/configs/pine64-lts_defconfig
@@ -10,6 +10,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index f42f4e5..0fd24b5 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -6,6 +6,7 @@
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_PINE64_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
CONFIG_PHY_REALTEK=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 09a4275..578bd92 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -11,6 +11,7 @@
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig
index 26918dd..75999b2 100644
--- a/configs/pinebook_defconfig
+++ b/configs/pinebook_defconfig
@@ -8,6 +8,7 @@
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_R_I2C_ENABLE=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 28e347b..3386eda 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -8,6 +8,7 @@
CONFIG_DRAM_ODT_EN=y
CONFIG_I2C0_ENABLE=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
index 9d39204..373c8c8 100644
--- a/configs/pinephone_defconfig
+++ b/configs/pinephone_defconfig
@@ -10,6 +10,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_PINEPHONE_DT_SELECTION=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2"
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig
index 0cc2414..f579010 100644
--- a/configs/pinetab_defconfig
+++ b/configs/pinetab_defconfig
@@ -8,3 +8,4 @@
CONFIG_DRAM_ZQ=3881949
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 170ac86..0fe41c1 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index c5a2097..98a79b2 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -16,6 +16,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index 17fffeb..9b7ee4c 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index e542b71..e4b2797 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 2d250e0..f6c49da 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index aedaa9b..83cc54a 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index a62c9f8..e2ebf2b 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,6 +14,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index f269b8a..2505822 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -15,6 +15,7 @@
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index dda1a0c..dfa220b 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index 7925677..79a0fc5 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index f3335f9..b2d3712 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -16,6 +16,7 @@
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_CONS_INDEX=5
CONFIG_USB_MUSB_HOST=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index 351913f..d6ff4ac 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -8,6 +8,7 @@
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -24,6 +25,7 @@
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
+CONFIG_LOADS_ECHO=y
CONFIG_CMD_PCI=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_DHCP=y
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index 9634d7f..40ba252 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -8,6 +8,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index c3d13a5..eb9bf9b 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -9,6 +9,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index a3a899e..756e7f3 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -11,6 +11,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig
index 6045e06..cee9a1f 100644
--- a/configs/r2dplus_defconfig
+++ b/configs/r2dplus_defconfig
@@ -9,6 +9,7 @@
CONFIG_SYS_LOAD_ADDR=0x8e000000
CONFIG_ENV_ADDR=0xA0040000
CONFIG_TARGET_R2DPLUS=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xA0000000
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 8875a09..60d8d7d 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,6 +6,7 @@
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 9716ebf..fac4ab6 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -15,6 +15,7 @@
CONFIG_TARGET_EAGLE=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index a05b92d..1983c8a 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig
@@ -15,6 +15,7 @@
CONFIG_TARGET_CONDOR=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index 1ee826b..fe2a38d 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -14,6 +14,7 @@
CONFIG_TARGET_EBISU=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 12e8704..9ac70cb 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -14,6 +14,7 @@
CONFIG_TARGET_DRAAK=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig
index 7ccedf7..8cf2921 100644
--- a/configs/r8a779a0_falcon_defconfig
+++ b/configs/r8a779a0_falcon_defconfig
@@ -17,6 +17,7 @@
CONFIG_ARMV8_PSCI=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 6749f81..cba0ce5 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -13,6 +13,7 @@
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
# CONFIG_BOOTSTD is not set
CONFIG_SUPPORT_RAW_INITRD=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index f462bab..43361a2 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -14,6 +14,7 @@
CONFIG_TARGET_ULCB=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_MONITOR_BASE=0x00000000
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index f462844..1bf4027 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -22,6 +22,7 @@
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig
index ffcbd35..4ed98c0 100644
--- a/configs/rock-pi-n8-rk3288_defconfig
+++ b/configs/rock-pi-n8-rk3288_defconfig
@@ -18,6 +18,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 1570a71..38a5f3a 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -17,6 +17,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig
index d3e77c6..3678705 100644
--- a/configs/rzg2_beacon_defconfig
+++ b/configs/rzg2_beacon_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_LTO=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 4f29a2b..f2cfed5 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -14,6 +14,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x33000000
+CONFIG_SYS_MONITOR_LEN=262144
# CONFIG_AUTOBOOT is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}"
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 84e6c0f..160e338 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -18,6 +18,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x447fff10
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="Please use defined boot"
CONFIG_BOOTCOMMAND="run mmcboot"
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index 27497c5..d08a42d 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index c1b4e00..93ae714 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -25,6 +25,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 9eb65bb..5096366 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 2339425..d7c7f42 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 801ce79..7634a6c 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -24,6 +24,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index ede7081..bb018d4 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -24,6 +24,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_SPI_BOOT=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 8e2e160..51f7104 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -24,6 +24,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig
index 2536d40..ab73088 100644
--- a/configs/sama5d2_icp_qspiflash_defconfig
+++ b/configs/sama5d2_icp_qspiflash_defconfig
@@ -18,6 +18,7 @@
CONFIG_SYS_BOOT_GET_KBD=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index ba66d9f..9509091 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -25,6 +25,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index a30b0cb..fe267f3 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index 6daedb8..7fc5dad 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 9e0c07c..95e2b44 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index 61a0320..22748d2 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -16,6 +16,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index 8d8526b..e6ca89a 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -16,6 +16,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 114175d..f1cd95c 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -18,6 +18,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 41f2c36..f82103e 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index e2e9d1d..a3bc040 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -23,6 +23,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 9bab96d..b3108fa 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 3132671..f06c21f 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -23,6 +23,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index a60f925..2045146 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index ace2dd3..061cec9 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index cfc168c..d11d882 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -23,6 +23,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 419067c..5822825 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 6236430..69a9f6c 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -26,6 +26,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index ea82684..6d8b796 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -23,6 +23,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 108133e..79b9a7d 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 686a3c0..40d8836 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig
index b239d22..34d23fd 100644
--- a/configs/seeed_npi_imx6ull_defconfig
+++ b/configs/seeed_npi_imx6ull_defconfig
@@ -17,6 +17,7 @@
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig
index 2ef2f7c..378e175 100644
--- a/configs/silinux_ek874_defconfig
+++ b/configs/silinux_ek874_defconfig
@@ -15,6 +15,7 @@
CONFIG_TARGET_SILINUX_EK874=y
CONFIG_SYS_LOAD_ADDR=0x58000000
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 38a1476..9ff9e23 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index 1476935..e525b80 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -15,6 +15,7 @@
CONFIG_ENV_ADDR=0x40000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)"
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index cdfc8b7..714c111 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -18,6 +18,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTCOMMAND="fatload mmc 0 40007000 uImage; bootm 40007000"
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_FOOTPRINT_LIMIT=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 167e05b..6844092 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -71,6 +71,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index e5864eb..de9ebd0 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -65,6 +65,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index bcdeb6d..7642498 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -72,6 +72,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 6fe8d55..08ae6c5 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -55,6 +55,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 2632c0a..2951574 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -54,6 +54,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 451de03..9c3c0f6 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -54,6 +54,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index 7786843..b3ba9ff 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -63,6 +63,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index cfc8b50..5f5706f 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -54,6 +54,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 53c4ff5..1f835be 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -51,6 +51,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig
index 15d4599..412b0da 100644
--- a/configs/socfpga_de10_standard_defconfig
+++ b/configs/socfpga_de10_standard_defconfig
@@ -51,6 +51,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 2a15936..68a3689 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -48,6 +48,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 35ea73a..8be8b85 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -54,6 +54,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index 453fd87..0feda3b 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -70,6 +70,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index ae71791..fa19f55 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -62,6 +62,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index 259b8dd..12e8ebf 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -71,6 +71,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index a6106f2..debe22f 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -83,6 +83,7 @@
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 0539d29..31cc03a 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -54,6 +54,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index a81f74d..72a7037 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -54,6 +54,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 59d809c..44e9ba6 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -61,6 +61,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_SPEED=100000000
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index acb1ce9..5ee9f5f 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -72,6 +72,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 90a44f2..f689105 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -69,6 +69,7 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 3a99667..96c0ebb 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -88,6 +88,7 @@
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_SPEED=40000000
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index cd04e0e..b89c348 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -7,9 +7,11 @@
CONFIG_ENV_ADDR=0xFFF40000
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SOCRATES=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_MONITOR_LEN=393216
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@@ -32,6 +34,8 @@
CONFIG_CMD_IMLS=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig
index fbbef7a..84890d8 100644
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -11,6 +11,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SUN8I_EMAC=y
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index f5ed3b1..9fc3463 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -12,6 +12,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 9e39088..45b8459 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -21,6 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 764ccf5..924ca0d 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -12,6 +12,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index 2c58aef..877616d 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -21,6 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index b55569a..35b9c03 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -12,6 +12,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index 6e37f6a..706fbb6 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -21,6 +21,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
index 99074c9..5ee2edc 100644
--- a/configs/stmark2_defconfig
+++ b/configs/stmark2_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_STMARK2=y
CONFIG_MCFTMR=y
CONFIG_SYS_BARGSIZE=256
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_TIMESTAMP=y
CONFIG_SYS_MONITOR_BASE=0x47E00400
CONFIG_USE_BOOTARGS=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 8028c2d..231e22a 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -28,6 +28,7 @@
CONFIG_ENV_ADDR=0xC0000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SPL_MAX_SIZE=0x4000
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
index a3b1d76..1480158 100644
--- a/configs/sun8i_a23_evb_defconfig
+++ b/configs/sun8i_a23_evb_defconfig
@@ -9,6 +9,7 @@
CONFIG_USB0_VBUS_DET="axp_vbus_detect"
CONFIG_USB1_VBUS_PIN="PH7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONS_INDEX=5
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 3fee7c2..b67d1fb 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,6 +11,7 @@
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig
index 0390347..d8095d0 100644
--- a/configs/tanix_tx6_defconfig
+++ b/configs/tanix_tx6_defconfig
@@ -8,3 +8,4 @@
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig
index b3c2e69..6c3d5d4 100644
--- a/configs/tbs_a711_defconfig
+++ b/configs/tbs_a711_defconfig
@@ -13,6 +13,7 @@
CONFIG_USB0_ID_DET="PH11"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_AXP_DCDC5_VOLT=1200
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 02d6b49..1caac5a 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 967d305..852d73e 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig
index e7de85e..64fa2a9 100644
--- a/configs/teres_i_defconfig
+++ b/configs/teres_i_defconfig
@@ -8,6 +8,7 @@
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_I2C0_ENABLE=y
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start"
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 998b2ab..85d94a6 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -18,6 +18,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 39b6914..7dfbad8 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -18,6 +18,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb"
diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig
index f9901a4..807e9eb 100644
--- a/configs/total_compute_defconfig
+++ b/configs/total_compute_defconfig
@@ -48,6 +48,7 @@
CONFIG_CLK=y
# CONFIG_MMC_WRITE is not set
CONFIG_ARM_PL180_MMCI=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=127
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index a8ede1e..1ce3f50 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -19,6 +19,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43dfff10
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 406d6bc..a294228 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -18,6 +18,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x447fff10
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTARGS=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index a9f774c..5da3a27 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 3577745..3b8560f 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_TUGE1=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
@@ -122,6 +123,7 @@
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -142,6 +144,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 3711d22..04ce0b3 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -9,6 +9,7 @@
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_TUXX1=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
@@ -144,6 +145,7 @@
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_83XX_PCICLK=0x3ef1480
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
@@ -164,6 +166,8 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
CONFIG_CMD_I2C=y
+CONFIG_LOADS_ECHO=y
+CONFIG_SYS_LOADS_BAUD_CHANGE=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 57f2ba4..0a3baec 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index 8ae9fa5..95428e1 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -20,6 +20,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_SPL_MALLOC=y
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 4050266..5665cf3 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
+CONFIG_SYS_MONITOR_LEN=2097152
CONFIG_TIMESTAMP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 513fbd1..e3087a9 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -12,6 +12,7 @@
CONFIG_SYS_LOAD_ADDR=0x85000000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000
+CONFIG_SYS_MONITOR_LEN=2097152
CONFIG_TIMESTAMP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index d202508..1b0e0d0 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -9,6 +9,7 @@
CONFIG_ARCH_UNIPHIER_V8_MULTI=y
CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_LOAD_ADDR=0x85000000
+CONFIG_SYS_MONITOR_LEN=2097152
CONFIG_TIMESTAMP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index b0f5f8f..67ac97c 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -15,6 +15,7 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_BOOTCOMMAND="run mmc_mmc_fit"
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index a754c20..226480b 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x80110000
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 3c924ec..7a5e47b 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_SYS_L2CACHE_OFF=y
CONFIG_ARCH_TEGRA=y
CONFIG_TEXT_BASE=0x00110000
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 7bb4b88..62f8588 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -21,6 +21,7 @@
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index ed54132..bae8179 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -27,6 +27,7 @@
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig
index 25e5d39..234686e 100644
--- a/configs/vexpress_ca9x4_defconfig
+++ b/configs/vexpress_ca9x4_defconfig
@@ -39,6 +39,7 @@
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_CLK=y
CONFIG_ARM_PL180_MMCI=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=127
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 6efd1ab..3b5658d 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -23,6 +23,7 @@
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SUPPORT_RAW_INITRD=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index bd7af0a..cbae60f 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -18,6 +18,7 @@
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SYS_MONITOR_LEN=614400
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
CONFIG_SILENT_CONSOLE=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 33d9db5..525f55e 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -23,6 +23,7 @@
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index d30ebf1..127bbf7 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -22,6 +22,7 @@
CONFIG_SYS_LOAD_ADDR=0x80008000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007ff20
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS2,115200n8"
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index 4276f4f..41a1c47 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -7,6 +7,7 @@
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_R_I2C_ENABLE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig
index 1242e35..3148329 100644
--- a/configs/xtfpga_defconfig
+++ b/configs/xtfpga_defconfig
@@ -8,6 +8,7 @@
CONFIG_SYS_LOAD_ADDR=0x02000000
CONFIG_ENV_ADDR=0xF7FE0000
CONFIG_XTFPGA_KC705=y
+CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SYS_MONITOR_BASE=0xF6000000
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_SHOW_BOOT_PROGRESS=y
diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig
index 11f3715..8365da2 100644
--- a/configs/zeropi_defconfig
+++ b/configs/zeropi_defconfig
@@ -7,6 +7,7 @@
CONFIG_MACPWR="PD6"
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_MONITOR_LEN=786432
CONFIG_CONSOLE_MUX=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
diff --git a/disk/part.c b/disk/part.c
index f982b30..2eb30eb 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -139,7 +139,7 @@
case UCLASS_USB:
case UCLASS_NVME:
case UCLASS_PVBLOCK:
- case UCLASS_ROOT:
+ case UCLASS_HOST:
printf ("Vendor: %s Rev: %s Prod: %s\n",
dev_desc->vendor,
dev_desc->revision,
@@ -264,7 +264,7 @@
case UCLASS_MMC:
puts ("MMC");
break;
- case UCLASS_ROOT:
+ case UCLASS_HOST:
puts ("HOST");
break;
case UCLASS_NVME:
diff --git a/doc/README.JFFS2 b/doc/README.JFFS2
deleted file mode 100644
index 0245da0..0000000
--- a/doc/README.JFFS2
+++ /dev/null
@@ -1,40 +0,0 @@
-JFFS2 options and usage.
------------------------
-
-JFFS2 in U-Boot is a read only implementation of the file system in
-Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2.
-
-The module adds three new commands.
-fsload - load binary file from a file system image
-fsinfo - print information about file systems
-ls - list files in a directory
-chpart - change active partition
-
-If you do now need the commands, you can enable the filesystem separately
-with CONFIG_FS_JFFS2 and call the jffs2 functions yourself.
-
-If you boot from a partition which is mounted writable, and you
-update your boot environment by replacing single files on that
-partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. Scanning
-the JFFS2 filesystem takes *much* longer with this feature, though.
-Sorting is done while inserting into the fragment list, which is
-more or less a bubble sort. That algorithm is known to be O(n^2),
-thus you should really consider if you can avoid it!
-
-
-There only one way for JFFS2 to find the disk. It uses the flash_info
-structure to find the start of a JFFS2 disk (called partition in the code)
-and you can change where the partition is with two defines.
-
-CONFIG_SYS_JFFS2_FIRST_BANK
- defined the first flash bank to use
-
-CONFIG_SYS_JFFS2_FIRST_SECTOR
- defines the first sector to use
----
-
-TODO.
-
- Remove the assumption that JFFS can dereference a pointer
- into the disk. The current code do not work with memory holes
- or hardware with a sliding window (PCMCIA).
diff --git a/doc/README.nand b/doc/README.nand
index ffcea90..d1ce307 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -99,9 +99,6 @@
CONFIG_CMD_NAND_TORTURE
Enables the torture command (see description of this command below).
- CONFIG_SYS_MAX_NAND_DEVICE
- The maximum number of NAND devices you want to support.
-
CONFIG_SYS_NAND_MAX_ECCPOS
If specified, overrides the maximum number of ECC bytes
supported. Useful for reducing image size, especially with SPL.
diff --git a/doc/arch/index.rst b/doc/arch/index.rst
index 792d918..b3e85f9 100644
--- a/doc/arch/index.rst
+++ b/doc/arch/index.rst
@@ -11,7 +11,7 @@
m68k
mips
nios2
- sandbox
+ sandbox/index
sh
x86
xtensa
diff --git a/doc/arch/sandbox/block_impl.rst b/doc/arch/sandbox/block_impl.rst
new file mode 100644
index 0000000..344c74f
--- /dev/null
+++ b/doc/arch/sandbox/block_impl.rst
@@ -0,0 +1,39 @@
+.. SPDX-License-Identifier: GPL-2.0+ */
+.. Copyright (c) 2014 The Chromium OS Authors.
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Sandbox block devices (implementation)
+======================================
+
+(See :ref:`sandbox_blk` for operation)
+
+Sandbox block devices are implemented using the `UCLASS_HOST` uclass. Only one
+driver is provided (`host_sb_drv`) so all devices in the uclass use the same
+driver.
+
+The uclass has a simple API allowing files to be attached and detached.
+Attaching a file results in it appearing as a block device in sandbox. This
+allows filesystems and whole disk images to be accessed from U-Boot. This is
+particularly useful for tests.
+
+Devices are created using `host_create_device()`. This sets up a new
+`UCLASS_HOST`.
+
+The device can then be attached to a file with `host_attach_file()`. This
+creates the child block device (and bootdev device).
+
+The host device's block device must be probed before use, as normal.
+
+To destroy a device, call host_destroy_device(). This removes the device (and
+its children of course), then closes any attached file, then unbinds the device.
+
+There is no arbitrary limit to the number of host devices that can be created.
+
+
+Uclass API
+----------
+
+This is incomplete as it isn't clear how to make Sphinx do the right thing for
+struct host_ops. See `include/sandbox_host.h` for full details.
+
+.. kernel-doc:: include/sandbox_host.h
diff --git a/doc/arch/sandbox/index.rst b/doc/arch/sandbox/index.rst
new file mode 100644
index 0000000..1f1f5de
--- /dev/null
+++ b/doc/arch/sandbox/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0+ */
+.. Copyright 2022 Google LLC
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Sandbox
+=======
+
+.. toctree::
+ :maxdepth: 2
+
+ sandbox
+ block_impl
diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox/sandbox.rst
similarity index 98%
rename from doc/arch/sandbox.rst
rename to doc/arch/sandbox/sandbox.rst
index ed66f70..34c4e06 100644
--- a/doc/arch/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -43,7 +43,7 @@
Prerequisites
-------------
-Install the dependencies noted in :doc:`../build/gcc`.
+Install the dependencies noted in :doc:`../../build/gcc`.
Basic Operation
@@ -374,6 +374,7 @@
This is issuing a READ_ID command and getting back 20 (ST Micro) part
0x2015 (the M25P16).
+.. _sandbox_blk:
Block Device Emulation
----------------------
@@ -401,6 +402,8 @@
import make_test_disk
make_test_disk.makeDisk()
+For more technical details, see :doc:`block_impl`.
+
Writing Sandbox Drivers
-----------------------
@@ -600,8 +603,8 @@
U-Boot sandbox can be used to run various tests, mostly in the test/
directory.
-See :doc:`../develop/tests_sandbox` for more information and
-:doc:`../develop/testing` for information about testing generally.
+See :doc:`../../develop/tests_sandbox` for more information and
+:doc:`../../develop/testing` for information about testing generally.
Memory Map
diff --git a/doc/develop/tests_sandbox.rst b/doc/develop/tests_sandbox.rst
index 8e42a32..bfd3bdb 100644
--- a/doc/develop/tests_sandbox.rst
+++ b/doc/develop/tests_sandbox.rst
@@ -143,6 +143,75 @@
Test dm_test_rtc_reset failed 3 times
+Isolating a test that breaks another
+------------------------------------
+
+When running unit tests, some may have side effects which cause a subsequent
+test to break. This can sometimes be seen when using 'ut dm' or similar.
+
+You can use the `-I` argument to the `ut` command to isolate this problem.
+First use `ut info` to see how many tests there are, then use a binary search to
+home in on the problem. Note that you might need to restart U-Boot after each
+iteration, so the `-c` argument to U-Boot is useful.
+
+For example, let's stay that dm_test_host() is failing::
+
+ => ut dm
+ ...
+ Test: dm_test_get_stats: core.c
+ Test: dm_test_get_stats: core.c (flat tree)
+ Test: dm_test_host: host.c
+ test/dm/host.c:71, dm_test_host(): 0 == ut_check_delta(mem_start): Expected 0x0 (0), got 0xffffcbb0 (-13392)
+ Test: dm_test_host: host.c (flat tree)
+ Test <NULL> failed 1 times
+ Test: dm_test_host_dup: host.c
+ Test: dm_test_host_dup: host.c (flat tree)
+ ...
+
+You can then tell U-Boot to run the failing test at different points in the
+sequence:
+
+ => ut info
+ Test suites: 21
+ Total tests: 645
+
+::
+
+ $ ./u-boot -T -c "ut dm -I300:dm_test_host"
+ ...
+ Test: dm_test_pinctrl_single: pinmux.c (flat tree)
+ Test: dm_test_host: host.c
+ test/dm/host.c:71, dm_test_host(): 0 == ut_check_delta(mem_start): Expected 0x0 (0), got 0xfffffdb0 (-592)
+ Test: dm_test_host: host.c (flat tree)
+ Test dm_test_host failed 1 times (position 300)
+ Failures: 4
+
+So it happened before position 300. Trying 150 shows it failing, so we try 75::
+
+ $ ./u-boot -T -c "ut dm -I75:dm_test_host"
+ ...
+ Test: dm_test_autoprobe: core.c
+ Test: dm_test_autoprobe: core.c (flat tree)
+ Test: dm_test_host: host.c
+ Test: dm_test_host: host.c (flat tree)
+ Failures: 0
+
+That succeeds, so we try 120, etc. until eventually we can figure out that the
+problem first happens at position 82.
+
+ $ ./u-boot -T -c "ut dm -I82:dm_test_host"
+ ...
+ Test: dm_test_blk_flags: blk.c
+ Test: dm_test_blk_flags: blk.c (flat tree)
+ Test: dm_test_host: host.c
+ test/dm/host.c:71, dm_test_host(): 0 == ut_check_delta(mem_start): Expected 0x0 (0), got 0xffffc960 (-13984)
+ Test: dm_test_host: host.c (flat tree)
+ Test dm_test_host failed 1 times (position 82)
+ Failures: 1
+
+From this we can deduce that `dm_test_blk_flags()` causes the problem with
+`dm_test_host()`.
+
Running sandbox_spl tests directly
----------------------------------
diff --git a/doc/usage/cmd/host.rst b/doc/usage/cmd/host.rst
new file mode 100644
index 0000000..e145089
--- /dev/null
+++ b/doc/usage/cmd/host.rst
@@ -0,0 +1,116 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+host command
+============
+
+Synopis
+-------
+
+::
+
+ host bind [-r] <label> [<filename>]
+ host unbind <label|seq>
+ host info [<label|seq>]
+ host dev [<label|seq>]
+
+Description
+-----------
+
+The host command provides a way to attach disk images on the host to U-Boot
+sandbox. This can be useful for testing U-Boot's filesystem implementations.
+
+Common arguments:
+
+<label|seq>
+ This is used to specify a host device. It can either be a label (a string)
+ or the sequence number of the device. An invalid value causes the command
+ to fail.
+
+
+host bind
+~~~~~~~~~
+
+This creates a new host device and binds a file to it.
+
+Arguments:
+
+label
+ Label to use to identify this binding. This can be any string.
+
+filename:
+ Host filename to bind to
+
+Flags:
+
+-r
+ Mark the device as removable
+
+
+host unbind
+~~~~~~~~~~~
+
+This unbinds a host device that was previously bound. The sequence numbers of
+other devices remain unchanged.
+
+
+host info
+~~~~~~~~~
+
+Provides information about a particular host binding, or all of them.
+
+
+host dev
+~~~~~~~~
+
+Allowing selecting a particular device, or (with no arguments) seeing which one
+is selected.
+
+
+Example
+-------
+
+Initially there are no devices::
+
+ => host info
+ dev blocks label path
+
+Bind a device::
+
+ => host bind -r test2 2MB.ext2.img
+ => host bind fat 1MB.fat32.img
+ => host info
+ dev blocks label path
+ 0 4096 test2 2MB.ext2.img
+ 1 2048 fat 1MB.fat32.img
+
+Select a device by label or sequence number::
+
+ => host dev fat
+ Current host device: 1: fat
+ => host dev 0
+ Current host device: 0: test2
+
+Write a file::
+
+ => ext4write host 0 0 /dump 1e00
+ File System is consistent
+ 7680 bytes written in 3 ms (2.4 MiB/s)
+ => ext4ls host 0
+ <DIR> 4096 .
+ <DIR> 4096 ..
+ <DIR> 16384 lost+found
+ 4096 testing
+ 7680 dump
+
+Unbind a device::
+
+ => host unbind test2
+ => host info
+ dev blocks label path
+ 1 2048 fat 1MB.fat32.img
+
+
+Return value
+------------
+
+The return value $? indicates whether the command succeeded.
diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst
new file mode 100644
index 0000000..a303963
--- /dev/null
+++ b/doc/usage/cmd/ut.rst
@@ -0,0 +1,117 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+ut command
+==========
+
+Synopis
+-------
+
+::
+
+ ut [-r<runs>] [-f] [-I<n>:<one_test>] [<suite> [<test>]]
+
+ <runs> Number of times to run each test
+ -f Force 'manual' tests to run as well
+ <n> Run <one test> after <n> other tests have run
+ <one_test> Name of the 'one' test to run
+ <suite> Test suite to run, or `all`
+ <test> Name of single test to run
+
+Description
+-----------
+
+The ut command runs unit tests written in C.
+
+Typically the command is run on :ref:`arch/sandbox/sandbox:sandbox` since it
+includes a near-complete set of emulators, no code-size limits, many CONFIG
+options enabled and runs easily in CI without needing QEMU. It is also possible
+to run some tests on real boards.
+
+For a list of available test suites, type `ut` by itself.
+
+Each test is normally run once, although those marked with `UT_TESTF_DM` are
+run with livetree and flattree where possible. To run a test more than once,
+use the `-r` flag.
+
+Manual tests are normally skipped by this command. Use `-f` to run them. See
+See :ref:`develop/tests_writing:mixing python and c` for more information on
+manual test.
+
+When running unit tests, some may have side effects which cause a subsequent
+test to break. This can sometimes be seen when using 'ut dm' or similar. To
+fix this, select the 'one' test which breaks. Then tell the 'ut' command to
+run this one test after a certain number of other tests have run. Using a
+binary search method with `-I` you can quickly figure one which test is causing
+the problem.
+
+Generally all tests in the suite are run. To run just a single test from the
+suite, provide the <test> argument.
+
+See :ref:`develop/tests_writing:writing c tests` for more information on how to
+write unit tests.
+
+Example
+-------
+
+List available unit-test suites::
+
+ => ut
+ ut - unit tests
+
+ Usage:
+ ut [-r] [-f] [<suite>] - run unit tests
+ -r<runs> Number of times to run each test
+ -f Force 'manual' tests to run as well
+ <suite> Test suite to run, or all
+
+ Suites:
+ all - execute all enabled tests
+ addrmap - very basic test of addrmap command
+ bloblist - bloblist implementation
+ bootstd - standard boot implementation
+ compression - compressors and bootm decompression
+ dm - driver model
+ env - environment
+ fdt - fdt command
+ loadm - loadm command parameters and loading memory blob
+ lib - library functions
+ log - logging functions
+ mem - memory-related commands
+ overlay - device tree overlays
+ print - printing things to the console
+ setexpr - setexpr command
+ str - basic test of string functions
+ time - very basic test of time functions
+ unicode - Unicode functions
+
+Run one of the suites::
+
+ => ut bloblist
+ Running 14 bloblist tests
+ Test: bloblist_test_align: bloblist.c
+ Test: bloblist_test_bad_blob: bloblist.c
+ Test: bloblist_test_blob: bloblist.c
+ Test: bloblist_test_blob_ensure: bloblist.c
+ Test: bloblist_test_blob_maxsize: bloblist.c
+ Test: bloblist_test_checksum: bloblist.c
+ Test: bloblist_test_cmd_info: bloblist.c
+ Test: bloblist_test_cmd_list: bloblist.c
+ Test: bloblist_test_grow: bloblist.c
+ Test: bloblist_test_init: bloblist.c
+ Test: bloblist_test_reloc: bloblist.c
+ Test: bloblist_test_resize_fail: bloblist.c
+ Test: bloblist_test_resize_last: bloblist.c
+ Test: bloblist_test_shrink: bloblist.c
+ Failures: 0
+
+Run just a single test in a suite::
+
+ => ut bloblist bloblist_test_grow
+ Test: bloblist_test_grow: bloblist.c
+ Failures: 0
+
+Show information about tests::
+
+ => ut info
+ Test suites: 21
+ Total tests: 642
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index df50746..f7f03ae 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -52,6 +52,7 @@
cmd/for
cmd/fwu_mdata
cmd/gpio
+ cmd/host
cmd/load
cmd/loadm
cmd/loady
@@ -74,6 +75,7 @@
cmd/tftpput
cmd/true
cmd/ums
+ cmd/ut
cmd/wdt
cmd/xxd
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 19d9317..f12447d 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -12,7 +12,7 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_IDE) += ide.o
endif
-obj-$(CONFIG_SANDBOX) += sandbox.o
+obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o
obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index e82789f..c69fc4d 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -26,7 +26,7 @@
{ UCLASS_USB, "usb" },
{ UCLASS_MMC, "mmc" },
{ UCLASS_AHCI, "sata" },
- { UCLASS_ROOT, "host" },
+ { UCLASS_HOST, "host" },
{ UCLASS_NVME, "nvme" },
{ UCLASS_EFI_MEDIA, "efi" },
{ UCLASS_EFI_LOADER, "efiloader" },
@@ -369,45 +369,43 @@
return blk_select_hwpart(desc->bdev, hwpart);
}
-int blk_first_device(int uclass_id, struct udevice **devp)
+static int _blk_next_device(int uclass_id, struct udevice **devp)
{
struct blk_desc *desc;
- int ret;
+ int ret = 0;
- ret = uclass_find_first_device(UCLASS_BLK, devp);
+ for (; *devp; uclass_find_next_device(devp)) {
+ desc = dev_get_uclass_plat(*devp);
+ if (desc->uclass_id == uclass_id) {
+ ret = device_probe(*devp);
+ if (!ret)
+ return 0;
+ }
+ }
+
if (ret)
return ret;
- if (!*devp)
- return -ENODEV;
- do {
- desc = dev_get_uclass_plat(*devp);
- if (desc->uclass_id == uclass_id)
- return 0;
- ret = uclass_find_next_device(devp);
- if (ret)
- return ret;
- } while (*devp);
return -ENODEV;
}
+int blk_first_device(int uclass_id, struct udevice **devp)
+{
+ uclass_find_first_device(UCLASS_BLK, devp);
+
+ return _blk_next_device(uclass_id, devp);
+}
+
int blk_next_device(struct udevice **devp)
{
struct blk_desc *desc;
- int ret, uclass_id;
+ int uclass_id;
desc = dev_get_uclass_plat(*devp);
uclass_id = desc->uclass_id;
- do {
- ret = uclass_find_next_device(devp);
- if (ret)
- return ret;
- if (!*devp)
- return -ENODEV;
- desc = dev_get_uclass_plat(*devp);
- if (desc->uclass_id == uclass_id)
- return 0;
- } while (1);
+ uclass_find_next_device(devp);
+
+ return _blk_next_device(uclass_id, devp);
}
int blk_find_device(int uclass_id, int devnum, struct udevice **devp)
@@ -508,24 +506,28 @@
return blk_erase(desc->bdev, start, blkcnt);
}
-int blk_get_from_parent(struct udevice *parent, struct udevice **devp)
+int blk_find_from_parent(struct udevice *parent, struct udevice **devp)
{
struct udevice *dev;
- enum uclass_id id;
- int ret;
- device_find_first_child(parent, &dev);
- if (!dev) {
+ if (device_find_first_child_by_uclass(parent, UCLASS_BLK, &dev)) {
debug("%s: No block device found for parent '%s'\n", __func__,
parent->name);
return -ENODEV;
}
- id = device_get_uclass_id(dev);
- if (id != UCLASS_BLK) {
- debug("%s: Incorrect uclass %s for block device '%s'\n",
- __func__, uclass_get_name(id), dev->name);
- return -ENOTBLK;
- }
+ *devp = dev;
+
+ return 0;
+}
+
+int blk_get_from_parent(struct udevice *parent, struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = blk_find_from_parent(parent, &dev);
+ if (ret)
+ return ret;
ret = device_probe(dev);
if (ret)
return ret;
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index b53420a..f99465a 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -150,8 +150,8 @@
list_for_each_safe(entry, n, &block_cache) {
node = (struct block_cache_node *)entry;
- if ((node->iftype == iftype) &&
- (node->devnum == devnum)) {
+ if (iftype == -1 ||
+ (node->iftype == iftype && node->devnum == devnum)) {
list_del(entry);
free(node->cache);
free(node);
@@ -162,18 +162,10 @@
void blkcache_configure(unsigned blocks, unsigned entries)
{
- struct block_cache_node *node;
+ /* invalidate cache if there is a change */
if ((blocks != _stats.max_blocks_per_entry) ||
- (entries != _stats.max_entries)) {
- /* invalidate cache */
- while (!list_empty(&block_cache)) {
- node = (struct block_cache_node *)block_cache.next;
- list_del(&node->lh);
- free(node->cache);
- free(node);
- }
- _stats.entries = 0;
- }
+ (entries != _stats.max_entries))
+ blkcache_invalidate(-1, 0);
_stats.max_blocks_per_entry = blocks;
_stats.max_entries = entries;
@@ -188,3 +180,8 @@
_stats.hits = 0;
_stats.misses = 0;
}
+
+void blkcache_free(void)
+{
+ blkcache_invalidate(-1, 0);
+}
diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c
new file mode 100644
index 0000000..6460d96
--- /dev/null
+++ b/drivers/block/host-uclass.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Uclass for sandbox host interface, used to access files on the host which
+ * contain partitions and filesystem
+ *
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_HOST
+
+#include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <sandbox_host.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct host_priv - information kept by the host uclass
+ *
+ * @cur_dev: Currently selected host device, or NULL if none
+ */
+struct host_priv {
+ struct udevice *cur_dev;
+};
+
+int host_create_device(const char *label, bool removable, struct udevice **devp)
+{
+ char dev_name[30], *str, *label_new;
+ struct host_sb_plat *plat;
+ struct udevice *dev, *blk;
+ int ret;
+
+ /* unbind any existing device with this label */
+ dev = host_find_by_label(label);
+ if (dev) {
+ ret = host_detach_file(dev);
+ if (ret)
+ return log_msg_ret("det", ret);
+
+ ret = device_unbind(dev);
+ if (ret)
+ return log_msg_ret("unb", ret);
+ }
+
+ snprintf(dev_name, sizeof(dev_name), "host-%s", label);
+ str = strdup(dev_name);
+ if (!str)
+ return -ENOMEM;
+
+ label_new = strdup(label);
+ if (!label_new) {
+ ret = -ENOMEM;
+ goto no_label;
+ }
+
+ ret = device_bind_driver(gd->dm_root, "host_sb_drv", str, &dev);
+ if (ret)
+ goto no_dev;
+ device_set_name_alloced(dev);
+
+ if (!blk_find_from_parent(dev, &blk)) {
+ struct blk_desc *desc = dev_get_uclass_plat(blk);
+
+ desc->removable = removable;
+ }
+
+ plat = dev_get_plat(dev);
+ plat->label = label_new;
+ *devp = dev;
+
+ return 0;
+
+no_dev:
+ free(label_new);
+no_label:
+ free(str);
+
+ return ret;
+}
+
+int host_attach_file(struct udevice *dev, const char *filename)
+{
+ struct host_ops *ops = host_get_ops(dev);
+
+ if (!ops->attach_file)
+ return -ENOSYS;
+
+ return ops->attach_file(dev, filename);
+}
+
+int host_create_attach_file(const char *label, const char *filename,
+ bool removable, struct udevice **devp)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = host_create_device(label, removable, &dev);
+ if (ret)
+ return log_msg_ret("cre", ret);
+
+ ret = host_attach_file(dev, filename);
+ if (ret) {
+ device_unbind(dev);
+ return log_msg_ret("att", ret);
+ }
+ *devp = dev;
+
+ return 0;
+}
+
+int host_detach_file(struct udevice *dev)
+{
+ struct host_ops *ops = host_get_ops(dev);
+
+ if (!ops->detach_file)
+ return -ENOSYS;
+
+ if (dev == host_get_cur_dev())
+ host_set_cur_dev(NULL);
+
+ return ops->detach_file(dev);
+}
+
+struct udevice *host_find_by_label(const char *label)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+
+ uclass_id_foreach_dev(UCLASS_HOST, dev, uc) {
+ struct host_sb_plat *plat = dev_get_plat(dev);
+
+ if (plat->label && !strcmp(label, plat->label))
+ return dev;
+ }
+
+ return NULL;
+}
+
+struct udevice *host_get_cur_dev(void)
+{
+ struct uclass *uc = uclass_find(UCLASS_HOST);
+
+ if (uc) {
+ struct host_priv *priv = uclass_get_priv(uc);
+
+ return priv->cur_dev;
+ }
+
+ return NULL;
+}
+
+void host_set_cur_dev(struct udevice *dev)
+{
+ struct uclass *uc = uclass_find(UCLASS_HOST);
+
+ if (uc) {
+ struct host_priv *priv = uclass_get_priv(uc);
+
+ priv->cur_dev = dev;
+ }
+}
+
+UCLASS_DRIVER(host) = {
+ .id = UCLASS_HOST,
+ .name = "host",
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .post_bind = dm_scan_fdt_dev,
+#endif
+ .priv_auto = sizeof(struct host_priv),
+};
diff --git a/drivers/block/host_dev.c b/drivers/block/host_dev.c
new file mode 100644
index 0000000..5885fc3
--- /dev/null
+++ b/drivers/block/host_dev.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for sandbox host interface, used to access files on the host which
+ * contain partitions and filesystem
+ *
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_HOST
+
+#include <common.h>
+#include <blk.h>
+#include <bootdev.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <os.h>
+#include <sandbox_host.h>
+#include <dm/device-internal.h>
+
+static int host_sb_attach_file(struct udevice *dev, const char *filename)
+{
+ struct host_sb_plat *plat = dev_get_plat(dev);
+ struct blk_desc *desc;
+ struct udevice *blk;
+ int ret, fd, size;
+ char *fname;
+
+ if (!filename)
+ return -EINVAL;
+
+ if (plat->fd)
+ return log_msg_ret("fd", -EEXIST);
+
+ /* Sanity check that host_sb_bind() has been used */
+ ret = blk_find_from_parent(dev, &blk);
+ if (ret)
+ return ret;
+
+ fd = os_open(filename, OS_O_RDWR);
+ if (fd == -1) {
+ printf("Failed to access host backing file '%s', trying read-only\n",
+ filename);
+ fd = os_open(filename, OS_O_RDONLY);
+ if (fd == -1) {
+ printf("- still failed\n");
+ return log_msg_ret("open", -ENOENT);
+ }
+ }
+
+ fname = strdup(filename);
+ if (!fname) {
+ ret = -ENOMEM;
+ goto err_fname;
+ }
+
+ size = os_filesize(fd);
+ desc = dev_get_uclass_plat(blk);
+ desc->lba = size / desc->blksz;
+
+ /* write this in last, when nothing can go wrong */
+ plat = dev_get_plat(dev);
+ plat->fd = fd;
+ plat->filename = fname;
+
+ return 0;
+
+err_fname:
+ os_close(fd);
+
+ return ret;
+}
+
+int host_sb_detach_file(struct udevice *dev)
+{
+ struct host_sb_plat *plat = dev_get_plat(dev);
+ int ret;
+
+ if (!plat->fd)
+ return log_msg_ret("fd", -ENOENT);
+
+ ret = device_remove(dev, DM_REMOVE_NORMAL);
+ if (ret)
+ return log_msg_ret("rem", ret);
+
+ /* Unbind all children */
+ ret = device_chld_unbind(dev, NULL);
+ if (ret)
+ return log_msg_ret("unb", ret);
+
+ os_close(plat->fd);
+ plat->fd = 0;
+ free(plat->filename);
+ free(plat->label);
+
+ return 0;
+}
+
+static int host_sb_bind(struct udevice *dev)
+{
+ struct udevice *blk, *bdev;
+ struct blk_desc *desc;
+ int ret;
+
+ ret = blk_create_devicef(dev, "sandbox_host_blk", "blk", UCLASS_HOST,
+ dev_seq(dev), 512, 0, &blk);
+ if (ret)
+ return log_msg_ret("blk", ret);
+
+ desc = dev_get_uclass_plat(blk);
+ snprintf(desc->vendor, BLK_VEN_SIZE, "U-Boot");
+ snprintf(desc->product, BLK_PRD_SIZE, "hostfile");
+ snprintf(desc->revision, BLK_REV_SIZE, "1.0");
+
+ if (CONFIG_IS_ENABLED(BOOTSTD)) {
+ ret = bootdev_bind(dev, "host_bootdev", "bootdev", &bdev);
+ if (ret)
+ return log_msg_ret("bd", ret);
+ }
+
+ return 0;
+}
+
+struct host_ops host_sb_ops = {
+ .attach_file = host_sb_attach_file,
+ .detach_file = host_sb_detach_file,
+};
+
+static const struct udevice_id host_ids[] = {
+ { .compatible = "sandbox,host" },
+ { }
+};
+
+U_BOOT_DRIVER(host_sb_drv) = {
+ .name = "host_sb_drv",
+ .id = UCLASS_HOST,
+ .of_match = host_ids,
+ .ops = &host_sb_ops,
+ .bind = host_sb_bind,
+ .plat_auto = sizeof(struct host_sb_plat),
+};
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index f2aae89..be4e02c 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -10,244 +10,52 @@
#include <part.h>
#include <os.h>
#include <malloc.h>
-#include <sandboxblockdev.h>
+#include <sandbox_host.h>
#include <asm/global_data.h>
#include <dm/device_compat.h>
-#include <linux/errno.h>
#include <dm/device-internal.h>
+#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_BLK
-static struct host_block_dev host_devices[SANDBOX_HOST_MAX_DEVICES];
-
-static struct host_block_dev *find_host_device(int dev)
-{
- if (dev >= 0 && dev < SANDBOX_HOST_MAX_DEVICES)
- return &host_devices[dev];
-
- return NULL;
-}
-#endif
-
-#ifdef CONFIG_BLK
static unsigned long host_block_read(struct udevice *dev,
unsigned long start, lbaint_t blkcnt,
void *buffer)
{
- struct host_block_dev *host_dev = dev_get_plat(dev);
- struct blk_desc *block_dev = dev_get_uclass_plat(dev);
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
+ struct udevice *host_dev = dev_get_parent(dev);
+ struct host_sb_plat *plat = dev_get_plat(host_dev);
-#else
-static unsigned long host_block_read(struct blk_desc *block_dev,
- unsigned long start, lbaint_t blkcnt,
- void *buffer)
-{
- int dev = block_dev->devnum;
- struct host_block_dev *host_dev = find_host_device(dev);
-
- if (!host_dev)
- return -1;
-#endif
-
- if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
- -1) {
+ if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
- ssize_t len = os_read(host_dev->fd, buffer, blkcnt * block_dev->blksz);
+ ssize_t len = os_read(plat->fd, buffer, blkcnt * desc->blksz);
if (len >= 0)
- return len / block_dev->blksz;
- return -1;
+ return len / desc->blksz;
+
+ return -EIO;
}
-#ifdef CONFIG_BLK
static unsigned long host_block_write(struct udevice *dev,
unsigned long start, lbaint_t blkcnt,
const void *buffer)
{
- struct host_block_dev *host_dev = dev_get_plat(dev);
- struct blk_desc *block_dev = dev_get_uclass_plat(dev);
-#else
-static unsigned long host_block_write(struct blk_desc *block_dev,
- unsigned long start, lbaint_t blkcnt,
- const void *buffer)
-{
- int dev = block_dev->devnum;
- struct host_block_dev *host_dev = find_host_device(dev);
-#endif
+ struct blk_desc *desc = dev_get_uclass_plat(dev);
+ struct udevice *host_dev = dev_get_parent(dev);
+ struct host_sb_plat *plat = dev_get_plat(host_dev);
- if (os_lseek(host_dev->fd, start * block_dev->blksz, OS_SEEK_SET) ==
- -1) {
+ if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
- ssize_t len = os_write(host_dev->fd, buffer, blkcnt * block_dev->blksz);
+ ssize_t len = os_write(plat->fd, buffer, blkcnt * desc->blksz);
if (len >= 0)
- return len / block_dev->blksz;
- return -1;
-}
-
-#ifdef CONFIG_BLK
-int host_dev_bind(int devnum, char *filename, bool removable)
-{
- struct host_block_dev *host_dev;
- struct udevice *dev;
- struct blk_desc *desc;
- char dev_name[20], *str, *fname;
- int ret, fd;
-
- /* Remove and unbind the old device, if any */
- ret = blk_get_device(UCLASS_ROOT, devnum, &dev);
- if (ret == 0) {
- ret = device_remove(dev, DM_REMOVE_NORMAL);
- if (ret)
- return ret;
- ret = device_unbind(dev);
- if (ret)
- return ret;
- } else if (ret != -ENODEV) {
- return ret;
- }
-
- if (!filename)
- return 0;
-
- snprintf(dev_name, sizeof(dev_name), "host%d", devnum);
- str = strdup(dev_name);
- if (!str)
- return -ENOMEM;
- fname = strdup(filename);
- if (!fname) {
- free(str);
- return -ENOMEM;
- }
-
- fd = os_open(filename, OS_O_RDWR);
- if (fd == -1) {
- printf("Failed to access host backing file '%s', trying read-only\n",
- filename);
- fd = os_open(filename, OS_O_RDONLY);
- if (fd == -1) {
- printf("- still failed\n");
- ret = -ENOENT;
- goto err;
- }
- }
- ret = blk_create_device(gd->dm_root, "sandbox_host_blk", str,
- UCLASS_ROOT, devnum, 512,
- os_lseek(fd, 0, OS_SEEK_END) / 512, &dev);
- if (ret)
- goto err_file;
-
- host_dev = dev_get_plat(dev);
- host_dev->fd = fd;
- host_dev->filename = fname;
+ return len / desc->blksz;
- ret = device_probe(dev);
- if (ret) {
- device_unbind(dev);
- goto err_file;
- }
-
- desc = blk_get_devnum_by_uclass_id(UCLASS_ROOT, devnum);
- desc->removable = removable;
- snprintf(desc->vendor, BLK_VEN_SIZE, "U-Boot");
- snprintf(desc->product, BLK_PRD_SIZE, "hostfile");
- snprintf(desc->revision, BLK_REV_SIZE, "1.0");
-
- return 0;
-err_file:
- os_close(fd);
-err:
- free(fname);
- free(str);
- return ret;
-}
-#else
-int host_dev_bind(int dev, char *filename, bool removable)
-{
- struct host_block_dev *host_dev = find_host_device(dev);
-
- if (!host_dev)
- return -1;
- if (host_dev->blk_dev.priv) {
- os_close(host_dev->fd);
- host_dev->blk_dev.priv = NULL;
- }
- if (host_dev->filename)
- free(host_dev->filename);
- if (filename && *filename) {
- host_dev->filename = strdup(filename);
- } else {
- host_dev->filename = NULL;
- return 0;
- }
-
- host_dev->fd = os_open(host_dev->filename, OS_O_RDWR);
- if (host_dev->fd == -1) {
- printf("Failed to access host backing file '%s'\n",
- host_dev->filename);
- return 1;
- }
-
- struct blk_desc *blk_dev = &host_dev->blk_dev;
- blk_dev->uclass_id = UCLASS_ROOT;
- blk_dev->priv = host_dev;
- blk_dev->blksz = 512;
- blk_dev->lba = os_lseek(host_dev->fd, 0, OS_SEEK_END) / blk_dev->blksz;
- blk_dev->block_read = host_block_read;
- blk_dev->block_write = host_block_write;
- blk_dev->devnum = dev;
- blk_dev->part_type = PART_TYPE_UNKNOWN;
- blk_dev->removable = removable;
- snprintf(blk_dev->vendor, BLK_VEN_SIZE, "U-Boot");
- snprintf(blk_dev->product, BLK_PRD_SIZE, "hostfile");
- snprintf(blk_dev->revision, BLK_REV_SIZE, "1.0");
- part_init(blk_dev);
-
- return 0;
-}
-#endif
-
-int host_get_dev_err(int devnum, struct blk_desc **blk_devp)
-{
-#ifdef CONFIG_BLK
- struct udevice *dev;
- int ret;
-
- ret = blk_get_device(UCLASS_ROOT, devnum, &dev);
- if (ret)
- return ret;
- *blk_devp = dev_get_uclass_plat(dev);
-#else
- struct host_block_dev *host_dev = find_host_device(devnum);
-
- if (!host_dev)
- return -ENODEV;
-
- if (!host_dev->blk_dev.priv)
- return -ENOENT;
-
- *blk_devp = &host_dev->blk_dev;
-#endif
-
- return 0;
+ return -EIO;
}
-#ifdef CONFIG_BLK
-
-int sandbox_host_unbind(struct udevice *dev)
-{
- struct host_block_dev *host_dev;
-
- /* Data validity is checked in host_dev_bind() */
- host_dev = dev_get_plat(dev);
- os_close(host_dev->fd);
-
- return 0;
-}
-
static const struct blk_ops sandbox_host_blk_ops = {
.read = host_block_read,
.write = host_block_write,
@@ -257,14 +65,4 @@
.name = "sandbox_host_blk",
.id = UCLASS_BLK,
.ops = &sandbox_host_blk_ops,
- .unbind = sandbox_host_unbind,
- .plat_auto = sizeof(struct host_block_dev),
-};
-#else
-U_BOOT_LEGACY_BLK(sandbox_host) = {
- .uclass_idname = "host",
- .uclass_id = UCLASS_ROOT,
- .max_devs = SANDBOX_HOST_MAX_DEVICES,
- .get_dev = host_get_dev_err,
};
-#endif
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index 542b165..d32c1fe 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -28,7 +28,7 @@
{
uint32_t temp_reg;
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid));
uint32_t jr_id = 0;
@@ -58,7 +58,7 @@
{
uint32_t temp_reg;
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid));
uint32_t jr_id = 0;
@@ -116,7 +116,7 @@
int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt,
uint8_t *dek_blob, uint32_t in_sz)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid));
uint32_t jr_id = 0;
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8c0fb27..ee822ed 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -33,8 +33,8 @@
uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
0,
#if defined(CONFIG_ARCH_C29X)
- CONFIG_SYS_FSL_SEC_IDX_OFFSET,
- 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
+ CFG_SYS_FSL_SEC_IDX_OFFSET,
+ 2 * CFG_SYS_FSL_SEC_IDX_OFFSET
#endif
};
@@ -42,11 +42,11 @@
struct udevice *caam_dev;
#else
#define SEC_ADDR(idx) \
- (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+ (ulong)((CFG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
- (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+ (CFG_SYS_FSL_JR0_OFFSET - CFG_SYS_FSL_SEC_OFFSET))
struct caam_regs caam_st;
#endif
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
index f0a4a63..9de30a6 100644
--- a/drivers/crypto/fsl/sec.c
+++ b/drivers/crypto/fsl/sec.c
@@ -128,7 +128,7 @@
{0x0A1C, 1, 5}
};
- ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
u32 secvid_ms = sec_in32(&sec->secvid_ms);
u32 ccbvid = sec_in32(&sec->ccbvid);
u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 629ba67..5e8fb7a 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -40,16 +40,16 @@
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 0b0b4e5..df7ec48 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2590,7 +2590,7 @@
void erratum_a009942_check_cpo(void)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
u32 cpo_max = cpo_min;
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 89cb4d3..3c1f7a1 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -86,16 +86,16 @@
#endif
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
index cbd625b..28f2219 100644
--- a/drivers/ddr/fsl/fsl_mmdc.c
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -28,7 +28,7 @@
void mmdc_init(const struct fsl_mmdc_info *priv)
{
- struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct mmdc_regs *mmdc = (struct mmdc_regs *)CFG_SYS_FSL_DDR_ADDR;
unsigned int tmp;
/* 1. set configuration request */
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index ed3313a..fcff223 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -21,18 +21,18 @@
#include <asm/bitops.h>
/*
- * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
+ * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
* of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
* all Power SoCs. But it could be different for ARM SoCs. For example,
* fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
* 0x00_8000_0000 ~ 0x00_ffff_ffff
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
-#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
#else
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
#endif
@@ -898,7 +898,7 @@
/* Reset info structure. */
memset(&info, 0, sizeof(fsl_ddr_info_t));
- info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+ info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
info.first_ctrl = 0;
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
@@ -946,7 +946,7 @@
unsigned long long total_memory = 0;
memset(&info, 0 , sizeof(fsl_ddr_info_t));
- info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+ info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
info.first_ctrl = 0;
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 9c2ddea..0f1e99e 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -18,7 +18,7 @@
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -71,7 +71,7 @@
ddr_enable_ecc(unsigned int dram_size)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index d7b8064..b830e7c 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -18,10 +18,10 @@
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
uint svr;
#endif
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 1ed4d50..0f2dc24 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -33,7 +33,7 @@
int timeout;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
int timeout_save;
- volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+ volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR;
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
@@ -52,16 +52,16 @@
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 589d7df..e49cf6e 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -34,16 +34,16 @@
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
@@ -181,7 +181,7 @@
void print_ddr_info(unsigned int start_ctrl)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
@@ -195,14 +195,14 @@
#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 1)) {
- ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 2)) {
- ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
@@ -353,16 +353,16 @@
for (i = first_ctrl; i <= last_ctrl; i++) {
switch (i) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index 1864b5d..cd78e45 100644
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -24,9 +24,9 @@
#if defined(CONFIG_MPC83xx)
-dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
+dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
#elif defined(CONFIG_MPC85xx)
-ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
#elif defined(CONFIG_MPC86xx)
ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
#else
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 9a3c824..edbcd83 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -271,13 +271,6 @@
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
unsigned long long timeval;
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* Call board specific i2c bus reset routine before accessing the
- * environment, which might be in a chip on that bus. For details
- * about this problem see doc/I2C_Edge_Conditions.
- */
- i2c_init_board();
-#endif
writeb(0, &base->cr); /* stop I2C controller */
udelay(5); /* let it shutdown in peace */
set_i2c_bus_speed(base, i2c_clk, speed);
diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c
index 1aedad5..4ed9e9e 100644
--- a/drivers/i2c/i2c-gpio.c
+++ b/drivers/i2c/i2c-gpio.c
@@ -362,7 +362,7 @@
return 0;
error:
- pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
+ pr_err("Can't get %s gpios! Error: %d\n", dev->name, ret);
return ret;
}
diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-microchip.c
index 12f65d0..d82b80f 100644
--- a/drivers/i2c/i2c-microchip.c
+++ b/drivers/i2c/i2c-microchip.c
@@ -2,8 +2,9 @@
/*
* Microchip I2C controller driver
*
- * Copyright (C) 2021 Microchip Technology Inc.
+ * Copyright (C) 2021-2022 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
+ * Conor Dooley <conor.dooley@microchip.com>
*/
#include <common.h>
#include <clk.h>
@@ -223,7 +224,7 @@
bus->msg_len--;
}
- if (bus->msg_len == 0) {
+ if (bus->msg_len <= 1) {
ctrl = readl(bus->base + MPFS_I2C_CTRL);
ctrl &= ~CTRL_AA;
writel(ctrl, bus->base + MPFS_I2C_CTRL);
@@ -265,10 +266,18 @@
}
break;
case STATUS_M_SLAR_ACK:
- ctrl = readl(bus->base + MPFS_I2C_CTRL);
- ctrl |= CTRL_AA;
- writel(ctrl, bus->base + MPFS_I2C_CTRL);
- if (bus->msg_len == 0) {
+ if (bus->msg_len > 1u) {
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl |= CTRL_AA;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+ } else if (bus->msg_len == 1u) {
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl &= ~CTRL_AA;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
+ } else {
+ ctrl = readl(bus->base + MPFS_I2C_CTRL);
+ ctrl |= CTRL_AA;
+ writel(ctrl, bus->base + MPFS_I2C_CTRL);
/* On the last byte to be transmitted, send STOP */
mpfs_i2c_stop(bus);
finish = true;
@@ -276,6 +285,9 @@
break;
case STATUS_M_RX_DATA_ACKED:
mpfs_i2c_empty_rx(bus);
+ break;
+ case STATUS_M_RX_DATA_NACKED:
+ mpfs_i2c_empty_rx(bus);
if (bus->msg_len == 0) {
/* On the last byte to be transmitted, send STOP */
mpfs_i2c_stop(bus);
@@ -283,7 +295,6 @@
}
break;
case STATUS_M_TX_DATA_NACK:
- case STATUS_M_RX_DATA_NACKED:
case STATUS_M_SLAR_NACK:
case STATUS_M_SLAW_NACK:
bus->msg_err = -ENXIO;
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index 0eff353..8ee17f0 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -374,27 +374,6 @@
static struct mv_i2c *base_glob;
-static void i2c_board_init(struct mv_i2c *base)
-{
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- u32 icr;
- /*
- * call board specific i2c bus reset routine before accessing the
- * environment, which might be in a chip on that bus. For details
- * about this problem see doc/I2C_Edge_Conditions.
- *
- * disable I2C controller first, otherwhise it thinks we want to
- * talk to the slave port...
- */
- icr = readl(&base->icr);
- writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
-
- i2c_init_board();
-
- writel(icr, &base->icr);
-#endif
-}
-
#ifdef CONFIG_I2C_MULTI_BUS
static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
@@ -411,7 +390,6 @@
current_bus = bus;
if (!bus_initialized[current_bus]) {
- i2c_board_init(base_glob);
bus_initialized[current_bus] = 1;
}
@@ -441,8 +419,6 @@
else
val = ICR_SM;
clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
-
- i2c_board_init(base_glob);
}
static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c
index cfe03b4..179053a 100644
--- a/drivers/misc/fsl_devdis.c
+++ b/drivers/misc/fsl_devdis.c
@@ -14,7 +14,7 @@
void device_disable(const struct devdis_table *tbl, uint32_t num)
{
int i;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
/*
* Extract hwconfig from environment and disable unused device.
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 59df57a..30a9409 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -28,7 +28,7 @@
CONFIG_SYS_BMAN_SWP_ISDR_REG;
void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
CONFIG_SYS_QMAN_SWP_ISDR_REG;
- struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
#ifdef CONFIG_PHYS_64BIT
@@ -159,7 +159,7 @@
if (!strncmp(name, "pme", 3)) {
u32 pme_rev1, pme_rev2;
ccsr_pme_t *pme_regs =
- (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
@@ -190,7 +190,7 @@
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
- struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+ struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
u32 rev_1 = in_be32(&qman->ip_rev_1);
u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
@@ -302,7 +302,7 @@
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
- struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+ struct ccsr_bman *bman = (void *)CFG_SYS_FSL_BMAN_ADDR;
u32 rev_1 = in_be32(&bman->ip_rev_1);
u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 56f4282..bf4d994 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -93,6 +93,13 @@
are enabled by default, other may require additional flags or are
enabled by the host driver.
+config SYS_MMC_MAX_BLK_COUNT
+ int "Block count limit"
+ default 65535
+ help
+ The block count limit on MMC based devices. We default to 65535 due
+ to a 16bit register limit on some hardware.
+
config MMC_HW_PARTITIONING
bool "Support for HW partitioning command(eMMC)"
default y
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index ca5a879..d506666 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -988,7 +988,7 @@
struct fsl_esdhc_cfg *cfg;
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR;
cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH;
/* Prefer peripheral clock which provides higher frequency. */
if (gd->arch.sdhc_per_clk)
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 92b152f..5ee3ce7 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1351,7 +1351,7 @@
struct fsl_esdhc_cfg *cfg;
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
- cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR;
cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index d6e3eeb..da2c579 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -26,6 +26,10 @@
config TPL_NAND_INIT
bool
+config SYS_MAX_NAND_DEVICE
+ int "Maximum number of NAND devices to support"
+ default 1
+
config SYS_NAND_DRIVER_ECC_LAYOUT
bool "Omit standard ECC layouts to save space"
help
@@ -132,6 +136,10 @@
Enable this driver for NAND flash controllers available in TI Davinci
and Keystone2 platforms
+config SYS_NAND_4BIT_HW_ECC_OOBFIRST
+ bool "Use 4-bit HW ECC with OOB at the front"
+ depends on NAND_DAVINCI
+
config KEYSTONE_RBL_NAND
depends on ARCH_KEYSTONE
def_bool y
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
index e622d86..1c5543e 100644
--- a/drivers/net/fm/b4860.c
+++ b/drivers/net/fm/b4860.c
@@ -25,7 +25,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -33,14 +33,14 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
@@ -51,7 +51,7 @@
u32 serdes2_prtcl;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
if (is_device_disabled(port))
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 1ffe9e2..c23e0c0 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -125,7 +125,7 @@
static void dtsec_init_phy(struct fm_eth *fm_eth)
{
#ifndef CONFIG_SYS_FMAN_V3
- struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
+ struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index ee96abb..9b6dbe2 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -403,7 +403,7 @@
} else {
ret = spi_flash_read(ucode_flash,
CONFIG_SYS_FMAN_FW_ADDR +
- CONFIG_SYS_FSL_QSPI_BASE,
+ CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_QE_FMAN_FW_LENGTH,
addr);
if (ret)
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 43d2000..34f3816 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -92,7 +92,7 @@
int i;
struct ccsr_fman *reg;
- reg = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ reg = (void *)CFG_SYS_FSL_FM1_ADDR;
if (fm_init_common(0, reg))
return 0;
@@ -102,7 +102,7 @@
}
#if (CONFIG_SYS_NUM_FMAN == 2)
- reg = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+ reg = (void *)CFG_SYS_FSL_FM2_ADDR;
if (fm_init_common(1, reg))
return 0;
@@ -247,7 +247,7 @@
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
- CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
+ CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
index cd8376a..3db5c90 100644
--- a/drivers/net/fm/ls1043.c
+++ b/drivers/net/fm/ls1043.c
@@ -35,7 +35,7 @@
static int is_device_disabled(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -43,14 +43,14 @@
void fman_disable_port(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c
index 876f48b..3b0ee98 100644
--- a/drivers/net/fm/ls1046.c
+++ b/drivers/net/fm/ls1046.c
@@ -35,7 +35,7 @@
static int is_device_disabled(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -43,14 +43,14 @@
void fman_disable_port(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
index c9b85fc..9013b27 100644
--- a/drivers/net/fm/p1023.c
+++ b/drivers/net/fm/p1023.c
@@ -16,7 +16,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
return port_to_devdisr[port] & devdisr;
@@ -24,7 +24,7 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
@@ -35,14 +35,14 @@
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
index 577ee22..7ad9932 100644
--- a/drivers/net/fm/p4080.c
+++ b/drivers/net/fm/p4080.c
@@ -24,7 +24,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -32,7 +32,7 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
@@ -43,14 +43,14 @@
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c
index 8ecc482..f931491 100644
--- a/drivers/net/fm/p5020.c
+++ b/drivers/net/fm/p5020.c
@@ -20,7 +20,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -28,7 +28,7 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
@@ -39,14 +39,14 @@
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c
index 3a1494d..ef9f4bc 100644
--- a/drivers/net/fm/p5040.c
+++ b/drivers/net/fm/p5040.c
@@ -26,7 +26,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -34,7 +34,7 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
@@ -45,14 +45,14 @@
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c
index 7110fb4..70ab461 100644
--- a/drivers/net/fm/t1024.c
+++ b/drivers/net/fm/t1024.c
@@ -20,7 +20,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -28,14 +28,14 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c
index 192f1c6..5c260be 100644
--- a/drivers/net/fm/t1040.c
+++ b/drivers/net/fm/t1040.c
@@ -11,7 +11,7 @@
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
/* handle RGMII first */
diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c
index bfbd8de..6174934 100644
--- a/drivers/net/fm/t2080.c
+++ b/drivers/net/fm/t2080.c
@@ -28,7 +28,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -36,14 +36,14 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index ba7b862..f0a02bf 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -35,7 +35,7 @@
static int is_device_disabled(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
@@ -43,21 +43,21 @@
void fman_disable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
void fman_enable_port(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
- ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c
index 943113b..32bcb51 100644
--- a/drivers/net/ldpaa_eth/ls1088a.c
+++ b/drivers/net/ldpaa_eth/ls1088a.c
@@ -25,7 +25,7 @@
static int is_device_disabled(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
@@ -33,14 +33,14 @@
void wriop_dpmac_disable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
@@ -90,7 +90,7 @@
#ifdef CONFIG_SYS_FSL_HAS_RGMII
void fsl_rgmii_init(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c
index 62e1d6b..845a36b 100644
--- a/drivers/net/ldpaa_eth/ls2080a.c
+++ b/drivers/net/ldpaa_eth/ls2080a.c
@@ -37,7 +37,7 @@
static int is_device_disabled(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
@@ -45,14 +45,14 @@
void wriop_dpmac_disable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c
index f0f8ee1..c2641a9 100644
--- a/drivers/net/ldpaa_eth/lx2160a.c
+++ b/drivers/net/ldpaa_eth/lx2160a.c
@@ -33,7 +33,7 @@
static int is_device_disabled(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2;
@@ -41,14 +41,14 @@
void wriop_dpmac_disable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
void wriop_dpmac_enable(int dpmac_id)
{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}
@@ -84,7 +84,7 @@
#ifdef CONFIG_SYS_FSL_HAS_RGMII
void fsl_rgmii_init(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 ec;
#ifdef CONFIG_SYS_FSL_EC1
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
index d338b36..ab532c5 100644
--- a/drivers/net/pfe_eth/pfe_eth.c
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -51,7 +51,7 @@
static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
index ae5b6fc..ff48726 100644
--- a/drivers/net/pfe_eth/pfe_mdio.c
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -213,7 +213,7 @@
struct phy_device *phydev = NULL;
struct udevice *dev = priv->dev;
struct gemac_s *gem = priv->gem;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
if (!gem->bus)
return -1;
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 59c38f9..a8f8c31 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -463,7 +463,7 @@
if (!fsl_pcie_link_up(pcie)) {
serdes_corenet_t *srds_regs;
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ srds_regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
val_32 = in_be32(&srds_regs->srdspccr0);
if ((val_32 >> 28) == 3) {
diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c
index a163300..7180b51 100644
--- a/drivers/power/power_fsl.c
+++ b/drivers/power/power_fsl.c
@@ -47,7 +47,7 @@
p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
#elif defined(CONFIG_POWER_I2C)
p->interface = PMIC_I2C;
- p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
+ p->hw.i2c.addr = CFG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C"
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 8342c33..fb1f683 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -238,7 +238,7 @@
if (src == BOOT_SOURCE_QSPI_NOR)
addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
- CONFIG_SYS_FSL_QSPI_BASE);
+ CFG_SYS_FSL_QSPI_BASE);
if (src == BOOT_SOURCE_SD_MMC) {
int dev = CONFIG_SYS_MMC_ENV_DEV;
@@ -467,9 +467,9 @@
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_ARCH_LS1021A
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#else
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
@@ -607,9 +607,9 @@
const struct qe_header *hdr;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_ARCH_LS1021A
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#else
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
#endif
if (!firmware) {
@@ -718,9 +718,9 @@
const u32 *code;
#ifdef CONFIG_DEEP_SLEEP
#ifdef CONFIG_PPC
- ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#else
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
#endif
#endif
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index c4bd5c4..3108879 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -562,7 +562,7 @@
struct uec_priv *uec = (struct uec_priv *)dev->priv;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII management signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
@@ -1194,7 +1194,7 @@
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (struct uec_priv *)dev->priv;
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index d621be6..009dd9d 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -27,11 +27,7 @@
obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o
obj-$(CONFIG_RTC_IMXDI) += imxdi.o
obj-$(CONFIG_RTC_ISL1208) += isl1208.o
-obj-$(CONFIG_RTC_M41T11) += m41t11.o
-obj-$(CONFIG_RTC_M41T60) += m41t60.o
obj-$(CONFIG_RTC_M41T62) += m41t62.o
-obj-$(CONFIG_RTC_M41T94) += m41t94.o
-obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o
obj-$(CONFIG_RTC_MAX6900) += max6900.o
obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
obj-$(CONFIG_RTC_MC146818) += mc146818.o
diff --git a/drivers/rtc/m41t11.c b/drivers/rtc/m41t11.c
deleted file mode 100644
index 706b718..0000000
--- a/drivers/rtc/m41t11.c
+++ /dev/null
@@ -1,168 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Andrew May, Viasat Inc, amay@viasat.com
- */
-
-/*
- * M41T11 Serial Access Timekeeper(R) SRAM
- * can you believe a trademark on that?
- */
-
-/* #define DEBUG 1 */
-
-#include <common.h>
-#include <command.h>
-#include <log.h>
-#include <rtc.h>
-#include <i2c.h>
-
-/*
- I Don't have an example config file but this
- is what should be done.
-
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#if 0
-#define CONFIG_SYS_M41T11_EXT_CENTURY_DATA
-#else
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-#endif
-*/
-
-/* ------------------------------------------------------------------------- */
-/*
- these are simple defines for the chip local to here so they aren't too
- verbose
- DAY/DATE aren't nice but that is how they are on the data sheet
-*/
-#define RTC_SEC_ADDR 0x0
-#define RTC_MIN_ADDR 0x1
-#define RTC_HOUR_ADDR 0x2
-#define RTC_DAY_ADDR 0x3
-#define RTC_DATE_ADDR 0x4
-#define RTC_MONTH_ADDR 0x5
-#define RTC_YEARS_ADDR 0x6
-
-#define RTC_REG_CNT 7
-
-#define RTC_CONTROL_ADDR 0x7
-
-
-#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA
-
-#define REG_CNT (RTC_REG_CNT+1)
-
-/*
- you only get 00-99 for the year we will asume you
- want from the year 2000 if you don't set the config
-*/
-#ifndef CONFIG_SYS_M41T11_BASE_YEAR
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-#endif
-
-#else
-/* we will store extra year info in byte 9*/
-#define M41T11_YEAR_DATA 0x8
-#define M41T11_YEAR_SIZE 1
-#define REG_CNT (RTC_REG_CNT+1+M41T11_YEAR_SIZE)
-#endif
-
-#define M41T11_STORAGE_SZ (64-REG_CNT)
-
-int rtc_get (struct rtc_time *tmp)
-{
- int rel = 0;
- uchar data[RTC_REG_CNT];
-
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT);
-
- if( data[RTC_SEC_ADDR] & 0x80 ){
- printf( "m41t11 RTC Clock stopped!!!\n" );
- rel = -1;
- }
- tmp->tm_sec = bcd2bin (data[RTC_SEC_ADDR] & 0x7F);
- tmp->tm_min = bcd2bin (data[RTC_MIN_ADDR] & 0x7F);
- tmp->tm_hour = bcd2bin (data[RTC_HOUR_ADDR] & 0x3F);
- tmp->tm_mday = bcd2bin (data[RTC_DATE_ADDR] & 0x3F);
- tmp->tm_mon = bcd2bin (data[RTC_MONTH_ADDR]& 0x1F);
-#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA
- tmp->tm_year = CONFIG_SYS_M41T11_BASE_YEAR
- + bcd2bin(data[RTC_YEARS_ADDR])
- + ((data[RTC_HOUR_ADDR]&0x40) ? 100 : 0);
-#else
- {
- unsigned char cent;
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE);
- if( !(data[RTC_HOUR_ADDR] & 0x80) ){
- printf( "m41t11 RTC: cann't keep track of years without CEB set\n" );
- rel = -1;
- }
- if( (cent & 0x1) != ((data[RTC_HOUR_ADDR]&0x40)>>7) ){
- /*century flip store off new year*/
- cent += 1;
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE);
- }
- tmp->tm_year =((int)cent*100)+bcd2bin(data[RTC_YEARS_ADDR]);
- }
-#endif
- tmp->tm_wday = bcd2bin (data[RTC_DAY_ADDR] & 0x07);
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
-
- debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- return rel;
-}
-
-int rtc_set (struct rtc_time *tmp)
-{
- uchar data[RTC_REG_CNT];
-
- debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- data[RTC_SEC_ADDR] = bin2bcd(tmp->tm_sec) & 0x7F;/*just in case*/
- data[RTC_MIN_ADDR] = bin2bcd(tmp->tm_min);
- data[RTC_HOUR_ADDR] = bin2bcd(tmp->tm_hour) & 0x3F;/*handle cent stuff later*/
- data[RTC_DATE_ADDR] = bin2bcd(tmp->tm_mday) & 0x3F;
- data[RTC_MONTH_ADDR] = bin2bcd(tmp->tm_mon);
- data[RTC_DAY_ADDR] = bin2bcd(tmp->tm_wday) & 0x07;
-
- data[RTC_HOUR_ADDR] |= 0x80;/*we will always use CEB*/
-
- data[RTC_YEARS_ADDR] = bin2bcd(tmp->tm_year%100);/*same thing either way*/
-#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA
- if( ((tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 200) ||
- (tmp->tm_year < CONFIG_SYS_M41T11_BASE_YEAR) ){
- printf( "m41t11 RTC setting year out of range!!need recompile\n" );
- }
- data[RTC_HOUR_ADDR] |= (tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 100 ? 0x40 : 0;
-#else
- {
- unsigned char cent;
- cent = tmp->tm_year ? tmp->tm_year / 100 : 0;
- data[RTC_HOUR_ADDR] |= (cent & 0x1) ? 0x40 : 0;
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE);
- }
-#endif
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT);
-
- return 0;
-}
-
-void rtc_reset (void)
-{
- unsigned char val;
- /* clear all control & status registers */
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1);
- val = val & 0x7F;/*make sure we are running*/
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT);
-
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
- val = val & 0x3F;/*turn off freq test keep calibration*/
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
-}
diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c
deleted file mode 100644
index b8ad33e..0000000
--- a/drivers/rtc/m41t60.c
+++ /dev/null
@@ -1,239 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Larry Johnson, lrj@acm.org
- *
- * based on rtc/m41t11.c which is ...
- *
- * (C) Copyright 2002
- * Andrew May, Viasat Inc, amay@viasat.com
- */
-
-/*
- * STMicroelectronics M41T60 serial access real-time clock
- */
-
-/* #define DEBUG 1 */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <log.h>
-#include <rtc.h>
-#include <i2c.h>
-
-/*
- * Convert between century and "century bits" (CB1 and CB0). These routines
- * assume years are in the range 1900 - 2299.
- */
-
-static unsigned char year2cb(unsigned const year)
-{
- if (year < 1900 || year >= 2300)
- printf("M41T60 RTC: year %d out of range\n", year);
-
- return (year / 100) & 0x3;
-}
-
-static unsigned cb2year(unsigned const cb)
-{
- return 1900 + 100 * ((cb + 1) & 0x3);
-}
-
-/*
- * These are simple defines for the chip local to here so they aren't too
- * verbose. DAY/DATE aren't nice but that is how they are on the data sheet.
- */
-#define RTC_SEC 0x0
-#define RTC_MIN 0x1
-#define RTC_HOUR 0x2
-#define RTC_DAY 0x3
-#define RTC_DATE 0x4
-#define RTC_MONTH 0x5
-#define RTC_YEAR 0x6
-
-#define RTC_REG_CNT 7
-
-#define RTC_CTRL 0x7
-
-#if defined(DEBUG)
-static void rtc_dump(char const *const label)
-{
- uchar data[8];
-
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
- printf("I2C read failed in rtc_dump()\n");
- return;
- }
- printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n",
- label, data[0], data[1], data[2], data[3],
- data[4], data[5], data[6], data[7]);
-}
-#else
-#define rtc_dump(label)
-#endif
-
-static uchar *rtc_validate(void)
-{
- /*
- * This routine uses the OUT bit and the validity of the time values to
- * determine whether there has been an initial power-up since the last
- * time the routine was run. It assumes that the OUT bit is not being
- * used for any other purpose.
- */
- static const uchar daysInMonth[0x13] = {
- 0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31,
- 0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x31, 0x30, 0x31
- };
- static uchar data[8];
- uchar min, date, month, years;
-
- rtc_dump("begin validate");
- if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
- printf("I2C read failed in rtc_validate()\n");
- return 0;
- }
- /*
- * If the OUT bit is "1", there has been a loss of power, so stop the
- * oscillator so it can be "kick-started" as per data sheet.
- */
- if (0x00 != (data[RTC_CTRL] & 0x80)) {
- printf("M41T60 RTC clock lost power.\n");
- data[RTC_SEC] = 0x80;
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) {
- printf("I2C write failed in rtc_validate()\n");
- return 0;
- }
- }
- /*
- * If the oscillator is stopped or the date is invalid, then reset the
- * OUT bit to "0", reset the date registers, and start the oscillator.
- */
- min = data[RTC_MIN] & 0x7F;
- date = data[RTC_DATE];
- month = data[RTC_MONTH] & 0x3F;
- years = data[RTC_YEAR];
- if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) ||
- 0x59 < min || 0x09 < (min & 0x0F) ||
- 0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) ||
- 0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] ||
- 0x12 < month ||
- 0x99 < years || 0x09 < (years & 0x0F) ||
- daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date ||
- (0x29 == date && 0x02 == month &&
- ((0x00 != (years & 0x03)) ||
- (0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) {
- printf("Resetting M41T60 RTC clock.\n");
- /*
- * Set to 00:00:00 1900-01-01 (Monday)
- */
- data[RTC_SEC] = 0x00;
- data[RTC_MIN] &= 0x80; /* preserve OFIE bit */
- data[RTC_HOUR] = 0x00;
- data[RTC_DAY] = 0x02;
- data[RTC_DATE] = 0x01;
- data[RTC_MONTH] = 0xC1;
- data[RTC_YEAR] = 0x00;
- data[RTC_CTRL] &= 0x7F; /* reset OUT bit */
-
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
- printf("I2C write failed in rtc_validate()\n");
- return 0;
- }
- }
- return data;
-}
-
-int rtc_get(struct rtc_time *tmp)
-{
- uchar const *const data = rtc_validate();
-
- if (!data)
- return -1;
-
- tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F);
- tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F);
- tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F);
- tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F);
- tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F);
- tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]);
- tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1;
- tmp->tm_yday = 0;
- tmp->tm_isdst = 0;
-
- debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- return 0;
-}
-
-int rtc_set(struct rtc_time *tmp)
-{
- uchar *const data = rtc_validate();
-
- if (!data)
- return -1;
-
- debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F);
- data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F);
- data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F;
- data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F;
- data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F;
- data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100);
- data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6;
- data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07;
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) {
- printf("I2C write failed in rtc_set()\n");
- return -1;
- }
-
- return 0;
-}
-
-void rtc_reset(void)
-{
- uchar *const data = rtc_validate();
- char const *const s = env_get("rtccal");
-
- if (!data)
- return;
-
- rtc_dump("begin reset");
- /*
- * If environmental variable "rtccal" is present, it must be a hex value
- * between 0x00 and 0x3F, inclusive. The five least-significan bits
- * represent the calibration magnitude, and the sixth bit the sign bit.
- * If these do not match the contents of the hardware register, that
- * register is updated. The value 0x00 imples no correction. Consult
- * the M41T60 documentation for further details.
- */
- if (s) {
- unsigned long const l = hextoul(s, 0);
-
- if (l <= 0x3F) {
- if ((data[RTC_CTRL] & 0x3F) != l) {
- printf("Setting RTC calibration to 0x%02lX\n",
- l);
- data[RTC_CTRL] &= 0xC0;
- data[RTC_CTRL] |= (uchar) l;
- }
- } else
- printf("environment parameter \"rtccal\" not valid: "
- "ignoring\n");
- }
- /*
- * Turn off frequency test.
- */
- data[RTC_CTRL] &= 0xBF;
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) {
- printf("I2C write failed in rtc_reset()\n");
- return;
- }
- rtc_dump("end reset");
-}
diff --git a/drivers/rtc/m41t94.c b/drivers/rtc/m41t94.c
deleted file mode 100644
index 5b665bb..0000000
--- a/drivers/rtc/m41t94.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Driver for ST M41T94 SPI RTC
- *
- * Taken from the Linux kernel drivier:
- * Copyright (C) 2008 Kim B. Heino
- *
- * Adaptation for U-Boot:
- * Copyright (C) 2009
- * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <rtc.h>
-#include <spi.h>
-
-static struct spi_slave *slave;
-
-#define M41T94_REG_SECONDS 0x01
-#define M41T94_REG_MINUTES 0x02
-#define M41T94_REG_HOURS 0x03
-#define M41T94_REG_WDAY 0x04
-#define M41T94_REG_DAY 0x05
-#define M41T94_REG_MONTH 0x06
-#define M41T94_REG_YEAR 0x07
-#define M41T94_REG_HT 0x0c
-
-#define M41T94_BIT_HALT 0x40
-#define M41T94_BIT_STOP 0x80
-#define M41T94_BIT_CB 0x40
-#define M41T94_BIT_CEB 0x80
-
-int rtc_set(struct rtc_time *tm)
-{
- u8 buf[8]; /* write cmd + 7 registers */
- int ret;
-
- if (!slave) {
- slave = spi_setup_slave(CONFIG_M41T94_SPI_BUS,
- CONFIG_M41T94_SPI_CS, 1000000,
- SPI_MODE_3);
- if (!slave)
- return -1;
- }
- spi_claim_bus(slave);
-
- buf[0] = 0x80 | M41T94_REG_SECONDS; /* write time + date */
- buf[M41T94_REG_SECONDS] = bin2bcd(tm->tm_sec);
- buf[M41T94_REG_MINUTES] = bin2bcd(tm->tm_min);
- buf[M41T94_REG_HOURS] = bin2bcd(tm->tm_hour);
- buf[M41T94_REG_WDAY] = bin2bcd(tm->tm_wday + 1);
- buf[M41T94_REG_DAY] = bin2bcd(tm->tm_mday);
- buf[M41T94_REG_MONTH] = bin2bcd(tm->tm_mon + 1);
-
- buf[M41T94_REG_HOURS] |= M41T94_BIT_CEB;
- if (tm->tm_year >= 100)
- buf[M41T94_REG_HOURS] |= M41T94_BIT_CB;
- buf[M41T94_REG_YEAR] = bin2bcd(tm->tm_year % 100);
-
- ret = spi_xfer(slave, 64, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
- spi_release_bus(slave);
- return ret;
-}
-
-int rtc_get(struct rtc_time *tm)
-{
- u8 buf[2];
- int ret, hour;
-
- if (!slave) {
- slave = spi_setup_slave(CONFIG_M41T94_SPI_BUS,
- CONFIG_M41T94_SPI_CS, 1000000,
- SPI_MODE_3);
- if (!slave)
- return -1;
- }
- spi_claim_bus(slave);
-
- /* clear halt update bit */
- ret = spi_w8r8(slave, M41T94_REG_HT);
- if (ret < 0)
- return ret;
- if (ret & M41T94_BIT_HALT) {
- buf[0] = 0x80 | M41T94_REG_HT;
- buf[1] = ret & ~M41T94_BIT_HALT;
- spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
- }
-
- /* clear stop bit */
- ret = spi_w8r8(slave, M41T94_REG_SECONDS);
- if (ret < 0)
- return ret;
- if (ret & M41T94_BIT_STOP) {
- buf[0] = 0x80 | M41T94_REG_SECONDS;
- buf[1] = ret & ~M41T94_BIT_STOP;
- spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
- }
-
- tm->tm_sec = bcd2bin(spi_w8r8(slave, M41T94_REG_SECONDS));
- tm->tm_min = bcd2bin(spi_w8r8(slave, M41T94_REG_MINUTES));
- hour = spi_w8r8(slave, M41T94_REG_HOURS);
- tm->tm_hour = bcd2bin(hour & 0x3f);
- tm->tm_wday = bcd2bin(spi_w8r8(slave, M41T94_REG_WDAY)) - 1;
- tm->tm_mday = bcd2bin(spi_w8r8(slave, M41T94_REG_DAY));
- tm->tm_mon = bcd2bin(spi_w8r8(slave, M41T94_REG_MONTH)) - 1;
- tm->tm_year = bcd2bin(spi_w8r8(slave, M41T94_REG_YEAR));
- if ((hour & M41T94_BIT_CB) || !(hour & M41T94_BIT_CEB))
- tm->tm_year += 100;
-
- spi_release_bus(slave);
- return 0;
-}
-
-void rtc_reset(void)
-{
- /*
- * Could not be tested as the reset pin is not wired on
- * the sbc35-ag20 board
- */
-}
diff --git a/drivers/rtc/m48t35ax.c b/drivers/rtc/m48t35ax.c
deleted file mode 100644
index 1cc24cc..0000000
--- a/drivers/rtc/m48t35ax.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- */
-
-/*
- * Date & Time support for ST Electronics M48T35Ax RTC
- */
-
-/*#define DEBUG */
-
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-#include <config.h>
-
-static uchar rtc_read (uchar reg);
-static void rtc_write (uchar reg, uchar val);
-
-/* ------------------------------------------------------------------------- */
-
-int rtc_get (struct rtc_time *tmp)
-{
- uchar sec, min, hour, cent_day, date, month, year;
- uchar ccr; /* Clock control register */
-
- /* Lock RTC for read using clock control register */
- ccr = rtc_read(0);
- ccr = ccr | 0x40;
- rtc_write(0, ccr);
-
- sec = rtc_read (0x1);
- min = rtc_read (0x2);
- hour = rtc_read (0x3);
- cent_day= rtc_read (0x4);
- date = rtc_read (0x5);
- month = rtc_read (0x6);
- year = rtc_read (0x7);
-
- /* UNLock RTC */
- ccr = rtc_read(0);
- ccr = ccr & 0xBF;
- rtc_write(0, ccr);
-
- debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
- "hr: %02x min: %02x sec: %02x\n",
- year, month, date, cent_day,
- hour, min, sec );
-
- tmp->tm_sec = bcd2bin (sec & 0x7F);
- tmp->tm_min = bcd2bin (min & 0x7F);
- tmp->tm_hour = bcd2bin (hour & 0x3F);
- tmp->tm_mday = bcd2bin (date & 0x3F);
- tmp->tm_mon = bcd2bin (month & 0x1F);
- tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
- tmp->tm_wday = bcd2bin (cent_day & 0x07);
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
-
- debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- return 0;
-}
-
-int rtc_set (struct rtc_time *tmp)
-{
- uchar ccr; /* Clock control register */
- uchar century;
-
- debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-
- /* Lock RTC for write using clock control register */
- ccr = rtc_read(0);
- ccr = ccr | 0x80;
- rtc_write(0, ccr);
-
- rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
- rtc_write (0x06, bin2bcd(tmp->tm_mon));
- rtc_write (0x05, bin2bcd(tmp->tm_mday));
-
- century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20;
- rtc_write (0x04, bin2bcd(tmp->tm_wday) | century);
-
- rtc_write (0x03, bin2bcd(tmp->tm_hour));
- rtc_write (0x02, bin2bcd(tmp->tm_min ));
- rtc_write (0x01, bin2bcd(tmp->tm_sec ));
-
- /* UNLock RTC */
- ccr = rtc_read(0);
- ccr = ccr & 0x7F;
- rtc_write(0, ccr);
-
- return 0;
-}
-
-void rtc_reset (void)
-{
- uchar val;
-
- /* Clear all clock control registers */
- rtc_write (0x0, 0x80); /* No Read Lock or calibration */
-
- /* Clear stop bit */
- val = rtc_read (0x1);
- val &= 0x7f;
- rtc_write(0x1, val);
-
- /* Enable century / disable frequency test */
- val = rtc_read (0x4);
- val = (val & 0xBF) | 0x20;
- rtc_write(0x4, val);
-
- /* Clear write lock */
- rtc_write(0x0, 0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-static uchar rtc_read (uchar reg)
-{
- return *(unsigned char *)
- ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
-}
-
-static void rtc_write (uchar reg, uchar val)
-{
- *(unsigned char *)
- ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
-}
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 71f96e2..122691b 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -22,7 +22,7 @@
/* Set this to 1 to clear the CMOS RAM */
#define CLEAR_CMOS 0
-#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
+#define RTC_PORT_MC146818 0x70
#define RTC_SECONDS 0x00
#define RTC_SECONDS_ALARM 0x01
#define RTC_MINUTES 0x02
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index c7a6926..b1d964d 100644
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -390,7 +390,7 @@
if (!fsl)
return NULL;
- fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR);
fsl->mode = mode;
fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
fsl->speed_hz = max_hz;
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c
index b45ef52..a7c0fc5 100644
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -22,6 +22,7 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/iopoll.h>
+#include <linux/sizes.h>
#define SPI_CFG0_REG 0x0000
#define SPI_CFG1_REG 0x0004
diff --git a/fs/jffs2/Kconfig b/fs/jffs2/Kconfig
index 0e79c34..3bf01cd 100644
--- a/fs/jffs2/Kconfig
+++ b/fs/jffs2/Kconfig
@@ -17,3 +17,15 @@
depends on FS_JFFS2
help
Enable support for NAND flash as the backing store for JFFS2.
+
+config SYS_JFFS2_SORT_FRAGMENTS
+ bool "Enable JFFS2 sorting of filesystem fragments (SLOW!)"
+ depends on FS_JFFS2
+ help
+ If you boot from a partition which is mounted writable, and you
+ update your boot environment by replacing single files on that
+ partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS.
+ Scanning the JFFS2 filesystem takes *much* longer with this feature,
+ though. Sorting is done while inserting into the fragment list,
+ which is more or less a bubble sort. That algorithm is known to be
+ O(n^2), thus you should really consider if you can avoid it!
diff --git a/include/blk.h b/include/blk.h
index e854166..1db203c 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -147,8 +147,8 @@
* blkcache_invalidate() - discard the cache for a set of blocks
* because of a write or device (re)initialization.
*
- * @param iftype - uclass_id_x for type of device
- * @param dev - device index of particular type
+ * @iftype - UCLASS_ID_ for type of device, or -1 for any
+ * @dev - device index of particular type, if @iftype is not -1
*/
void blkcache_invalidate(int iftype, int dev);
@@ -178,6 +178,9 @@
*/
void blkcache_stats(struct block_cache_stats *stats);
+/** blkcache_free() - free all memory allocated to the block cache */
+void blkcache_free(void);
+
#else
static inline int blkcache_read(int iftype, int dev,
@@ -193,6 +196,8 @@
static inline void blkcache_invalidate(int iftype, int dev) {}
+static inline void blkcache_free(void) {}
+
#endif
#if CONFIG_IS_ENABLED(BLK)
@@ -449,9 +454,35 @@
int blk_select_hwpart(struct udevice *dev, int hwpart);
/**
+ * blk_find_from_parent() - find a block device by looking up its parent
+ *
+ * All block devices have a parent 'media' device which provides the block
+ * driver for the block device, ensuring that access to the underlying medium
+ * is available.
+ *
+ * The block device is not activated by this function. See
+ * blk_get_from_parent() for that.
+ *
+ * @parent: Media device
+ * @devp: Returns the associated block device, if any
+ * Returns: 0 if OK, -ENODEV if @parent is not a media device and has no
+ * UCLASS_BLK child
+ */
+int blk_find_from_parent(struct udevice *parent, struct udevice **devp);
+
+/**
* blk_get_from_parent() - obtain a block device by looking up its parent
*
- * All devices with
+ * All block devices have a parent 'media' device which provides the block
+ * driver for the block device, ensuring that access to the underlying medium
+ * is available.
+ *
+ * The block device is probed and ready for use.
+ *
+ * @parent: Media device
+ * @devp: Returns the associated block device, if any
+ * Returns: 0 if OK, -ENODEV if @parent is not a media device and has no
+ * UCLASS_BLK child
*/
int blk_get_from_parent(struct udevice *parent, struct udevice **devp);
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
index 35560ab..afd7cc8 100644
--- a/include/configs/10m50_devboard.h
+++ b/include/configs/10m50_devboard.h
@@ -34,6 +34,5 @@
#define CONFIG_SYS_SDRAM_BASE 0xc8000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#endif /* __CONFIG_H */
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
index 69fa1c1..ad7bd13 100644
--- a/include/configs/3c120_devboard.h
+++ b/include/configs/3c120_devboard.h
@@ -29,6 +29,5 @@
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#endif /* __CONFIG_H */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 6c6469b..25c3f22 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -70,8 +70,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 5411641..f200d70 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -75,8 +75,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 42c62b4..9ff66d7 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -62,8 +62,6 @@
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 75278f4..f7bfe59 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -82,8 +82,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 356ad3e..dcd8365 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -77,8 +77,6 @@
#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 35ff267..9012794 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -79,8 +79,6 @@
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 900b0b5..e191dc6 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -80,8 +80,6 @@
#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 4f82389..79a4e61 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -84,8 +84,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index a6c953f..47ea51c 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -78,8 +78,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
@@ -95,7 +93,6 @@
#endif
#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index f519bef..a2e36cc 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -80,8 +80,6 @@
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
@@ -96,7 +94,6 @@
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
index 1826a6f..b080933 100644
--- a/include/configs/MCR3000.h
+++ b/include/configs/MCR3000.h
@@ -56,8 +56,6 @@
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
/* Miscellaneous configurable options */
/* Definitions for initial stack pointer and data area (in DPRAM) */
@@ -76,7 +74,6 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-#define CONFIG_SYS_MONITOR_LEN (320 << 10)
/* Environment Configuration */
@@ -85,7 +82,6 @@
/* Ethernet configuration part */
/* NAND configuration part */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index edf9b34..bb93c28 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -126,12 +126,9 @@
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
@@ -217,16 +214,9 @@
#endif
#endif
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 0951931..b241939 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -229,14 +229,11 @@
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -331,13 +328,6 @@
#endif /* CONFIG_TSEC_ENET */
/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 8492a64..addb306 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -202,7 +202,6 @@
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
@@ -297,14 +296,11 @@
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
/*
* Config the L2 Cache as L2 SRAM
*/
@@ -312,18 +308,15 @@
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#endif
@@ -399,7 +392,7 @@
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
@@ -411,9 +404,6 @@
#endif
#endif
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
|| defined(CONFIG_FSL_SATA)
#endif
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 0ac7f16..08c1bcc 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -59,8 +59,6 @@
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
@@ -121,7 +119,6 @@
#endif
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
@@ -145,7 +142,6 @@
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
@@ -163,8 +159,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
@@ -313,14 +307,8 @@
#define CONFIG_SYS_TBIPA_VALUE 8
#endif
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
index e42e6d5..9629d73 100644
--- a/include/configs/SBx81LIFKW.h
+++ b/include/configs/SBx81LIFKW.h
@@ -34,8 +34,6 @@
* U-Boot bootcode configuration
*/
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
-
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
index 8926c26..67e42b9 100644
--- a/include/configs/SBx81LIFXCAT.h
+++ b/include/configs/SBx81LIFXCAT.h
@@ -34,8 +34,6 @@
* U-Boot bootcode configuration
*/
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 14f0ce6..62c4177 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -104,7 +104,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (256 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT
@@ -237,7 +236,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -279,7 +277,6 @@
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
@@ -297,8 +294,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@ -370,7 +365,7 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
@@ -427,12 +422,6 @@
/*
* Dynamic MTD Partition support with mtdparts
*/
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* Miscellaneous configurable options
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index fad9594..ad8037e 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -78,7 +78,6 @@
* (CONFIG_SYS_INIT_L3_VADDR) will be different.
*/
#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
@@ -213,7 +212,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -255,7 +253,6 @@
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -267,8 +264,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
@@ -351,7 +346,7 @@
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/* Qman/Bman */
@@ -418,12 +413,6 @@
#endif
/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 285e5fc..2dcaeda 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -76,7 +76,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
@@ -201,7 +200,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -259,7 +257,6 @@
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -269,7 +266,6 @@
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/*
* Serial Port
@@ -406,7 +402,6 @@
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_SYS_INTERLAKEN
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -427,7 +422,7 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
@@ -435,12 +430,6 @@
*/
/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 7fe499b..223c8567 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -71,7 +71,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
@@ -177,7 +176,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -219,7 +217,6 @@
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -229,7 +226,6 @@
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/*
* Serial Port
@@ -360,7 +356,6 @@
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN /* RMan */
-#define CONFIG_SYS_INTERLAKEN
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -384,7 +379,7 @@
* SDHC
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 0dde24e..12edfdd 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -52,7 +52,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
@@ -75,7 +74,6 @@
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -87,8 +85,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
@@ -136,12 +132,6 @@
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
* Miscellaneous configurable options
*/
@@ -243,7 +233,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
@@ -367,7 +356,6 @@
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -394,7 +382,7 @@
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index bd7e2f1..8eefaf2 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -193,24 +193,6 @@
#endif
/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x020000 : SPL (128KiB)
- * 0x020000 - 0x0A0000 : U-Boot (512KiB)
- * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
- * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
- * 0x0E0000 - 0x442000 : Linux Kernel
- * 0x442000 - 0x800000 : Userland
- */
-#if defined(CONFIG_SPI_BOOT)
-/* SPL related */
-#elif defined(CONFIG_EMMC_BOOT)
-#define CONFIG_SYS_MMC_MAX_DEVICE 2
-#endif
-
-/* Network. */
-/* Enable Atheros phy driver */
-
-/*
* NOR Size = 16 MiB
* Number of Sectors/Blocks = 128
* Sector Size = 128 KiB
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 9cfae04..e0f5f2b 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -89,7 +89,6 @@
/* **** PISMO SUPPORT *** */
/* on one chip */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index 3f3b399..2bda66f 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -40,7 +40,6 @@
/* amcore design has flash data bytes wired swapped */
#define CONFIG_SYS_WRITE_SWAPPED_DATA
/* reserve 128-4KB */
-#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index c9f876f..e2e491b 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
@@ -61,7 +61,7 @@
/* Link Definitions */
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 8f33894..192c9cf 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -22,8 +22,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 3
/* Network */
#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 8997c6a..1f2b3b5 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -26,7 +26,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -412,7 +412,7 @@
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index adfadd7..58635df 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -46,9 +46,6 @@
*/
#ifdef CONFIG_RAM
#define CONFIG_MONITOR_IS_IN_RAM
-#define ENABLE_JFFS 0
-#else
-#define ENABLE_JFFS 1
#endif
/* I2C */
@@ -192,7 +189,6 @@
#define CONFIG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
@@ -210,14 +206,6 @@
. = DEFINED(env_offset) ? env_offset : .; \
env/embedded.o(.text*)
-#if ENABLE_JFFS
-/* JFFS Partition offset set */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-/* 512k reserved for u-boot */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40
-#endif
-
/* Cache Configuration */
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index ca5815f..d51da9d 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -43,7 +43,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 5576a5f..5dc8f21 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -24,7 +24,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 02d04d0..d31a774 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -34,9 +34,6 @@
#define PHYS_FLASH_1 0x10000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_SEC 1:0-3
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-
/* Address and size of Primary Environment Sector */
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -153,7 +150,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 2d257c4..0108547 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -20,7 +20,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
@@ -32,8 +31,6 @@
#endif
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index f2ca4f3..00f5774 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -21,7 +21,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
@@ -36,8 +35,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20953f03
#define CONFIG_SYS_MCKR 0x1301
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index bc687fc..c60c248 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 0e76658..71a2863 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -27,7 +27,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
@@ -40,8 +39,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
#define CONFIG_SYS_MCKR 0x1301
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
index 0198051..b347125 100644
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h
index f473963..b15c411 100644
--- a/include/configs/bcm963158.h
+++ b/include/configs/bcm963158.h
@@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
#endif
diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h
index ba2d8a3..6e420f2 100644
--- a/include/configs/bcm96855.h
+++ b/include/configs/bcm96855.h
@@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
#endif
diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h
index 3050cf3..a7ae71e 100644
--- a/include/configs/bcm96856.h
+++ b/include/configs/bcm96856.h
@@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
#endif
diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h
index 8bd1169..4e584b4 100644
--- a/include/configs/bcm96858.h
+++ b/include/configs/bcm96858.h
@@ -8,8 +8,4 @@
#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
#endif
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index b3e1fdd..ca2bc19 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -51,7 +51,6 @@
#include <linux/sizes.h>
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define IMX_FEC1_BASE ENET1_BASE_ADDR
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index 959c521..0b1fc91 100644
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -21,8 +21,6 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
/* FLASH */
#if !defined(CONFIG_MTD_NOR_FLASH)
#define CONFIG_SH_QSPI_BASE 0xE6B10000
diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h
index c1c1b37..bad1439 100644
--- a/include/configs/broadcom_bcm968380gerg.h
+++ b/include/configs/broadcom_bcm968380gerg.h
@@ -6,6 +6,3 @@
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6838.h>
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index 6b1e82a..c4110f8 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -14,9 +14,6 @@
/* SPL config */
#ifdef CONFIG_SPL_BUILD
-
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
#define CONFIG_MALLOC_F_ADDR 0x00120000
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h
index 6ac8487..c395384 100644
--- a/include/configs/cgtqmx8.h
+++ b/include/configs/cgtqmx8.h
@@ -12,8 +12,6 @@
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CONFIG_MALLOC_F_ADDR 0x00120000
@@ -22,7 +20,7 @@
/* Flat Device Tree Definitions */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
@@ -111,7 +109,7 @@
/* Link Definitions */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h
index 6c7f9ea..726c43d 100644
--- a/include/configs/cherryhill.h
+++ b/include/configs/cherryhill.h
@@ -8,8 +8,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (2 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index d094fb5..63dac1d 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h
@@ -10,7 +10,6 @@
#define __CONFIG_CI20_H__
/* Memory configuration */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 1043eb7..cbf8534 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -92,9 +92,9 @@
/* MMC Config*/
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
/* USB Configs */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index cbba726..874c0eb 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -15,8 +15,8 @@
/* Machine config */
/* MMC */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
@@ -129,7 +129,6 @@
/* NAND */
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* APBH DMA is required for NAND support */
/* Ethernet */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 50cb2a4..f0fbbe2 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -46,7 +46,6 @@
#define CONFIG_HSMMC2_8BIT
#include <configs/ti_armv7_omap.h>
-#undef CONFIG_SYS_MONITOR_LEN
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -74,7 +73,6 @@
"bootz ${loadaddr} - ${fdtaddr}\0"
/* SPL defines. */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* EEPROM */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 898ca96..52000b5 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -170,8 +170,6 @@
#define CONFIG_SYS_FLASH_BASE 0xffe00000
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 321edab..d7e181b 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -18,8 +18,8 @@
/* ENET1 */
/* MMC Config */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 1
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
@@ -122,7 +122,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
#define CONFIG_SYS_NAND_BASE -1
#endif
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index 5d6449c..d641fbf 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -10,7 +10,7 @@
#include <linux/sizes.h>
#include <linux/stringify.h>
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
@@ -94,7 +94,7 @@
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index d8b8736..14fdf5b 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -22,8 +22,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
/* Host */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index b8d0dc9..7380440 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -14,11 +14,11 @@
#include "mx7_common.h"
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_IPADDR 192.168.10.2
@@ -166,7 +166,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#endif
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 73d1844..b758086 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -16,7 +16,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define UBOOT_UPDATE \
"update_uboot=nand erase.part u-boot && " \
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 268afbb..0f6f99d 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -15,7 +15,6 @@
#include <linux/sizes.h>
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h
index a46b394..e8b0724 100644
--- a/include/configs/comtrend_vr3032u.h
+++ b/include/configs/comtrend_vr3032u.h
@@ -6,6 +6,3 @@
#include <configs/bmips_common.h>
#include <configs/bmips_bcm63268.h>
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index 6e819ad..823d37f 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 23c493b..f730043 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -15,8 +15,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
deleted file mode 100644
index 434da31..0000000
--- a/include/configs/corenet_ds.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
- */
-
-/*
- * Corenet DS style board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#include "../board/freescale/common/ics307_clk.h"
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#endif
-
-/* High Level Configuration Options */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
-#else
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
-#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of platform clock */
-#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
-
-#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
-#ifdef CONFIG_PHYS_64BIT
-#define PIXIS_BASE_PHYS 0xfffdf0000ull
-#else
-#define PIXIS_BASE_PHYS PIXIS_BASE
-#endif
-
-#define PIXIS_LBMAP_SWITCH 7
-#define PIXIS_LBMAP_MASK 0xf0
-#define PIXIS_LBMAP_SHIFT 4
-#define PIXIS_LBMAP_ALTBANK 0x40
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-/* Nand Flash */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-#else
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#endif
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_PGS /* Large Page*/ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#endif /* CONFIG_NAND_FSL_ELBC */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
-#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
-
-/*
- * for slave u-boot IMAGE instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
-/*
- * for slave UCODE and ENV instored in master memory space,
- * PHYS must be aligned based on the SIZE
- */
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
-
-/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
-
-/*
- * SRIO_PCIE_BOOT - SLAVE
- */
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
-#endif
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#else
-#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#else
-#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
-#endif
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
-#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
-
-#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
-#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
-#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
-#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
-#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
-
-#define CONFIG_SYS_TBIPA_VALUE 8
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#ifdef CONFIG_TARGET_P4080DS
-#define __USB_PHY_TYPE ulpi
-#else
-#define __USB_PHY_TYPE utmi
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
- "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=p4080ds/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=p4080ds/p4080ds.dtb\0" \
- "bdev=sda3\0"
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 5e43c21..0596afb 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -37,7 +37,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
index 3537561..efd0b77 100644
--- a/include/configs/cougarcanyon2.h
+++ b/include/configs/cougarcanyon2.h
@@ -8,8 +8,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (2 << 20)
-
#define CONFIG_SMSC_SIO1007
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 4c11808..e8a8af7 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_SMSC_LPC47M
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 58c9024..281cbe3 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -107,14 +107,12 @@
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index 36052fe..6079596 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -15,9 +15,9 @@
/* NAND pin conflicts with usdhc2 */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#else
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#ifdef CONFIG_CMD_NET
@@ -35,7 +35,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C configs */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 66fb25b..4236612 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -36,7 +36,6 @@
* NAND controller
*/
#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
/*
@@ -86,7 +85,6 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
/* See common/spl/spl.c spl_set_header_raw_uboot() */
-#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
/*
* Include SoC specific configuration
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index 53ed7de..4297047 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#ifndef CONFIG_INTERNAL_UART
/* Use BayTrail internal HS UART which is memory-mapped */
#undef CONFIG_SYS_NS16550_PORT_MAPPED
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 2040deb..54b2192 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -27,8 +27,8 @@
/* Miscellaneous configurable options */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 3
/* UART */
#define CONFIG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/display5.h b/include/configs/display5.h
index c23a57e..eb65f17 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -42,8 +42,8 @@
#define CONFIG_I2C_MULTI_BUS
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
#define PARTS_DEFAULT \
/* Linux partitions */ \
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 79cacd7..aaa2ef0 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -74,8 +74,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
-#define CONFIG_SYS_MONITOR_LEN 0x20000
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
diff --git a/include/configs/edison.h b/include/configs/edison.h
index 34536ec..b05141a 100644
--- a/include/configs/edison.h
+++ b/include/configs/edison.h
@@ -12,9 +12,4 @@
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-
-/* RTC */
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-
#endif
diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h
index 59fad4c..f50c2ce 100644
--- a/include/configs/efi-x86_payload.h
+++ b/include/configs/efi-x86_payload.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index 7fc3459..affe20a 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -17,8 +17,8 @@
#endif
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* PMIC */
#define CONFIG_POWER_PFUZE100
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 7526d3b..555239b 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -22,7 +22,7 @@
#define CONFIG_MXC_USB_FLAGS 0
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -36,11 +36,11 @@
#if defined(CONFIG_ENV_IS_IN_MMC)
/* RiOTboard */
#define CONFIG_FDTFILE "imx6dl-riotboard.dtb"
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
/* MarSBoard */
#define CONFIG_FDTFILE "imx6q-marsboard.dtb"
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
/* Framebuffer */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
index 7923fbb..75322a3 100644
--- a/include/configs/etamin.h
+++ b/include/configs/etamin.h
@@ -45,8 +45,6 @@
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
-#undef CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_MAX_NAND_DEVICE 3
#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 7a3c800..22647ab 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -37,7 +37,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 054cb53..81f450c 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -21,8 +21,6 @@
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
/* Common environment variables */
#define ENV_ITB \
"loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 49f57dd..545408a 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
/* ns16550 UART is memory-mapped in Quark SoC */
#undef CONFIG_SYS_NS16550_PORT_MAPPED
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 635d0f0..52b9fe2 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -22,7 +22,6 @@
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
@@ -34,8 +33,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
#define CONFIG_SYS_MCKR 0x1301
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
index e592dc4..fa6f0e6 100644
--- a/include/configs/gazerbeam.h
+++ b/include/configs/gazerbeam.h
@@ -25,12 +25,9 @@
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
@@ -44,13 +41,6 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index ab8c66f..d519384 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -100,7 +100,7 @@
/* environment organization */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */
#define CONFIG_IMX_HDMI
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index fb69716..d2138c2 100644
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -16,8 +16,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
/* Network interface */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index bba64af..a9ef35e 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -20,10 +20,9 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/*
* PCI express
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 879bd5c..fe4b02c 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -24,7 +24,6 @@
#endif
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND (which is 512M), aligned to start of last sector */
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
index bdc9c47..973df8e 100644
--- a/include/configs/hikey960.h
+++ b/include/configs/hikey960.h
@@ -39,6 +39,5 @@
BOOTENV
/* TODO: Remove this once the SD clock is fixed */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1024
#endif /* __HIKEY_H */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 6ebdc3d..232f786 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -81,7 +81,6 @@
#define PHYS_FLASH_1 0xc0000000
/* Flash Base for U-Boot */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
/* Address and size of Redundant Environment Sector */
/*
@@ -97,7 +96,6 @@
* NAND
*/
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0xd8000000
#define CONFIG_MXC_NAND_HWECC
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index fa73cab..f52367c 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -126,7 +126,6 @@
/* NAND */
#ifdef CONFIG_NAND_MXS
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE 0x40000000
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 9ab3f8a..008fc07 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -18,8 +18,8 @@
#include "mx6_common.h"
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* Ethernet Configs */
@@ -116,7 +116,6 @@
/* Environment organization */
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 488b2f1..3afe418 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -9,9 +9,6 @@
#ifdef CONFIG_SPL
/* MMC support */
-#if defined(CONFIG_SPL_MMC)
-#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */
-#endif
/* SATA support */
#if defined(CONFIG_SPL_SATA)
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 201684b..5025ad9 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h
@@ -94,17 +94,17 @@
#include "imx6_spl.h"
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#ifdef CONFIG_SYS_BOOT_EMMC
/* Boot from eMMC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 1
+#define CFG_SYS_FSL_ESDHC_ADDR 1
#else
/* Boot from SD-card */
-# define CONFIG_SYS_FSL_ESDHC_ADDR 0
+# define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h
index 50885c5..46a96f1 100644
--- a/include/configs/imx6ulz_smm_m2.h
+++ b/include/configs/imx6ulz_smm_m2.h
@@ -71,7 +71,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index f0f800b..caa6a11 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -74,8 +74,8 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h
index 5900c05..362b980 100644
--- a/include/configs/imx7_spl.h
+++ b/include/configs/imx7_spl.h
@@ -13,9 +13,6 @@
#ifdef CONFIG_SPL
/* MMC support */
-#if defined(CONFIG_SPL_MMC)
-#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */
-#endif
#endif /* CONFIG_SPL */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index c69f2fa..917d567 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -11,7 +11,6 @@
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
@@ -134,8 +133,8 @@
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index 79ed397..8e08899 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -9,7 +9,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index a5b7e9f..dd9f93f 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -10,8 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_1M
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_MALLOC_F_ADDR 0x930000
@@ -33,8 +31,8 @@
#define PHY_ANEG_TIMEOUT 20000
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index dac642e..f1d1c1c 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -10,7 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define UBOOT_ITB_OFFSET 0x57C00
#define FSPI_CONF_BLOCK_SIZE 0x1000
#define UBOOT_ITB_OFFSET_FSPI \
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
index 6b7f3af..9cdba70 100644
--- a/include/configs/imx8mm_icore_mx8mm.h
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -10,7 +10,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
@@ -49,7 +48,7 @@
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MM_ICORE_MX8MM_H */
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index f754126..0653563 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -9,7 +9,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 930b11b..0ae3da1 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -9,7 +9,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h
index c6b2962..a2323bd 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -43,7 +43,6 @@
#define PHYS_SDRAM_SIZE SZ_256M
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h
index a371c5b..d6959ac 100644
--- a/include/configs/imx8mn_bsh_smm_s2_common.h
+++ b/include/configs/imx8mn_bsh_smm_s2_common.h
@@ -10,7 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_bsh_smm_s2pro.h b/include/configs/imx8mn_bsh_smm_s2pro.h
index 37fda66..035e5c7 100644
--- a/include/configs/imx8mn_bsh_smm_s2pro.h
+++ b/include/configs/imx8mn_bsh_smm_s2pro.h
@@ -30,6 +30,6 @@
#define PHYS_SDRAM_SIZE SZ_512M
/* USDHC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_BSH_SMM_S2PRO_H */
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index ae7fcb1..9c75e3e 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -10,7 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h
index c8604e0..a484d91 100644
--- a/include/configs/imx8mn_var_som.h
+++ b/include/configs/imx8mn_var_som.h
@@ -10,7 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
@@ -52,6 +51,6 @@
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
/* USDHC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_VAR_SOM_H */
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index 022db00..d5252ab 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -9,7 +9,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index 4b4731c..bf87825 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -10,8 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_1M
-
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
@@ -27,8 +25,8 @@
#define FEC_QUIRK_ENET_MAC
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"altbootcmd=run bootcmd ; reset\0" \
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 140eba3..1b533e2 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -10,7 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h
index 28d4416..7986d20 100644
--- a/include/configs/imx8mp_icore_mx8mp.h
+++ b/include/configs/imx8mp_icore_mx8mp.h
@@ -11,7 +11,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index ddc035a..5be4609 100644
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -12,7 +12,6 @@
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* GUIDs for capsule updatable firmware images */
@@ -42,10 +41,6 @@
#if defined(CONFIG_CMD_NET)
#define CONFIG_FEC_MXC_PHYADDR 4
-#ifdef CONFIG_DWC_ETH_QOS
-#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
-#endif
-
#define PHY_ANEG_TIMEOUT 20000
#endif
@@ -155,8 +150,8 @@
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_FSL_FSPI
#define FSL_FSPI_FLASH_SIZE SZ_32M
@@ -171,7 +166,6 @@
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
#endif /* CONFIG_NAND_MXS */
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index 6b87f0d..b1c213c 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -9,7 +9,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
index ab74d5b..4b2107e 100644
--- a/include/configs/imx8mq_cm.h
+++ b/include/configs/imx8mq_cm.h
@@ -10,8 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
@@ -58,7 +56,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index ea43056..2d4c8d7 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -10,8 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
@@ -64,7 +62,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
index 97bd504..1905e53 100644
--- a/include/configs/imx8mq_phanbell.h
+++ b/include/configs/imx8mq_phanbell.h
@@ -9,8 +9,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
@@ -96,7 +94,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index 5f9d06e..7f6d59d 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -11,8 +11,6 @@
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CONFIG_MALLOC_F_ADDR 0x00120000
diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
index 308f17f..67f19bc 100644
--- a/include/configs/imx8qm_rom7720.h
+++ b/include/configs/imx8qm_rom7720.h
@@ -11,7 +11,7 @@
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define USDHC3_BASE_ADDR 0x5B030000
@@ -106,7 +106,7 @@
* USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
* USDHC2 is for SD, USDHC3 is for SD on base board
*/
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index f8ec16e..567351f 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -11,8 +11,6 @@
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CONFIG_MALLOC_F_ADDR 0x00120000
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index ebfc166..7bf0ce7 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -9,7 +9,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index f9750da..b281466 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -10,7 +10,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
@@ -132,7 +131,7 @@
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index 7b9a5b1..bf09510 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -26,6 +26,5 @@
* Miscellaneous configurable options
*/
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
-#define CONFIG_SYS_MONITOR_LEN 0x00100000
#endif /* __CONFIG_H */
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 1bfc89b..35cf27a 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -15,9 +15,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_LOADS_ECHO
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
-
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
"actual_bank=0\0"
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 04192d8..181ed1b 100644
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -26,12 +26,10 @@
#define CONFIG_SYS_FLASH_BASE 0xF0000000
/* Reserve 768 kB for Mon */
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
/*
@@ -61,7 +59,6 @@
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
#endif
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 43471e0..0613b77 100644
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -119,7 +119,6 @@
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
@@ -155,7 +154,6 @@
/*
* I2C
*/
-#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_MAX_HOPS 1
@@ -179,8 +177,6 @@
#define CONFIG_LS102XA_STREAM_ID
-#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */
-
/*
* Environment
*/
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 1b19001..2e1459e 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -154,7 +154,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
@@ -278,7 +277,6 @@
/* More NAND Flash Params */
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* QRIO on IFC CS2 */
#define CONFIG_SYS_QRIO_BASE 0xfb000000
@@ -314,7 +312,6 @@
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
@@ -326,8 +323,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */
-
/*
* Serial Port - controlled on board with jumper J8
* open - index 2
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index b9d20c9..d6b60d8 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -11,7 +11,6 @@
#define CONFIG_HOSTNAME "kmcoge5ne"
#define CONFIG_NAND_ECC_BCH
#define CONFIG_NAND_KMETER1
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
index 3bf7970..d3447a8 100644
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -45,8 +45,8 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV
diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h
index d77e4b4..6acd2f7 100644
--- a/include/configs/kontron_pitx_imx8m.h
+++ b/include/configs/kontron_pitx_imx8m.h
@@ -7,8 +7,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
-
/* GUID for capsule updatable firmware image */
#define KONTRON_PITX_IMX8M_FIT_IMAGE_GUID \
EFI_GUID(0xc898e959, 0x5b1f, 0x4e6d, 0x88, 0xe0, \
@@ -72,7 +70,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index df46e58..38860bf 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -20,7 +20,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -32,15 +32,13 @@
/* generic timer */
/* early heap for SPL DM */
-#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
+#define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE
/* serial port */
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
-
/* GUID for capsule updatable firmware image */
#define KONTRON_SL28_FIT_IMAGE_GUID \
EFI_GUID(0x86ebd44f, 0xfeb8, 0x466f, 0x8b, 0xb8, \
diff --git a/include/configs/librem5.h b/include/configs/librem5.h
index 389469a..dbd7d10 100644
--- a/include/configs/librem5.h
+++ b/include/configs/librem5.h
@@ -15,8 +15,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
@@ -27,7 +25,7 @@
#endif /* CONFIG_SPL_BUILD*/
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_USBD_HS
@@ -90,6 +88,6 @@
/* Monitor Command Prompt */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index a1fc056..a784002 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -20,7 +20,7 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 87eb10d..77f84e1 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -11,12 +11,12 @@
#include <linux/sizes.h>
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index a0ff3b8..1b417c7 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -17,7 +17,7 @@
#define SYS_SDRAM_SIZE_1024 0x40000000
/* ENV */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index f418c8c..885774f 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -41,10 +41,6 @@
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-#endif
-
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 37b8cd7..926c858 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -10,16 +10,11 @@
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_MONITOR_LEN 0xc0000
-#endif
-
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
#define SPD_EEPROM_ADDRESS 0x51
@@ -107,7 +102,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
/*
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index 157f218..fce9119 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -50,9 +50,6 @@
* size increases then increase this size in case of secure boot as
* it uses raw U-Boot image instead of FIT image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 83c74b6..2c96b6f 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -53,9 +53,6 @@
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 2442266..43dbeea 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -14,7 +14,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -57,7 +57,7 @@
"env exists secureboot && esbc_halt;"
#define OCRAM_NONSECURE_SIZE 0x00010000
-#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE 0x20000000
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 9f146c4..8c19468 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -33,7 +33,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
@@ -54,9 +54,6 @@
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_NXP_ESBC */
#endif
@@ -76,9 +73,6 @@
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index 4158d15..d207e47 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -111,7 +111,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 4bfe4e3..206de7e 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -82,7 +82,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 26ce93a..7e1a724 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -33,7 +33,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
@@ -54,22 +54,13 @@
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_NXP_ESBC */
#endif
-#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
-#define CONFIG_SYS_MONITOR_LEN 0x100000
-#endif
-
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN 0xa0000
#endif
/* GPIO */
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 2df5f3f..48408f2 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -45,7 +45,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */
@@ -74,7 +73,7 @@
/*
* Environment
*/
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#undef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index b411efd..037d462 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -127,7 +127,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
index 5d32957..7693493 100644
--- a/include/configs/ls1046ardb.h
+++ b/include/configs/ls1046ardb.h
@@ -50,7 +50,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
/*
@@ -105,7 +104,7 @@
/*
* Environment
*/
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 7d76170..73e4ac3 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -27,11 +27,11 @@
/* Link Definitions */
/* Link Definitions */
-#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
/*
@@ -146,9 +146,6 @@
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
-#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_NXP_ESBC */
#endif
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 2d3351e..d50b76b 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -102,7 +102,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index d98ed39..4edf40b 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -86,7 +86,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index dc43ecb..53a3af1 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -18,7 +18,7 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
@@ -132,7 +132,6 @@
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#endif
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#include <asm/arch/soc.h>
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index d02d7fc..1fa4aa3 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -103,7 +103,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 09484dc..e1c66c5 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -100,7 +100,6 @@
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index ed69b85..8b2b747 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -15,7 +15,7 @@
/* DDR */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
@@ -27,7 +27,6 @@
#define SPD_EEPROM_ADDRESS5 0x55
#define SPD_EEPROM_ADDRESS6 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 03e1619..a20b41b 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -37,14 +37,13 @@
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
/*
* NAND
*/
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
@@ -66,7 +65,6 @@
*/
#ifdef CONFIG_CMD_DATE
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
#endif
/*
diff --git a/include/configs/malta.h b/include/configs/malta.h
index ff70a59..30c2e41 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -13,8 +13,6 @@
#define CONFIG_MEMSIZE_IN_BYTES
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-
/*
* CPU Configuration
*/
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
index 17986a0..69ca7c5 100644
--- a/include/configs/mccmon6.h
+++ b/include/configs/mccmon6.h
@@ -22,8 +22,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* NOR 16-bit mode */
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
index b35ba59..b90a84d 100644
--- a/include/configs/medcom-wide.h
+++ b/include/configs/medcom-wide.h
@@ -19,7 +19,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index cffcd9d..9f913fa 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -52,7 +52,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 6bcae31..50c52f8 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0" \
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h
index 59ab732..bd35378 100644
--- a/include/configs/msc_sm2s_imx8mp.h
+++ b/include/configs/msc_sm2s_imx8mp.h
@@ -14,7 +14,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#if defined(CONFIG_CMD_NET)
@@ -58,7 +57,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h
index 554c435..9b1ba36 100644
--- a/include/configs/mt7621.h
+++ b/include/configs/mt7621.h
@@ -15,13 +15,10 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
-#define CONFIG_SYS_NONCACHED_MEMORY 0x100000
-
/* MMC */
#define MMC_SUPPORTS_TUNING
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
index f995399..fd8e30a 100644
--- a/include/configs/mt7622.h
+++ b/include/configs/mt7622.h
@@ -9,10 +9,6 @@
#ifndef __MT7622_H
#define __MT7622_H
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
/* Uboot definition */
#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
index 0cd8b08..73093f9 100644
--- a/include/configs/mt7623.h
+++ b/include/configs/mt7623.h
@@ -13,8 +13,6 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
/* Environment */
/* Preloader -> Uboot */
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
index 22d11d0..668dc3c 100644
--- a/include/configs/mt7629.h
+++ b/include/configs/mt7629.h
@@ -13,8 +13,6 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
/* Environment */
/* Defines for SPL */
diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h
index 1f81b0b..9f26b0b 100644
--- a/include/configs/mt7981.h
+++ b/include/configs/mt7981.h
@@ -9,10 +9,6 @@
#ifndef __MT7981_H
#define __MT7981_H
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
/* Uboot definition */
#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h
index 00e1c57..4fbd57a 100644
--- a/include/configs/mt7986.h
+++ b/include/configs/mt7986.h
@@ -9,10 +9,6 @@
#ifndef __MT7986_H
#define __MT7986_H
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
/* Uboot definition */
#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h
index 5ff5541..d159416 100644
--- a/include/configs/mt8512.h
+++ b/include/configs/mt8512.h
@@ -9,10 +9,6 @@
#ifndef __MT8512_H
#define __MT8512_H
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
/* Uboot definition */
#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE
diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h
index 6d47046..7cabbef 100644
--- a/include/configs/mt8518.h
+++ b/include/configs/mt8518.h
@@ -9,11 +9,6 @@
#ifndef __MT8518_H
#define __MT8518_H
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
-
-
/* DRAM definition */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 20e00ec..6d4fff3 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -61,8 +61,5 @@
/*
* Common NAND configuration
*/
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
#endif /* _MV_COMMON_H */
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
index 5a956f0..5debd91 100644
--- a/include/configs/mvebu_armada-8k.h
+++ b/include/configs/mvebu_armada-8k.h
@@ -25,8 +25,6 @@
/* When runtime detection fails this is the default */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
/* USB ethernet */
/*
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index fbc9a04..95afb35 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -34,7 +34,7 @@
/*
* MMC Configs
* */
-#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index d58d153..7783563 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -17,7 +17,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* bootz: zImage/initrd.img support */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 60ec34c..3c9b2ad 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -14,7 +14,7 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
@@ -25,7 +25,7 @@
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
+#define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index cffbb64..bc90b95 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -14,7 +14,7 @@
#include "imx6_spl.h"
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Framebuffer */
#define CONFIG_IMX_HDMI
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index bfcab1b..bc9fab1 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -13,7 +13,7 @@
#include "mx6_common.h"
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_SUPPORT_EMMC_BOOT
#define EMMC_ENV \
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index c76e7ea..61570b7 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -33,10 +33,9 @@
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#endif
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 16f8858..49cd151 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -21,7 +21,7 @@
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 9f89093..26b97bd3 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -17,7 +17,7 @@
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
@@ -98,6 +98,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#endif
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_USDHC_NUM 3
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index e9ccb99..44a5eef 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -89,8 +89,8 @@
/* Environment organization */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_IOMUX_LPSR
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index c878041..0d9764e 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -83,10 +83,9 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
@@ -101,6 +100,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#endif
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 570e2ce..83779f0 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -115,7 +115,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* Network */
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index ab56ea0..d0e3d3f 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -22,13 +22,13 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* NAND pin conflicts with usdhc2 */
#ifdef CONFIG_NAND_MXS
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#else
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#endif
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 00cc547..604923e 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -20,8 +20,8 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index b96341a..2a97d2f 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -93,7 +93,6 @@
*/
#ifdef CONFIG_NAND_MXS
/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index fc15ed8..e861038 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -83,7 +83,6 @@
/* NAND */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#endif
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index 4162ee8..a777305 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -13,13 +13,13 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -30,7 +30,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index d507f8f..ec5339d 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -16,8 +16,8 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 6
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 1696aa2..f2a04ca 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -43,8 +43,8 @@
/* I2C EEPROM */
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
/* PCI express */
#ifdef CONFIG_CMD_PCI
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index 217427a..ccc203f 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -13,13 +13,13 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_NETMASK 255.255.255.0
@@ -31,7 +31,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */
diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h
index 25116c5..ab1eb78 100644
--- a/include/configs/octeontx2_common.h
+++ b/include/configs/octeontx2_common.h
@@ -19,8 +19,6 @@
"loadaddr=20080000\0" \
"ethrotate=yes\0"
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
-
#if defined(CONFIG_MMC_OCTEONTX)
#define MMC_SUPPORTS_TUNING
/** EMMC specific defines */
diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h
index 373eb91..38f99ab 100644
--- a/include/configs/octeontx_common.h
+++ b/include/configs/octeontx_common.h
@@ -42,12 +42,6 @@
/** Heap size for U-Boot */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
-
/** EMMC specific defines */
-#if defined(CONFIG_NAND_OCTEONTX)
-#define CONFIG_SYS_MAX_NAND_DEVICE 8
-#endif
-
#endif /* __OCTEONTX_COMMON_H__ */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index ad3dbbc..d46ca33 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -21,7 +21,6 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index c47d557..77629d7 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -26,7 +26,6 @@
/* NAND */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 1af87b2..442a3ca 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -16,7 +16,6 @@
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index c644768..4103930 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -105,14 +105,12 @@
* Flash & Environment
*/
#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 543a16f..778bf51 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -27,7 +27,6 @@
#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
-#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
/*
@@ -58,7 +57,6 @@
#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
-#define CONFIG_SYS_L2_SIZE (256 << 10)
/*
* Dynamic MTD Partition support with mtdparts
*/
@@ -79,7 +77,6 @@
#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
-#define CONFIG_SYS_L2_SIZE (512 << 10)
/*
* Dynamic MTD Partition support with mtdparts
*/
@@ -218,7 +215,6 @@
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
@@ -245,7 +241,6 @@
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
@@ -265,8 +260,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
#define CONFIG_SYS_CPLD_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
@@ -419,15 +412,12 @@
#endif
#endif
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
/*
* USB
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 6e593da..dea8712 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -22,14 +22,14 @@
* Tweak the SPL text base address to avoid this.
*/
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
/* Miscellaneous configurable options */
@@ -42,7 +42,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index ae81b8e..2bdae8a 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -16,7 +16,7 @@
/* SPL options */
#include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* Environment settings */
@@ -29,7 +29,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C configs */
@@ -44,7 +44,6 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index a8cfec9..a04a03a 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -14,8 +14,6 @@
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
/* if no target-specific extra environment settings were defined by the
target, define an empty one */
#ifndef PCM052_EXTRA_ENV_SETTINGS
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
index cff71df..0119090 100644
--- a/include/configs/pcm058.h
+++ b/include/configs/pcm058.h
@@ -15,7 +15,6 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
/* Enable NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index 049d1d7..c98393b 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -11,7 +11,6 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index df17161..49cd9d4 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -10,7 +10,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 9d796f9..4ea16d6 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -25,8 +25,6 @@
/* SDRAM Configuration (for final code, data, stack, heap) */
#define CONFIG_SYS_SDRAM_BASE 0x88000000
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
/* Memory Test */
/*----------------------------------------------------------------------
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index dcbcd8d..687133b 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -21,7 +21,7 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index c0d837d..d4f58b6 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -27,7 +27,7 @@
#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 7fbf2c3..159bf4c 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -21,7 +21,7 @@
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* MMC Config */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=" \
@@ -113,7 +113,7 @@
/* Environment starts at 768k = 768 * 1024 = 786432 */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h
index d1cc1b9..17af19d 100644
--- a/include/configs/pico-imx8mq.h
+++ b/include/configs/pico-imx8mq.h
@@ -9,8 +9,6 @@
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
@@ -75,7 +73,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 9a4a632..09f0ed9 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -19,7 +19,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 7f9442a..278f1b5 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -129,7 +129,6 @@
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* NAND flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD22 */
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 00d159f..7c23206 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -146,7 +146,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
/* our ALE is AD21 */
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 69f3d06..35fd525 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -25,7 +25,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
@@ -44,8 +43,6 @@
/* Defines for SPL */
-#define CONFIG_SYS_MONITOR_LEN 0x80000
-
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h
index 90f548c..ebf5467 100644
--- a/include/configs/presidio_asic.h
+++ b/include/configs/presidio_asic.h
@@ -58,7 +58,6 @@
/* nand driver parameters */
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
- #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#endif
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 5181792..9fc51fd 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -46,18 +46,10 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
/* RTC */
#define CONFIG_RTC_PT7C4338
/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index ba843e3..5cd1388 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -22,8 +22,6 @@
#include <config_distro_bootcmd.h>
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index f0dfba3..ac39e11 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -10,7 +10,6 @@
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/*
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 2e54211..3a38e06 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -20,8 +20,6 @@
#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-
/* Timer */
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_TIMER_COUNTS_DOWN
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index 9efda3e..7432cff 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -31,8 +31,6 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024)
-
/* ENV setting */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index f4b3481..81f16ed 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -19,8 +19,6 @@
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0xfe000000
-#define CONFIG_SYS_MONITOR_LEN (600 * 1024)
-
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 712a47a..de4510a 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -121,8 +121,6 @@
#define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */
#define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
-
/* FLASH and environment organization */
#define CONFIG_MMC_DEFAULT_DEV 0
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index b9b56d9..70c6ec5 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -28,7 +28,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 0eecb56..79f354d 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -16,6 +16,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h
index 178a6ad..de6c92e 100644
--- a/include/configs/sama5d27_wlsom1_ek.h
+++ b/include/configs/sama5d27_wlsom1_ek.h
@@ -21,6 +21,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
index b18377b..ebdb392 100644
--- a/include/configs/sama5d2_icp.h
+++ b/include/configs/sama5d2_icp.h
@@ -28,6 +28,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
index 3b91e83..9281c7c 100644
--- a/include/configs/sama5d2_ptc_ek.h
+++ b/include/configs/sama5d2_ptc_ek.h
@@ -21,7 +21,6 @@
/* NAND Flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index bbd7297..da2ae96 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -13,6 +13,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index fad65cb..eed688d 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -29,7 +29,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
@@ -40,7 +39,6 @@
/* SPL */
/* size of u-boot.bin to load */
-#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K)
/* Falcon boot support on raw MMC */
/* U-Boot proper stored by default at 0x200 (256 KiB) */
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index ccb3842..b05fa59 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -38,7 +38,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
@@ -48,6 +47,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index d5cd45c..c4552c2 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -17,7 +17,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
@@ -27,6 +26,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 411ed29..d719992 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -17,7 +17,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
@@ -27,6 +26,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10)
-
#endif
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index e6c200f..c7f03a1 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -29,7 +29,6 @@
/* NAND support */
/* Max number of NAND devices */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#include "tegra-common-post.h"
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 5759794..87da5e4 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -368,8 +368,6 @@
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
- devices */
#endif
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 802ed07..a77215d 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -54,7 +54,6 @@
*/
/* NAND flash settings */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 1395b8d..ba562b2 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -84,8 +84,6 @@
* FLASH and environment organization
*/
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
-
/*-----------------------------------------------------------------------
* Boot configuration
*/
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 681c831..faa13c6 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -15,7 +15,7 @@
#define PHYS_SDRAM_SIZE SZ_512M
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=zImage\0" \
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index 59bba7d..c56fb37 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -30,7 +30,6 @@
/* NAND Flash */
#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c3f30af..704a714 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -68,19 +68,9 @@
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
/*
- * MMC Driver
- */
-#ifdef CONFIG_CMD_MMC
-/* FIXME */
-/* using smaller max blk cnt to avoid flooding the limited stack we have */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
-#endif
-
-/*
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 06198dd..86cc377 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -81,9 +81,6 @@
/*
* SDMMC configurations
*/
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
-#endif
/*
* Flash configurations
*/
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 762ba44..3c978f5 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -78,8 +78,6 @@
/*
* Flash on the LocalBus
*/
-#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
-
#define CONFIG_SYS_FLASH0 0xFE000000
#define CONFIG_SYS_FLASH1 0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
@@ -92,24 +90,19 @@
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
-
/* FPGA and NAND */
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
-#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
/*
* General PCI
@@ -140,13 +133,6 @@
/* Options are: TSEC[0,1] */
/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h
index 201f2c2..ee038d8 100644
--- a/include/configs/som-db5800-som-6867.h
+++ b/include/configs/som-db5800-som-6867.h
@@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index eeee587..49672df 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -19,9 +19,9 @@
/* MMC Configs */
#ifdef CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#endif /* CONFIG_FSL_USDHC */
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index b0ec226..c7d6d93 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -33,7 +33,6 @@
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
CONFIG_SPL_PAD_TO)
diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h
index 78089b9..07a5bfc 100644
--- a/include/configs/stm32mp13_common.h
+++ b/include/configs/stm32mp13_common.h
@@ -21,11 +21,7 @@
*/
#define CONFIG_SYS_BOOTMAPSZ SZ_256M
-/*MMC SD*/
-#define CONFIG_SYS_MMC_MAX_DEVICE 2
-
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/*****************************************************************************/
#ifdef CONFIG_DISTRO_DEFAULTS
diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h
index 214901c..b809f93 100644
--- a/include/configs/stm32mp15_common.h
+++ b/include/configs/stm32mp15_common.h
@@ -21,11 +21,7 @@
*/
#define CONFIG_SYS_BOOTMAPSZ SZ_256M
-/*MMC SD*/
-#define CONFIG_SYS_MMC_MAX_DEVICE 3
-
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Ethernet need */
#ifdef CONFIG_DWC_ETH_QOS
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index d8a3348..ba49075 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -34,10 +34,6 @@
"sf write ${loadaddr} 0x00800000 ${filesize}\0" \
""
-/* Realtime clock */
-#define CONFIG_RTC_MCFRRTC
-#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
-
#define CONFIG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */
@@ -72,7 +68,6 @@
#endif
/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 12666b7..7207686 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -73,14 +73,11 @@
#ifdef CONFIG_NAND_SUNXI
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
-#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif
/* mmc config */
#define CONFIG_MMC_SUNXI_SLOT 0
-#define CONFIG_SYS_MMC_MAX_DEVICE 4
-
/*
* Miscellaneous configurable options
*/
@@ -90,8 +87,6 @@
/* FLASH and environment organization */
-#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
-
/*
* We cannot use expressions here, because expressions won't be evaluated in
* autoconf.mk.
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index a29652d..45780d9 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -54,7 +54,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 432ccbd..2377b47 100644
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
@@ -19,7 +19,6 @@
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index 4e20e1d..69acabf 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -7,8 +7,6 @@
#ifndef __TEGRA_COMMON_POST_H
#define __TEGRA_COMMON_POST_H
-#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
-
#if CONFIG_IS_ENABLED(CMD_USB)
# define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 159ba09..2915db7 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -28,13 +28,6 @@
*/
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-/*
- * Common HW configuration.
- * If this varies between SoCs later, move to tegraNN-common.h
- * Note: This is number of devices, not max device ID.
- */
-#define CONFIG_SYS_MMC_MAX_DEVICE 4
-
#ifdef CONFIG_ARM64
#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#else
diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h
index eaa19ee..af0a095 100644
--- a/include/configs/theadorable-x86-common.h
+++ b/include/configs/theadorable-x86-common.h
@@ -11,8 +11,6 @@
#ifndef __THEADORABLE_X86_COMMON_H
#define __THEADORABLE_X86_COMMON_H
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 1aca83a..82add65 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -43,7 +43,6 @@
* access CS0 at is 0x8000000.
*/
#define CONFIG_SYS_NAND_BASE 0x8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND: SPL related configs */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 29a6038..6c01ab8 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -65,11 +65,9 @@
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_CS 2
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define DFU_ALT_INFO_MMC \
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index 727c648..44706c7 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -19,7 +19,6 @@
#ifndef CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE 0x8000000
#endif
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#endif
/* Now for the remaining common defines */
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 725a5a6..47f3c81 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -52,8 +52,6 @@
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-
/* SPL */
#ifdef CONFIG_MTD_RAW_NAND
diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
index 7c77a8d..ab6cd06 100644
--- a/include/configs/total_compute.h
+++ b/include/configs/total_compute.h
@@ -28,8 +28,6 @@
#define PHYS_SDRAM_2 0x8080000000
#define PHYS_SDRAM_2_SIZE 0x180000000
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
"load_addr=0xa0000000\0" \
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 9498dbe..2c58915 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -44,7 +44,7 @@
#endif
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index f5a9f12..7eed31c 100644
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -31,8 +31,4 @@
#include "km/km-mpc83xx.h"
#include "km/km-mpc832x.h"
-#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
- 0x0000c000 | \
- MxMR_WLFx_2X)
-
#endif /* __CONFIG_H */
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 03e5c04..8af5151 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -15,7 +15,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc1,115200\0" \
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index e30b6cc..093e2e8 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -15,7 +15,7 @@
#include "imx6_spl.h"
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Command definition */
#define CONFIG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index d9e95ab..32b47db 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -35,14 +35,11 @@
BOOT_TARGET_DEVICE_UBIFS(func) \
BOOT_TARGET_DEVICE_USB(func)
-#define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */
-
#if !defined(CONFIG_ARM64)
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE 1000000
#endif
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index e0dde1c..44eaeda 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -33,7 +33,6 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 08a6f5f..c381934 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -20,7 +20,7 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SD/MMC */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB */
#define CONFIG_MXC_USB_PORT 1
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index 1de0023..f513dad 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -9,7 +9,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h
index ce72798..fea4329 100644
--- a/include/configs/verdin-imx8mp.h
+++ b/include/configs/verdin-imx8mp.h
@@ -9,7 +9,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 7c0856a..5d77306 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -124,8 +124,6 @@
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
-
/* Miscellaneous configurable options */
#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index c13f2ba..7e3d347 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -14,13 +14,12 @@
/* NAND support */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
/* Dynamic MTD partition support */
#endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 6eb022f..a4484fd 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -32,7 +32,7 @@
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* PMIC */
#define CONFIG_POWER_PFUZE100
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 899b8ca..91c1f4b 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -15,8 +15,8 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_SYS_FSL_USDHC_NUM 2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index a9cc859..a4b12dc 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -14,7 +14,7 @@
#define PHYS_SDRAM_SIZE SZ_512M
/* MMC Config*/
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
@@ -90,7 +90,7 @@
/* environment organization */
-#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CFG_SYS_FSL_USDHC_NUM 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index f53ea3c..a7c805c 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -42,7 +42,6 @@
*/
/* driver configuration */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_MAX_NAND_CHIPS 1
#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
@@ -64,7 +63,6 @@
/* SPL will use serial */
/* SPL will load U-Boot from NAND offset 0x40000 */
/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
-#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
diff --git a/include/configs/x530.h b/include/configs/x530.h
index cb12683..0add626 100644
--- a/include/configs/x530.h
+++ b/include/configs/x530.h
@@ -27,7 +27,6 @@
*/
/* NAND */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BBT_CUSTOM_SCAN
#define BBT_CUSTOM_SCAN_PAGE 0
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 4109af7..ec87edd 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -6,8 +6,6 @@
#ifndef _X86_CHROMEBOOK_H
#define _X86_CHROMEBOOK_H
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-
#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_X86_REFCODE_ADDR 0xffea0000
#define CONFIG_X86_REFCODE_RUN_ADDR 0
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 42b2cb2..8e22d6e 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -19,12 +19,6 @@
#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
-
-/*-----------------------------------------------------------------------
* Serial Configuration
*/
#define CONFIG_SYS_NS16550_PORT_MAPPED
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index f72f3e6..60f007a 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -27,10 +27,6 @@
EFI_GUID(0xcf9ecfd4, 0x938b, 0x41c5, 0x85, 0x51, \
0x1f, 0x88, 0x3a, 0xb7, 0xdc, 0x18)
-#ifdef CONFIG_NAND_ARASAN
-# define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
-
/* Miscellaneous configurable options */
#if defined(CONFIG_ZYNQMP_USB)
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 0e43b37..fc8ec32 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -16,7 +16,7 @@
#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Miscellaneous configurable options */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index ad8ea65..58d01f4 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -50,11 +50,6 @@
#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
-#ifdef CONFIG_XTFPGA_LX60
-# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
-#else
-# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
-#endif
/* Memory test is destructive so default must not overlap vectors or U-Boot*/
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index dc0cba0..6574cf9 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -40,10 +40,6 @@
# define CONFIG_FLASH_SHOW_PROGRESS 10
#endif
-#ifdef CONFIG_NAND_ZYNQ
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
-
#ifdef CONFIG_USB_EHCI_ZYNQ
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_THOR_RESET_OFF
@@ -199,9 +195,6 @@
/* Extend size of kernel image for uncompression */
-/* Boot FreeBSD/vxWorks from an ELF image */
-#define CONFIG_SYS_MMC_MAX_DEVICE 1
-
/* Address in RAM where the parameters must be copied by SPL. */
/* Not using MMC raw mode - just for compilation purpose */
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 1f3cf8c..376f741 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -63,6 +63,7 @@
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_HASH, /* Hash device */
UCLASS_HWSPINLOCK, /* Hardware semaphores */
+ UCLASS_HOST, /* Sandbox host device */
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */
diff --git a/include/fm_eth.h b/include/fm_eth.h
index bf95706..7475b51 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -51,18 +51,18 @@
*/
#ifdef CONFIG_SYS_FMAN_V3
#ifdef CONFIG_TARGET_LS1046AFRWY
-#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#else
-#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
#endif
-#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CONFIG_SYS_NUM_FMAN == 2)
-#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
-#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
+#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
#endif
#else
-#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
-#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
+#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000)
#endif
#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
@@ -84,7 +84,7 @@
.port = FM##idx##_DTSEC##n, \
.rx_port_id = RX_PORT_1G_BASE + n - 1, \
.tx_port_id = TX_PORT_1G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1]),\
}
@@ -98,7 +98,7 @@
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE2 + n - 1, \
.tx_port_id = TX_PORT_10G_BASE2 + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1]),\
}
#else
@@ -112,7 +112,7 @@
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#else
@@ -125,7 +125,7 @@
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
#endif
@@ -141,7 +141,7 @@
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE2 + n - 3, \
.tx_port_id = TX_PORT_10G_BASE2 + n - 3, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1-2]),\
}
#endif
@@ -156,7 +156,7 @@
.port = FM##idx##_DTSEC##n, \
.rx_port_id = RX_PORT_1G_BASE + n - 1, \
.tx_port_id = TX_PORT_1G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_1g[n-1]),\
}
@@ -169,7 +169,7 @@
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
- .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_10g[n-1]),\
}
#endif
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index d57c4ca..d8861d1 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -272,7 +272,7 @@
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Job Ring Base Address */
-#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
+#define JR_BASE_ADDR(x) (CFG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */
#define SM_V1_OFFSET 0x0f4
#define SM_V2_OFFSET 0xa00
@@ -287,7 +287,7 @@
/* JR Allocation Error */
#define SMCSJR_AERR (3 << 12)
/* Secure memory partition 0 page 0 owner register */
-#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
+#define CAAM_SMPO_0 (CFG_SYS_FSL_SEC_ADDR + 0x1FBC)
/* Secure memory command register */
#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
/* Secure memory command status register */
diff --git a/include/mk48t59.h b/include/mk48t59.h
index 5d863ef..f95d349 100644
--- a/include/mk48t59.h
+++ b/include/mk48t59.h
@@ -11,9 +11,9 @@
#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
-#define RTC_PORT_ADDR0 CONFIG_SYS_ISA_IO + 0x70
+#define RTC_PORT_ADDR0 0x70
#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1
-#define RTC_PORT_DATA CONFIG_SYS_ISA_IO + 0x76
+#define RTC_PORT_DATA 0x76
/* RTC Offsets */
#define RTC_SECONDS 0x1FF9
diff --git a/include/mmc.h b/include/mmc.h
index 027e8bc..571fa62 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -952,11 +952,6 @@
/* Minimum partition switch timeout in units of 10-milliseconds */
#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
-/* Set block count limit because of 16 bit register limit on some hardware*/
-#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
-#endif
-
/**
* mmc_get_blk_desc() - Get the block descriptor for an MMC device
*
diff --git a/include/os.h b/include/os.h
index 54874f5..0415f0f 100644
--- a/include/os.h
+++ b/include/os.h
@@ -110,6 +110,10 @@
/**
* os_alarm() - access to the OS alarm() system call
+ *
+ * @seconds: number of seconds before the signal is sent
+ * Returns: number of seconds remaining until any previously scheduled alarm was
+ * due to be delivered; 0 if there was no previously scheduled alarm
*/
unsigned int os_alarm(unsigned int seconds);
diff --git a/include/post.h b/include/post.h
index a07a6bc..ec03556 100644
--- a/include/post.h
+++ b/include/post.h
@@ -27,7 +27,7 @@
#elif defined (CONFIG_MPC85xx)
#include <asm/immap_85xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET + \
offsetof(ccsr_pic_t, tfrr))
#endif
diff --git a/include/sandbox_host.h b/include/sandbox_host.h
new file mode 100644
index 0000000..2e37ede
--- /dev/null
+++ b/include/sandbox_host.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sandbox host uclass
+ *
+ * Copyright 2022 Google LLC
+ */
+
+#ifndef __SANDBOX_HOST__
+#define __SANDBOX_HOST__
+
+/**
+ * struct host_sb_plat - platform data for a host device
+ *
+ * @label: Label for this device (allocated)
+ * @filename: Name of file this is attached to, or NULL (allocated)
+ * @fd: File descriptor of file, or 0 for none (file is not open)
+ */
+struct host_sb_plat {
+ char *label;
+ char *filename;
+ int fd;
+};
+
+/**
+ * struct host_ops - operations supported by UCLASS_HOST
+ *
+ * @attach_file: Attach a new file to a device
+ * @detach_file: Detach a file from a device
+ */
+struct host_ops {
+ /*
+ * attach_file() - Attach a new file to the device
+ *
+ * @dev: Device to update
+ * @filename: Name of the file, e.g. "/path/to/disk.img"
+ * Returns: 0 if OK, -EEXIST if a file is already attached, other -ve on
+ * other error
+ */
+ int (*attach_file)(struct udevice *dev, const char *filename);
+
+ /**
+ * detach_file() - Detach a file from the device
+ *
+ * @dev: Device to detach from
+ * Returns: 0 if OK, -ENOENT if no file is attached, other -ve on other
+ * error
+ */
+ int (*detach_file)(struct udevice *dev);
+};
+
+#define host_get_ops(dev) ((struct host_ops *)(dev)->driver->ops)
+
+/**
+ * host_attach_file() - Attach a new file to the device
+ *
+ * @dev: Device to update
+ * @filename: Name of the file, e.g. "/path/to/disk.img"
+ * Returns: 0 if OK, -EEXIST if a file is already attached, other -ve on
+ * other error
+ */
+int host_attach_file(struct udevice *dev, const char *filename);
+
+/**
+ * host_detach_file() - Detach a file from the device
+ *
+ * @dev: Device to detach from
+ * Returns: 0 if OK, -ENOENT if no file is attached, other -ve on other
+ * error
+ */
+int host_detach_file(struct udevice *dev);
+
+/**
+ * host_create_device() - Create a new host device
+ *
+ * Any existing device with the same label is removed and unbound first
+ *
+ * @label: Label of the attachment, e.g. "test1"
+ * @removable: true if the device should be marked as removable, false
+ * if it is fixed. See enum blk_flag_t
+ * @devp: Returns the device created, on success
+ * Returns: 0 if OK, -ve on error
+ */
+int host_create_device(const char *label, bool removable,
+ struct udevice **devp);
+
+/**
+ * host_create_attach_file() - Create a new host device attached to a file
+ *
+ * @label: Label of the attachment, e.g. "test1"
+ * @filename: Name of the file, e.g. "/path/to/disk.img"
+ * @removable: true if the device should be marked as removable, false
+ * if it is fixed. See enum blk_flag_t
+ * @devp: Returns the device created, on success
+ * Returns: 0 if OK, -ve on error
+ */
+int host_create_attach_file(const char *label, const char *filename,
+ bool removable, struct udevice **devp);
+
+/**
+ * host_find_by_label() - Find a host by label
+ *
+ * Searches all host devices to find one with the given label
+ *
+ * @label: Label to find
+ * Returns: associated device, or NULL if not found
+ */
+struct udevice *host_find_by_label(const char *label);
+
+/**
+ * host_get_cur_dev() - Get the current device
+ *
+ * Returns current device, or NULL if none
+ */
+struct udevice *host_get_cur_dev(void);
+
+/**
+ * host_set_cur_dev() - Set the current device
+ *
+ * Sets the current device, or clears it if @dev is NULL
+ *
+ * @dev: Device to set as the current one
+ */
+void host_set_cur_dev(struct udevice *dev);
+
+#endif /* __SANDBOX_HOST__ */
diff --git a/include/sandboxblockdev.h b/include/sandboxblockdev.h
deleted file mode 100644
index dc983f0..0000000
--- a/include/sandboxblockdev.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013, Henrik Nordstrom <henrik@henriknordstrom.net>
- */
-
-#ifndef __SANDBOX_BLOCK_DEV__
-#define __SANDBOX_BLOCK_DEV__
-
-/* Maximum number of host devices - see drivers/block/sandbox.c */
-#define SANDBOX_HOST_MAX_DEVICES 4
-
-struct host_block_dev {
-#ifndef CONFIG_BLK
- struct blk_desc blk_dev;
-#endif
- char *filename;
- int fd;
-};
-
-/**
- * host_dev_bind() - Bind or unbind a device
- *
- * @dev: Device number (0=first slot)
- * @filename: Host filename to use, or NULL to unbind
- * @removable: true if the block device should mark itself as removable
- */
-int host_dev_bind(int dev, char *filename, bool removable);
-
-int host_get_dev_err(int dev, struct blk_desc **blk_devp);
-
-#endif
diff --git a/include/test/ut.h b/include/test/ut.h
index e0e618b..4d00b4e 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -410,10 +410,15 @@
* then all tests are run
* @runs_per_test: Number of times to run each test (typically 1)
* @force_run: Run tests that are marked as manual-only (UT_TESTF_MANUAL)
+ * @test_insert: String describing a test to run after n other tests run, in the
+ * format n:name where n is the number of tests to run before this one and
+ * name is the name of the test to run. This is used to find which test causes
+ * another test to fail. If the one test fails, testing stops immediately.
+ * Pass NULL to disable this
* Return: 0 if all tests passed, -1 if any failed
*/
int ut_run_list(const char *name, const char *prefix, struct unit_test *tests,
int count, const char *select_name, int runs_per_test,
- bool force_run);
+ bool force_run, const char *test_insert);
#endif
diff --git a/include/w83c553f.h b/include/w83c553f.h
deleted file mode 100644
index 2403e34..0000000
--- a/include/w83c553f.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- */
-
- /* winbond access routines and defines*/
-
-/* from the winbond data sheet -
- The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
- Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
-*/
-
-/*ISA bridge configuration space*/
-
-#define W83C553F_VID 0x10AD
-#define W83C553F_DID 0x0565
-
-#define WINBOND_PCICONTR 0x40 /*pci control reg*/
-#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
-#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
-#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
-#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
-#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
-#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
-#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
-#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
-#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
-#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
-#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
-#define WINBOND_ATSCR 0x4e /*AT System Control register*/
-#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
-#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
-#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
-#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
-#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
-
-#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
-
-#define IPADCR_MBE512 0x1
-#define IPADCR_MBE640 0x2
-#define IPADCR_IPATOM4 0x10
-#define IPADCR_IPATOM5 0x20
-#define IPADCR_IPATOM6 0x40
-#define IPADCR_IPATOM7 0x80
-
-#define CSCR_UBIOSCSE 0x10
-#define CSCR_BIOSWP 0x20
-
-#define IDECSR_P0EN 0x01
-#define IDECSR_P0F16 0x02
-#define IDECSR_P1EN 0x10
-#define IDECSR_P1F16 0x20
-#define IDECSR_LEGIRQ 0x800
-
-/*
- * Interrupt controller
- */
-#define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20
-#define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21
-#define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21
-#define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21
-#define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21
-#define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20
-#define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20
-#define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0
-#define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0
-#define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1
-#define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1
-#define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1
-#define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1
-#define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0
-#define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0
-#define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1
-
-#define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43
-
-/*
- * DMA controller
- */
-#define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
-#define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
-
-/* command/status register bit definitions */
-
-#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
-#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
-#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
-#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
-
-#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
-#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
-#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
-#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
-
-#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
-#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
-#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
-#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
-
-/* mode register bit definitions */
-
-#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
-#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
-#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
-#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
-#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
-#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
-#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
-#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
-#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
-#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
-#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
-#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
-#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
-#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
-
-/* request register bit definitions */
-
-#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
-#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
-#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
-#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
-#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
-
-/* write single mask bit register bit definitions */
-
-#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
-#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
-#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
-#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
-#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
-
-/* read/write all mask bits register bit definitions */
-
-#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
-#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
-#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
-#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
-
-/* typedefs */
-
-#define W83C553F_DMA1_CS 0x8
-#define W83C553F_DMA1_WR 0x9
-#define W83C553F_DMA1_WSMB 0xA
-#define W83C553F_DMA1_WM 0xB
-#define W83C553F_DMA1_CBP 0xC
-#define W83C553F_DMA1_MC 0xD
-#define W83C553F_DMA1_CM 0xE
-#define W83C553F_DMA1_RWAMB 0xF
-
-#define W83C553F_DMA2_CS 0x10
-#define W83C553F_DMA2_WR 0x12
-#define W83C553F_DMA2_WSMB 0x14
-#define W83C553F_DMA2_WM 0x16
-#define W83C553F_DMA2_CBP 0x18
-#define W83C553F_DMA2_MC 0x1A
-#define W83C553F_DMA2_CM 0x1C
-#define W83C553F_DMA2_RWAMB 0x1E
-
-void initialise_w83c553f(void);
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index d45985a..3b267b7 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -17,7 +17,6 @@
#include <nvme.h>
#include <efi_loader.h>
#include <part.h>
-#include <sandboxblockdev.h>
#include <uuid.h>
#include <asm-generic/unaligned.h>
#include <linux/compat.h> /* U16_MAX */
@@ -556,7 +555,7 @@
sizeof(struct efi_device_path_nvme);
#endif
#ifdef CONFIG_SANDBOX
- case UCLASS_ROOT:
+ case UCLASS_HOST:
/*
* Sandbox's host device will be represented
* as vendor device with extra one byte for
@@ -633,7 +632,7 @@
case UCLASS_BLK:
switch (dev->parent->uclass->uc_drv->id) {
#ifdef CONFIG_SANDBOX
- case UCLASS_ROOT: {
+ case UCLASS_HOST: {
/* stop traversing parents at this point: */
struct efi_device_path_vendor *dp;
struct blk_desc *desc = dev_get_uclass_plat(dev);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index a50a46c..7ea0334 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -555,7 +555,7 @@
if (ret == EFI_NOT_READY)
log_notice("Disk %s not ready\n", dev->name);
else
- log_err("Adding disk for %s failed\n", dev->name);
+ log_err("Adding disk for %s failed (err=%ld/%#lx)\n", dev->name, ret, ret);
return -1;
}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c3e0f53..c0f55e4 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -66,148 +66,6 @@
CONFIG_HDMI_ENCODER_I2C_ADDR
CONFIG_HIKEY_GPIO
CONFIG_HOSTNAME
-CONFIG_HPS_ALTERAGRP_DBGATCLK
-CONFIG_HPS_ALTERAGRP_MAINCLK
-CONFIG_HPS_ALTERAGRP_MPUCLK
-CONFIG_HPS_CLK_CAN0_HZ
-CONFIG_HPS_CLK_CAN1_HZ
-CONFIG_HPS_CLK_EMAC0_HZ
-CONFIG_HPS_CLK_EMAC1_HZ
-CONFIG_HPS_CLK_F2S_PER_REF_HZ
-CONFIG_HPS_CLK_F2S_SDR_REF_HZ
-CONFIG_HPS_CLK_GPIODB_HZ
-CONFIG_HPS_CLK_L4_MP_HZ
-CONFIG_HPS_CLK_L4_SP_HZ
-CONFIG_HPS_CLK_MAINVCO_HZ
-CONFIG_HPS_CLK_NAND_HZ
-CONFIG_HPS_CLK_OSC1_HZ
-CONFIG_HPS_CLK_OSC2_HZ
-CONFIG_HPS_CLK_PERVCO_HZ
-CONFIG_HPS_CLK_QSPI_HZ
-CONFIG_HPS_CLK_SDMMC_HZ
-CONFIG_HPS_CLK_SDRVCO_HZ
-CONFIG_HPS_CLK_SPIM_HZ
-CONFIG_HPS_CLK_USBCLK_HZ
-CONFIG_HPS_DBCTRL_STAYOSC1
-CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
-CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
-CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
-CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
-CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
-CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
-CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
-CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
-CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
-CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
-CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
-CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
-CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
-CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
-CONFIG_HPS_MAINPLLGRP_VCO_DENOM
-CONFIG_HPS_MAINPLLGRP_VCO_NUMER
-CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
-CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
-CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
-CONFIG_HPS_PERPLLGRP_DIV_USBCLK
-CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
-CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
-CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
-CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
-CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
-CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
-CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
-CONFIG_HPS_PERPLLGRP_SRC_NAND
-CONFIG_HPS_PERPLLGRP_SRC_QSPI
-CONFIG_HPS_PERPLLGRP_SRC_SDMMC
-CONFIG_HPS_PERPLLGRP_VCO_DENOM
-CONFIG_HPS_PERPLLGRP_VCO_NUMER
-CONFIG_HPS_PERPLLGRP_VCO_PSRC
-CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
-CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
-CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
-CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
-CONFIG_HPS_SDRPLLGRP_VCO_DENOM
-CONFIG_HPS_SDRPLLGRP_VCO_NUMER
-CONFIG_HPS_SDRPLLGRP_VCO_SSRC
-CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
-CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
-CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
-CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
-CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
-CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
-CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
-CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
-CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
-CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
-CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
-CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
-CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
-CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
-CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
-CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
-CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
-CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
-CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
-CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
-CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
-CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
-CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
-CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
-CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
-CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
CONFIG_HSMMC2_8BIT
CONFIG_HWCONFIG
CONFIG_HW_ENV_SETTINGS
@@ -262,7 +120,6 @@
CONFIG_L1_INIT_RAM
CONFIG_L2_CACHE
CONFIG_LEGACY_BOOTCMD_ENV
-CONFIG_LOADS_ECHO
CONFIG_LOWPOWER_ADDR
CONFIG_LOWPOWER_FLAG
CONFIG_LPC32XX_HSUART
@@ -382,7 +239,6 @@
CONFIG_RTC_DS1374
CONFIG_RTC_DS3231
CONFIG_RTC_MC13XXX
-CONFIG_RTC_MCFRRTC
CONFIG_RTC_MXS
CONFIG_RTC_PT7C4338
CONFIG_SANDBOX_ARCH
@@ -661,111 +517,6 @@
CONFIG_SYS_FPGA_FTIM3
CONFIG_SYS_FPGA_SIZE
CONFIG_SYS_FPGA_WAIT
-CONFIG_SYS_FSL_BMAN_ADDR
-CONFIG_SYS_FSL_BMAN_OFFSET
-CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
-CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
-CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
-CONFIG_SYS_FSL_CLK_ADDR
-CONFIG_SYS_FSL_CLUSTER_1_L2
-CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
-CONFIG_SYS_FSL_CLUSTER_CLOCKS
-CONFIG_SYS_FSL_CORENET_CCM_ADDR
-CONFIG_SYS_FSL_CORENET_CCM_OFFSET
-CONFIG_SYS_FSL_CORENET_CLK_ADDR
-CONFIG_SYS_FSL_CORENET_CLK_OFFSET
-CONFIG_SYS_FSL_CORENET_PMAN
-CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET
-CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET
-CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET
-CONFIG_SYS_FSL_CORENET_PME_ADDR
-CONFIG_SYS_FSL_CORENET_PME_OFFSET
-CONFIG_SYS_FSL_CORENET_RCPM_ADDR
-CONFIG_SYS_FSL_CORENET_RCPM_OFFSET
-CONFIG_SYS_FSL_CORENET_RMAN_ADDR
-CONFIG_SYS_FSL_CORENET_RMAN_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES3_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES4_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
-CONFIG_SYS_FSL_CORENET_SERDES_ADDR
-CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
-CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
-CONFIG_SYS_FSL_CPC_ADDR
-CONFIG_SYS_FSL_CPC_OFFSET
-CONFIG_SYS_FSL_CSU_ADDR
-CONFIG_SYS_FSL_DCSR_DDR2_ADDR
-CONFIG_SYS_FSL_DCSR_DDR3_ADDR
-CONFIG_SYS_FSL_DCSR_DDR_ADDR
-CONFIG_SYS_FSL_DDR2_ADDR
-CONFIG_SYS_FSL_DDR3_ADDR
-CONFIG_SYS_FSL_DDR_ADDR
-CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
-CONFIG_SYS_FSL_ESDHC_ADDR
-CONFIG_SYS_FSL_FM
-CONFIG_SYS_FSL_FM1_ADDR
-CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
-CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
-CONFIG_SYS_FSL_FM1_OFFSET
-CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET
-CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET
-CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
-CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
-CONFIG_SYS_FSL_FM2_ADDR
-CONFIG_SYS_FSL_FM2_OFFSET
-CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET
-CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET
-CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
-CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
-CONFIG_SYS_FSL_GUTS_ADDR
-CONFIG_SYS_FSL_JR0_ADDR
-CONFIG_SYS_FSL_JR0_OFFSET
-CONFIG_SYS_FSL_LS1_CLK_ADDR
-CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
-CONFIG_SYS_FSL_NUM_CC_PLL
-CONFIG_SYS_FSL_OCRAM_BASE
-CONFIG_SYS_FSL_OCRAM_SIZE
-CONFIG_SYS_FSL_PAMU_OFFSET
-CONFIG_SYS_FSL_PMIC_I2C_ADDR
-CONFIG_SYS_FSL_PMU_ADDR
-CONFIG_SYS_FSL_PMU_CLTBENR
-CONFIG_SYS_FSL_QMAN_ADDR
-CONFIG_SYS_FSL_QMAN_OFFSET
-CONFIG_SYS_FSL_QSPI_BASE
-CONFIG_SYS_FSL_RAID_ENGINE_ADDR
-CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
-CONFIG_SYS_FSL_RCPM_ADDR
-CONFIG_SYS_FSL_RST_ADDR
-CONFIG_SYS_FSL_SCFG_ADDR
-CONFIG_SYS_FSL_SCFG_OFFSET
-CONFIG_SYS_FSL_SEC_ADDR
-CONFIG_SYS_FSL_SEC_IDX_OFFSET
-CONFIG_SYS_FSL_SEC_OFFSET
-CONFIG_SYS_FSL_SERDES
-CONFIG_SYS_FSL_SERDES_ADDR
-CONFIG_SYS_FSL_SRDS_3
-CONFIG_SYS_FSL_SRDS_4
-CONFIG_SYS_FSL_SRIO_ADDR
-CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
-CONFIG_SYS_FSL_SRIO_MAX_PORTS
-CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
-CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
-CONFIG_SYS_FSL_SRIO_OFFSET
-CONFIG_SYS_FSL_TIMER_ADDR
-CONFIG_SYS_FSL_USDHC_NUM
-CONFIG_SYS_FSL_WRIOP1_ADDR
-CONFIG_SYS_FSL_WRIOP1_MDIO1
-CONFIG_SYS_FSL_WRIOP1_MDIO2
CONFIG_SYS_GPIO1_EN
CONFIG_SYS_GPIO1_FUNC
CONFIG_SYS_GPIO1_LED
@@ -780,7 +531,6 @@
CONFIG_SYS_I2C_FPGA_ADDR
CONFIG_SYS_I2C_G762_ADDR
CONFIG_SYS_I2C_IFDR_DIV
-CONFIG_SYS_I2C_INIT_BOARD
CONFIG_SYS_I2C_MAX_HOPS
CONFIG_SYS_I2C_NOPROBES
CONFIG_SYS_I2C_PCA953X_ADDR
@@ -802,32 +552,21 @@
CONFIG_SYS_INIT_L2_END
CONFIG_SYS_INIT_L3_ADDR
CONFIG_SYS_INIT_L3_ADDR_PHYS
-CONFIG_SYS_INIT_L3_END
CONFIG_SYS_INIT_L3_VADDR
CONFIG_SYS_INIT_RAM_ADDR
CONFIG_SYS_INIT_RAM_ADDR_PHYS
CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
CONFIG_SYS_INIT_RAM_CTRL
-CONFIG_SYS_INIT_RAM_LOCK
CONFIG_SYS_INIT_RAM_SIZE
CONFIG_SYS_INIT_SP_OFFSET
-CONFIG_SYS_INTERLAKEN
CONFIG_SYS_INT_FLASH_BASE
CONFIG_SYS_INT_FLASH_ENABLE
CONFIG_SYS_IO_BASE
-CONFIG_SYS_ISA_IO
-CONFIG_SYS_ISA_IO_BASE_ADDRESS
-CONFIG_SYS_JFFS2_FIRST_BANK
-CONFIG_SYS_JFFS2_FIRST_SECTOR
-CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE
-CONFIG_SYS_L2_SIZE
-CONFIG_SYS_L3_SIZE
CONFIG_SYS_LATCH_ADDR
CONFIG_SYS_LBC_ADDR
-CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LBC_FLASH_BASE
CONFIG_SYS_LBC_LBCR
CONFIG_SYS_LBC_LCRR
@@ -839,8 +578,6 @@
CONFIG_SYS_LBC_SDRAM_SIZE
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LIME_BASE
-CONFIG_SYS_LIME_SIZE
-CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_SYS_LOW
CONFIG_SYS_LOWMEM_BASE
CONFIG_SYS_LPAE_SDRAM_BASE
@@ -852,18 +589,14 @@
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
-CONFIG_SYS_M41T11_BASE_YEAR
CONFIG_SYS_MAIN_PWR_ON
-CONFIG_SYS_MAMR
CONFIG_SYS_MASTER_CLOCK
CONFIG_SYS_MATRIX_EBI0CSA_VAL
CONFIG_SYS_MATRIX_EBICSA_VAL
CONFIG_SYS_MAX_I2C_BUS
CONFIG_SYS_MAX_NAND_CHIPS
-CONFIG_SYS_MAX_NAND_DEVICE
CONFIG_SYS_MBAR
CONFIG_SYS_MBAR2
-CONFIG_SYS_MCFRRTC_BASE
CONFIG_SYS_MCKR
CONFIG_SYS_MCKR1_VAL
CONFIG_SYS_MCKR2_VAL
@@ -874,79 +607,12 @@
CONFIG_SYS_MFD
CONFIG_SYS_MMC_CD_PIN
CONFIG_SYS_MMC_CLK_OD
-CONFIG_SYS_MMC_MAX_BLK_COUNT
-CONFIG_SYS_MMC_MAX_DEVICE
CONFIG_SYS_MMC_U_BOOT_DST
CONFIG_SYS_MMC_U_BOOT_OFFS
CONFIG_SYS_MMC_U_BOOT_SIZE
CONFIG_SYS_MMC_U_BOOT_START
-CONFIG_SYS_MONITOR_LEN
-CONFIG_SYS_MONITOR_SEC
CONFIG_SYS_MOR_VAL
-CONFIG_SYS_MPC83xx_DMA_ADDR
-CONFIG_SYS_MPC83xx_DMA_OFFSET
-CONFIG_SYS_MPC83xx_ESDHC_ADDR
-CONFIG_SYS_MPC83xx_ESDHC_OFFSET
-CONFIG_SYS_MPC85xx_DMA
-CONFIG_SYS_MPC85xx_DMA1_OFFSET
-CONFIG_SYS_MPC85xx_DMA2_OFFSET
-CONFIG_SYS_MPC85xx_DMA3_OFFSET
-CONFIG_SYS_MPC85xx_DMA_ADDR
-CONFIG_SYS_MPC85xx_DMA_OFFSET
-CONFIG_SYS_MPC85xx_ECM_ADDR
-CONFIG_SYS_MPC85xx_ECM_OFFSET
-CONFIG_SYS_MPC85xx_ESDHC_ADDR
-CONFIG_SYS_MPC85xx_ESDHC_OFFSET
-CONFIG_SYS_MPC85xx_ESPI_ADDR
-CONFIG_SYS_MPC85xx_ESPI_OFFSET
-CONFIG_SYS_MPC85xx_GPIO_ADDR
-CONFIG_SYS_MPC85xx_GPIO_OFFSET
-CONFIG_SYS_MPC85xx_GUTS_ADDR
-CONFIG_SYS_MPC85xx_GUTS_OFFSET
-CONFIG_SYS_MPC85xx_IFC_OFFSET
-CONFIG_SYS_MPC85xx_L2_ADDR
-CONFIG_SYS_MPC85xx_L2_OFFSET
-CONFIG_SYS_MPC85xx_LBC_OFFSET
-CONFIG_SYS_MPC85xx_PCI1_OFFSET
-CONFIG_SYS_MPC85xx_PCI2_OFFSET
-CONFIG_SYS_MPC85xx_PCIE
-CONFIG_SYS_MPC85xx_PCIE1_OFFSET
-CONFIG_SYS_MPC85xx_PCIE2_OFFSET
-CONFIG_SYS_MPC85xx_PCIE3_OFFSET
-CONFIG_SYS_MPC85xx_PCIE4_OFFSET
-CONFIG_SYS_MPC85xx_PCIX2_ADDR
-CONFIG_SYS_MPC85xx_PCIX2_OFFSET
-CONFIG_SYS_MPC85xx_PCIX_ADDR
-CONFIG_SYS_MPC85xx_PCIX_OFFSET
-CONFIG_SYS_MPC85xx_PIC_OFFSET
-CONFIG_SYS_MPC85xx_QE_OFFSET
-CONFIG_SYS_MPC85xx_SATA
-CONFIG_SYS_MPC85xx_SATA1_ADDR
-CONFIG_SYS_MPC85xx_SATA1_OFFSET
-CONFIG_SYS_MPC85xx_SATA2_ADDR
-CONFIG_SYS_MPC85xx_SATA2_OFFSET
-CONFIG_SYS_MPC85xx_SCFG
-CONFIG_SYS_MPC85xx_SCFG_OFFSET
-CONFIG_SYS_MPC85xx_SERDES1_ADDR
-CONFIG_SYS_MPC85xx_SERDES1_OFFSET
-CONFIG_SYS_MPC85xx_SERDES2_ADDR
-CONFIG_SYS_MPC85xx_SERDES2_OFFSET
-CONFIG_SYS_MPC85xx_TDM_OFFSET
-CONFIG_SYS_MPC85xx_USB
-CONFIG_SYS_MPC85xx_USB1_ADDR
-CONFIG_SYS_MPC85xx_USB1_OFFSET
-CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
-CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET
-CONFIG_SYS_MPC85xx_USB2_ADDR
-CONFIG_SYS_MPC85xx_USB2_OFFSET
-CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
-CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET
-CONFIG_SYS_MPC8xxx_DDR2_OFFSET
-CONFIG_SYS_MPC8xxx_DDR3_OFFSET
-CONFIG_SYS_MPC8xxx_DDR_OFFSET
-CONFIG_SYS_MPC8xxx_PIC_ADDR
CONFIG_SYS_MRAM_BASE
-CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
CONFIG_SYS_NAND_AMASK
CONFIG_SYS_NAND_BASE
CONFIG_SYS_NAND_BASE2
@@ -991,7 +657,6 @@
CONFIG_SYS_NAND_U_BOOT_RELOC_SP
CONFIG_SYS_NAND_U_BOOT_SIZE
CONFIG_SYS_NAND_U_BOOT_START
-CONFIG_SYS_NONCACHED_MEMORY
CONFIG_SYS_NOR0_CSPR
CONFIG_SYS_NOR0_CSPR_EARLY
CONFIG_SYS_NOR0_CSPR_EXT
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index beebd5c..2736582 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -14,10 +14,14 @@
static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
+static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
+
int cmd_ut_category(const char *name, const char *prefix,
struct unit_test *tests, int n_ents,
int argc, char *const argv[])
{
+ const char *test_insert = NULL;
int runs_per_text = 1;
bool force_run = false;
int ret;
@@ -32,19 +36,24 @@
case 'f':
force_run = true;
break;
+ case 'I':
+ test_insert = str + 2;
+ break;
}
argv++;
- argc++;
+ argc--;
}
ret = ut_run_list(name, prefix, tests, n_ents,
- argc > 1 ? argv[1] : NULL, runs_per_text, force_run);
+ argc > 1 ? argv[1] : NULL, runs_per_text, force_run,
+ test_insert);
return ret ? CMD_RET_FAILURE : 0;
}
static struct cmd_tbl cmd_ut_sub[] = {
U_BOOT_CMD_MKENT(all, CONFIG_SYS_MAXARGS, 1, do_ut_all, "", ""),
+ U_BOOT_CMD_MKENT(info, 1, 1, do_ut_info, "", ""),
#ifdef CONFIG_BOOTSTD
U_BOOT_CMD_MKENT(bootstd, CONFIG_SYS_MAXARGS, 1, do_ut_bootstd,
"", ""),
@@ -119,6 +128,15 @@
return any_fail;
}
+static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ printf("Test suites: %d\n", (int)ARRAY_SIZE(cmd_ut_sub));
+ printf("Total tests: %d\n", (int)UNIT_TEST_ALL_COUNT());
+
+ return 0;
+}
+
static int do_ut(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct cmd_tbl *cp;
@@ -140,59 +158,67 @@
#ifdef CONFIG_SYS_LONGHELP
static char ut_help_text[] =
- "all - execute all enabled tests\n"
+ "[-r] [-f] [<suite>] - run unit tests\n"
+ " -r<runs> Number of times to run each test\n"
+ " -f Force 'manual' tests to run as well\n"
+ " <suite> Test suite to run, or all\n"
+ "\n"
+ "\nOptions for <suite>:"
+ "\nall - execute all enabled tests"
+ "\ninfo - show info about tests"
+#ifdef CONFIG_CMD_ADDRMAP
+ "\naddrmap - very basic test of addrmap command"
+#endif
#ifdef CONFIG_SANDBOX
- "ut bloblist - Test bloblist implementation\n"
- "ut compression - Test compressors and bootm decompression\n"
+ "\nbloblist - bloblist implementation"
#endif
#ifdef CONFIG_BOOTSTD
- "ut bootstd - Test standard boot implementation\n"
+ "\nbootstd - standard boot implementation"
+#endif
+#ifdef CONFIG_SANDBOX
+ "\ncompression - compressors and bootm decompression"
#endif
#ifdef CONFIG_UT_DM
- "ut dm [test-name]\n"
+ "\ndm - driver model"
#endif
#ifdef CONFIG_UT_ENV
- "ut env [test-name]\n"
+ "\nenv - environment"
#endif
#ifdef CONFIG_CMD_FDT
- "ut fdt [test-name] - test of the fdt command\n"
+ "\nfdt - fdt command"
#endif
#ifdef CONFIG_CONSOLE_TRUETYPE
- "ut font [test-name] - test of the font command\n"
+ "\nut font - font command\n"
+#endif
+#ifdef CONFIG_CMD_LOADM
+ "\nloadm - loadm command parameters and loading memory blob"
#endif
#ifdef CONFIG_UT_LIB
- "ut lib [test-name] - test library functions\n"
+ "\nlib - library functions"
#endif
#ifdef CONFIG_UT_LOG
- "ut log [test-name] - test logging functions\n"
+ "\nlog - logging functions"
#endif
- "ut mem [test-name] - test memory-related commands\n"
+ "\nmem - memory-related commands"
#ifdef CONFIG_UT_OPTEE
- "ut optee [test-name]\n"
+ "\noptee - test OP-TEE"
#endif
#ifdef CONFIG_UT_OVERLAY
- "ut overlay [test-name]\n"
+ "\noverlay - device tree overlays"
#endif
- "ut print [test-name] - test printing\n"
- "ut setexpr [test-name] - test setexpr command\n"
+ "\nprint - printing things to the console"
+ "\nsetexpr - setexpr command"
#ifdef CONFIG_SANDBOX
- "ut str - Basic test of string functions\n"
+ "\nstr - basic test of string functions"
#endif
#ifdef CONFIG_UT_TIME
- "ut time - Very basic test of time functions\n"
+ "\ntime - very basic test of time functions"
#endif
#if defined(CONFIG_UT_UNICODE) && \
!defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
- "ut unicode [test-name] - test Unicode functions\n"
-#endif
-#ifdef CONFIG_CMD_ADDRMAP
- "ut addrmap - Very basic test of addrmap command\n"
-#endif
-#ifdef CONFIG_CMD_LOADM
- "ut loadm [test-name]- test of parameters and load memory blob\n"
+ "\nunicode - Unicode functions"
#endif
- "All commands accept an optional [-r<runs>] flag before [test-name], to\n"
- "run each test multiple times (<runs> is in decimal)";
+ ;
#endif /* CONFIG_SYS_LONGHELP */
U_BOOT_CMD(
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 1901f22..7a79b6e 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -49,6 +49,7 @@
obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_FPGA) += fpga.o
obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_mdata.o
+obj-$(CONFIG_SANDBOX) += host.o
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_SOUND) += i2s.o
diff --git a/test/dm/blk.c b/test/dm/blk.c
index 35bd531..612f3ff 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <dm.h>
#include <part.h>
+#include <sandbox_host.h>
#include <usb.h>
#include <asm/global_data.h>
#include <asm/state.h>
@@ -21,26 +22,27 @@
/* Test that block devices can be created */
static int dm_test_blk_base(struct unit_test_state *uts)
{
- struct udevice *blk1, *blk3, *dev;
+ struct udevice *blk0, *blk1, *dev0, *dev1, *dev, *chk0, *chk1;
/* Create two, one the parent of the other */
- ut_assertok(blk_create_device(gd->dm_root, "sandbox_host_blk", "test",
- UCLASS_ROOT, 1, 512, 2, &blk1));
- ut_assertok(blk_create_device(blk1, "sandbox_host_blk", "test",
- UCLASS_ROOT, 3, 512, 2, &blk3));
+ ut_assertok(host_create_device("test0", false, &dev0));
+ ut_assertok(host_create_device("test1", false, &dev1));
/* Check we can find them */
- ut_asserteq(-ENODEV, blk_get_device(UCLASS_ROOT, 0, &dev));
- ut_assertok(blk_get_device(UCLASS_ROOT, 1, &dev));
- ut_asserteq_ptr(blk1, dev);
- ut_assertok(blk_get_device(UCLASS_ROOT, 3, &dev));
- ut_asserteq_ptr(blk3, dev);
+ ut_assertok(blk_get_device(UCLASS_HOST, 0, &blk0));
+ ut_assertok(blk_get_from_parent(dev0, &chk0));
+ ut_asserteq_ptr(blk0, chk0);
+
+ ut_assertok(blk_get_device(UCLASS_HOST, 1, &blk1));
+ ut_assertok(blk_get_from_parent(dev1, &chk1));
+ ut_asserteq_ptr(blk1, chk1);
+ ut_asserteq(-ENODEV, blk_get_device(UCLASS_HOST, 2, &dev0));
/* Check we can iterate */
- ut_assertok(blk_first_device(UCLASS_ROOT, &dev));
- ut_asserteq_ptr(blk1, dev);
+ ut_assertok(blk_first_device(UCLASS_HOST, &dev));
+ ut_asserteq_ptr(blk0, dev);
ut_assertok(blk_next_device(&dev));
- ut_asserteq_ptr(blk3, dev);
+ ut_asserteq_ptr(blk1, dev);
return 0;
}
@@ -98,19 +100,20 @@
/* Test that we can find block devices without probing them */
static int dm_test_blk_find(struct unit_test_state *uts)
{
- struct udevice *blk, *dev;
+ struct udevice *blk, *chk, *dev;
- ut_assertok(blk_create_device(gd->dm_root, "sandbox_host_blk", "test",
- UCLASS_ROOT, 1, 512, 2, &blk));
- ut_asserteq(-ENODEV, blk_find_device(UCLASS_ROOT, 0, &dev));
- ut_assertok(blk_find_device(UCLASS_ROOT, 1, &dev));
- ut_asserteq_ptr(blk, dev);
+ ut_assertok(host_create_device("test0", false, &dev));
+
+ ut_assertok(blk_find_device(UCLASS_HOST, 0, &chk));
+ ut_assertok(device_find_first_child_by_uclass(dev, UCLASS_BLK, &blk));
+ ut_asserteq_ptr(chk, blk);
ut_asserteq(false, device_active(dev));
+ ut_asserteq(-ENODEV, blk_find_device(UCLASS_HOST, 1, &dev));
/* Now activate it */
- ut_assertok(blk_get_device(UCLASS_ROOT, 1, &dev));
- ut_asserteq_ptr(blk, dev);
- ut_asserteq(true, device_active(dev));
+ ut_assertok(blk_get_device(UCLASS_HOST, 0, &blk));
+ ut_asserteq_ptr(chk, blk);
+ ut_asserteq(true, device_active(blk));
return 0;
}
@@ -160,7 +163,7 @@
ut_assertok(blk_get_from_parent(dev, &blk));
ut_assertok(uclass_get_device(UCLASS_I2C, 0, &dev));
- ut_asserteq(-ENOTBLK, blk_get_from_parent(dev, &blk));
+ ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk));
ut_assertok(uclass_get_device(UCLASS_GPIO, 0, &dev));
ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk));
diff --git a/test/dm/host.c b/test/dm/host.c
new file mode 100644
index 0000000..4dafc24
--- /dev/null
+++ b/test/dm/host.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright 2022 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <dm.h>
+#include <fs.h>
+#include <sandbox_host.h>
+#include <asm/test.h>
+#include <dm/device-internal.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static const char filename[] = "2MB.ext2.img";
+static const char filename2[] = "1MB.fat32.img";
+
+/* Basic test of host interface */
+static int dm_test_host(struct unit_test_state *uts)
+{
+ static char label[] = "test";
+ struct udevice *dev, *part, *chk, *blk;
+ struct host_sb_plat *plat;
+ struct blk_desc *desc;
+ ulong mem_start;
+ loff_t actwrite;
+
+ ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_HOST, &dev));
+ ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_PARTITION, &part));
+
+ mem_start = ut_check_delta(0);
+ ut_assertok(host_create_device(label, true, &dev));
+
+ /* Check that the plat data has been allocated */
+ plat = dev_get_plat(dev);
+ ut_asserteq_str("test", plat->label);
+ ut_assert(label != plat->label);
+ ut_asserteq(0, plat->fd);
+
+ /* Attach a file created in test_host.py */
+ ut_assertok(host_attach_file(dev, filename));
+ ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
+ ut_asserteq_ptr(chk, dev);
+
+ ut_asserteq_str(filename, plat->filename);
+ ut_assert(filename != plat->filename);
+ ut_assert(plat->fd != 0);
+
+ /* Get the block device */
+ ut_assertok(blk_get_from_parent(dev, &blk));
+ ut_assertok(device_probe(blk));
+
+ /* There should be no partition table in this device */
+ ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_PARTITION, &part));
+
+ /* Write to a file on the ext4 filesystem */
+ desc = dev_get_uclass_plat(blk);
+ ut_asserteq(true, desc->removable);
+ ut_assertok(fs_set_blk_dev_with_part(desc, 0));
+ ut_assertok(fs_write("/testing", 0, 0, 0x1000, &actwrite));
+
+ ut_assertok(host_detach_file(dev));
+ ut_asserteq(0, plat->fd);
+ ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk));
+ ut_assertok(device_unbind(dev));
+
+ /* check there were no memory leaks */
+ ut_asserteq(0, ut_check_delta(mem_start));
+
+ return 0;
+}
+DM_TEST(dm_test_host, UT_TESTF_SCAN_FDT);
+
+/* reusing the same label should work */
+static int dm_test_host_dup(struct unit_test_state *uts)
+{
+ static char label[] = "test";
+ struct udevice *dev, *chk;
+
+ ut_asserteq(0, uclass_id_count(UCLASS_HOST));
+ ut_assertok(host_create_device(label, true, &dev));
+
+ /* Attach a file created in test_host.py */
+ ut_assertok(host_attach_file(dev, filename));
+ ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
+ ut_asserteq_ptr(chk, dev);
+ ut_asserteq(1, uclass_id_count(UCLASS_HOST));
+
+ /* Create another device with the same label (should remove old one) */
+ ut_assertok(host_create_device(label, true, &dev));
+
+ /* Attach a different file created in test_host.py */
+ ut_assertok(host_attach_file(dev, filename2));
+ ut_assertok(uclass_first_device_err(UCLASS_HOST, &chk));
+ ut_asserteq_ptr(chk, dev);
+
+ /* Make sure there is still only one device */
+ ut_asserteq(1, uclass_id_count(UCLASS_HOST));
+
+ return 0;
+}
+DM_TEST(dm_test_host_dup, UT_TESTF_SCAN_FDT);
+
+/* Basic test of 'host' command */
+static int dm_test_cmd_host(struct unit_test_state *uts)
+{
+ struct udevice *dev, *blk;
+ struct blk_desc *desc;
+
+ console_record_reset();
+
+ /* first check 'host info' with binding */
+ ut_assertok(run_command("host info", 0));
+ ut_assert_nextline("dev blocks label path");
+ ut_assert_console_end();
+
+ ut_assertok(run_commandf("host bind -r test2 %s", filename));
+
+ /* Check the -r flag worked */
+ ut_assertok(uclass_first_device_err(UCLASS_HOST, &dev));
+ ut_assertok(blk_get_from_parent(dev, &blk));
+ desc = dev_get_uclass_plat(blk);
+ ut_asserteq(true, desc->removable);
+
+ ut_assertok(run_command("host info", 0));
+ ut_assert_nextline("dev blocks label path");
+ ut_assert_nextline(" 0 4096 test2 2MB.ext2.img");
+ ut_assert_console_end();
+
+ ut_assertok(run_commandf("host bind fat %s", filename2));
+
+ /* Check it is not removeable (no '-r') */
+ ut_assertok(uclass_next_device_err(&dev));
+ ut_assertok(blk_get_from_parent(dev, &blk));
+ desc = dev_get_uclass_plat(blk);
+ ut_asserteq(false, desc->removable);
+
+ ut_assertok(run_command("host info", 0));
+ ut_assert_nextline("dev blocks label path");
+ ut_assert_nextline(" 0 4096 test2 2MB.ext2.img");
+ ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("host info test", 0));
+ ut_assert_nextline("No such device 'test'");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("host info fat", 0));
+ ut_assert_nextline("dev blocks label path");
+ ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_console_end();
+
+ /* check 'host dev' */
+ ut_asserteq(1, run_command("host dev", 0));
+ ut_assert_nextline("No current host device");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("host dev missing", 0));
+ ut_assert_nextline("No such device 'missing'");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("host dev fat", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("host dev", 0));
+ ut_assert_nextline("Current host device: 1: fat");
+ ut_assert_console_end();
+
+ /* Try a numerical label */
+ ut_assertok(run_command("host dev 0", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("host dev", 0));
+ ut_assert_nextline("Current host device: 0: test2");
+ ut_assert_console_end();
+
+ /* Remove one of the bindings */
+ ut_assertok(run_commandf("host unbind test2"));
+
+ /* There should now be no current device */
+ ut_asserteq(1, run_command("host dev", 0));
+ ut_assert_nextline("No current host device");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("host info", 0));
+ ut_assert_nextline("dev blocks label path");
+ ut_assert_nextline(" 1 2048 fat 1MB.fat32.img");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_cmd_host, UT_TESTF_SCAN_FDT);
diff --git a/test/dm/test-dm.c b/test/dm/test-dm.c
index 66cc2bc..e73a1dd 100644
--- a/test/dm/test-dm.c
+++ b/test/dm/test-dm.c
@@ -4,55 +4,14 @@
*/
#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <dm.h>
-#include <errno.h>
-#include <log.h>
-#include <malloc.h>
-#include <asm/global_data.h>
-#include <asm/state.h>
-#include <dm/root.h>
-#include <dm/uclass-internal.h>
+#include <test/suites.h>
#include <test/test.h>
-#include <test/test.h>
-#include <test/ut.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-/**
- * dm_test_run() - Run driver model tests
- *
- * Run all the available driver model tests, or a selection
- *
- * @test_name: Name of single test to run (e.g. "dm_test_fdt_pre_reloc" or just
- * "fdt_pre_reloc"), or NULL to run all
- * Return: 0 if all tests passed, 1 if not
- */
-static int dm_test_run(const char *test_name, int runs_per_text)
+int do_ut_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct unit_test *tests = UNIT_TEST_SUITE_START(dm_test);
const int n_ents = UNIT_TEST_SUITE_COUNT(dm_test);
- int ret;
-
- ret = ut_run_list("driver model", "dm_test_", tests, n_ents, test_name,
- runs_per_text, false);
-
- return ret ? CMD_RET_FAILURE : 0;
-}
-
-int do_ut_dm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- const char *test_name = NULL;
- int runs_per_text = 1;
-
- if (argc > 1 && !strncmp("-r", argv[1], 2)) {
- runs_per_text = dectoul(argv[1] + 2, NULL);
- argv++;
- argc++;
- }
- if (argc > 1)
- test_name = argv[1];
- return dm_test_run(test_name, runs_per_text);
+ return cmd_ut_category("driver model", "dm_test_", tests, n_ents, argc,
+ argv);
}
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
new file mode 100644
index 0000000..17151bc
--- /dev/null
+++ b/test/py/tests/fs_helper.py
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2018, Linaro Limited
+# Author: Takahiro Akashi <takahiro.akashi@linaro.org>
+
+"""Helper functions for dealing with filesystems"""
+
+import re
+import os
+from subprocess import call, check_call, check_output, CalledProcessError
+
+def mk_fs(config, fs_type, size, prefix, use_src_dir=False):
+ """Create a file system volume
+
+ Args:
+ config (u_boot_config): U-Boot configuration
+ fs_type (str): File system type, e.g. 'ext4'
+ size (int): Size of file system in bytes
+ prefix (str): Prefix string of volume's file name
+ use_src_dir (bool): true to put the file in the source directory
+
+ Raises:
+ CalledProcessError: if any error occurs when creating the filesystem
+ """
+ fs_img = f'{prefix}.{fs_type}.img'
+ fs_img = os.path.join(config.source_dir if use_src_dir
+ else config.persistent_data_dir, fs_img)
+
+ if fs_type == 'fat16':
+ mkfs_opt = '-F 16'
+ elif fs_type == 'fat32':
+ mkfs_opt = '-F 32'
+ else:
+ mkfs_opt = ''
+
+ if re.match('fat', fs_type):
+ fs_lnxtype = 'vfat'
+ else:
+ fs_lnxtype = fs_type
+
+ count = (size + 0x100000 - 1) // 0x100000
+
+ # Some distributions do not add /sbin to the default PATH, where mkfs lives
+ if '/sbin' not in os.environ["PATH"].split(os.pathsep):
+ os.environ["PATH"] += os.pathsep + '/sbin'
+
+ try:
+ check_call(f'rm -f {fs_img}', shell=True)
+ check_call(f'dd if=/dev/zero of={fs_img} bs=1M count={count}',
+ shell=True)
+ check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True)
+ if fs_type == 'ext4':
+ sb_content = check_output(f'tune2fs -l {fs_img}',
+ shell=True).decode()
+ if 'metadata_csum' in sb_content:
+ check_call(f'tune2fs -O ^metadata_csum {fs_img}', shell=True)
+ return fs_img
+ except CalledProcessError:
+ call(f'rm -f {fs_img}', shell=True)
+ raise
+
+# Just for trying out
+if __name__ == "__main__":
+ import collections
+
+ CNF= collections.namedtuple('config', 'persistent_data_dir')
+
+ mk_fs(CNF('.'), 'ext4', 0x1000000, 'pref')
diff --git a/test/py/tests/test_eficonfig/test_eficonfig.py b/test/py/tests/test_eficonfig/test_eficonfig.py
index 99606d9..3859a77 100644
--- a/test/py/tests/test_eficonfig/test_eficonfig.py
+++ b/test/py/tests/test_eficonfig/test_eficonfig.py
@@ -64,6 +64,9 @@
initrddump.efi
"""
+ # This test passes for unknown reasons in the bowels of U-Boot. It needs to
+ # be replaced with a unit test.
+ return
# Restart the system to clean the previous state
u_boot_console.restart_uboot()
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index b638284..9329ec6 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -9,6 +9,7 @@
from subprocess import call, check_call, check_output, CalledProcessError
from fstest_defs import *
import u_boot_utils as util
+from tests import fs_helper
supported_fs_basic = ['fat16', 'fat32', 'ext4']
supported_fs_ext = ['fat16', 'fat32']
@@ -132,53 +133,6 @@
pytest.skip('.config feature "%s_WRITE" not enabled'
% fs_type.upper())
-def mk_fs(config, fs_type, size, id):
- """Create a file system volume.
-
- Args:
- fs_type: File system type.
- size: Size of file system in MiB.
- id: Prefix string of volume's file name.
-
- Return:
- Nothing.
- """
- fs_img = '%s.%s.img' % (id, fs_type)
- fs_img = config.persistent_data_dir + '/' + fs_img
-
- if fs_type == 'fat16':
- mkfs_opt = '-F 16'
- elif fs_type == 'fat32':
- mkfs_opt = '-F 32'
- else:
- mkfs_opt = ''
-
- if re.match('fat', fs_type):
- fs_lnxtype = 'vfat'
- else:
- fs_lnxtype = fs_type
-
- count = (size + 1048576 - 1) / 1048576
-
- # Some distributions do not add /sbin to the default PATH, where mkfs lives
- if '/sbin' not in os.environ["PATH"].split(os.pathsep):
- os.environ["PATH"] += os.pathsep + '/sbin'
-
- try:
- check_call('rm -f %s' % fs_img, shell=True)
- check_call('dd if=/dev/zero of=%s bs=1M count=%d'
- % (fs_img, count), shell=True)
- check_call('mkfs.%s %s %s'
- % (fs_lnxtype, mkfs_opt, fs_img), shell=True)
- if fs_type == 'ext4':
- sb_content = check_output('tune2fs -l %s' % fs_img, shell=True).decode()
- if 'metadata_csum' in sb_content:
- check_call('tune2fs -O ^metadata_csum %s' % fs_img, shell=True)
- return fs_img
- except CalledProcessError:
- call('rm -f %s' % fs_img, shell=True)
- raise
-
# from test/py/conftest.py
def tool_is_in_path(tool):
"""Check whether a given command is available on host.
@@ -283,7 +237,7 @@
try:
# 3GiB volume
- fs_img = mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB')
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0xc0000000, '3GB')
except CalledProcessError as err:
pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
return
@@ -405,7 +359,7 @@
try:
# 128MiB volume
- fs_img = mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
except CalledProcessError as err:
pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
return
@@ -500,7 +454,7 @@
try:
# 128MiB volume
- fs_img = mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
except:
pytest.skip('Setup failed for filesystem: ' + fs_type)
return
@@ -534,7 +488,7 @@
try:
# 128MiB volume
- fs_img = mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB')
except CalledProcessError as err:
pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
return
@@ -617,7 +571,7 @@
try:
# 1GiB volume
- fs_img = mk_fs(u_boot_config, fs_type, 0x40000000, '1GB')
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x40000000, '1GB')
except CalledProcessError as err:
pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
return
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 9d42390..bab8b97 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -7,6 +7,7 @@
import pytest
import u_boot_utils
+from tests import fs_helper
def mkdir_cond(dirname):
"""Create a directory if it doesn't already exist
@@ -123,6 +124,11 @@
u_boot_utils.run_and_log(
u_boot_console, f'sfdisk {fn}', stdin=b'type=83')
+ fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB',
+ use_src_dir=True)
+ fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB',
+ use_src_dir=True)
+
@pytest.mark.buildconfigspec('cmd_bootflow')
def test_ut_dm_init_bootstd(u_boot_console):
"""Initialise data for bootflow tests"""
diff --git a/test/test-main.c b/test/test-main.c
index fe3ef6d..5931e94 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <blk.h>
#include <console.h>
#include <cyclic.h>
#include <dm.h>
@@ -352,6 +353,8 @@
free(uts->of_other);
uts->of_other = NULL;
+ blkcache_free();
+
return 0;
}
@@ -428,12 +431,11 @@
* the first call to this function. On exit, @uts->fail_count is
* incremented by the number of failures (0, one hopes)
* @test: Test to run
- * @name: Name of test, possibly skipping a prefix that should not be displayed
* Return: 0 if all tests passed, -EAGAIN if the test should be skipped, -1 if
* any failed
*/
static int ut_run_test_live_flat(struct unit_test_state *uts,
- struct unit_test *test, const char *name)
+ struct unit_test *test)
{
int runs;
@@ -496,12 +498,29 @@
*/
static int ut_run_tests(struct unit_test_state *uts, const char *prefix,
struct unit_test *tests, int count,
- const char *select_name)
+ const char *select_name, const char *test_insert)
{
- struct unit_test *test;
+ struct unit_test *test, *one;
int found = 0;
+ int pos = 0;
+ int upto;
- for (test = tests; test < tests + count; test++) {
+ one = NULL;
+ if (test_insert) {
+ char *p;
+
+ pos = dectoul(test_insert, NULL);
+ p = strchr(test_insert, ':');
+ if (p)
+ p++;
+
+ for (test = tests; test < tests + count; test++) {
+ if (!strcmp(p, test->name))
+ one = test;
+ }
+ }
+
+ for (upto = 0, test = tests; test < tests + count; test++, upto++) {
const char *test_name = test->name;
int ret, i, old_fail_count;
@@ -532,8 +551,19 @@
}
}
old_fail_count = uts->fail_count;
+
+ if (one && upto == pos) {
+ ret = ut_run_test_live_flat(uts, one);
+ if (uts->fail_count != old_fail_count) {
+ printf("Test %s failed %d times (position %d)\n",
+ one->name,
+ uts->fail_count - old_fail_count, pos);
+ }
+ return -EBADF;
+ }
+
for (i = 0; i < uts->runs_per_test; i++)
- ret = ut_run_test_live_flat(uts, test, select_name);
+ ret = ut_run_test_live_flat(uts, test);
if (uts->fail_count != old_fail_count) {
printf("Test %s failed %d times\n", select_name,
uts->fail_count - old_fail_count);
@@ -552,7 +582,7 @@
int ut_run_list(const char *category, const char *prefix,
struct unit_test *tests, int count, const char *select_name,
- int runs_per_test, bool force_run)
+ int runs_per_test, bool force_run, const char *test_insert)
{
struct unit_test_state uts = { .fail_count = 0 };
bool has_dm_tests = false;
@@ -587,7 +617,8 @@
memcpy(uts.fdt_copy, gd->fdt_blob, uts.fdt_size);
}
uts.force_run = force_run;
- ret = ut_run_tests(&uts, prefix, tests, count, select_name);
+ ret = ut_run_tests(&uts, prefix, tests, count, select_name,
+ test_insert);
/* Best efforts only...ignore errors */
if (has_dm_tests)