| commit | 8bbdc3f11306146d9eaff547943e295fb2409f17 | [log] [tgz] |
|---|---|---|
| author | Sricharan R <r.sricharan@ti.com> | Thu May 30 03:19:34 2013 +0000 |
| committer | Tom Rini <trini@ti.com> | Mon Jun 10 08:43:10 2013 -0400 |
| tree | 791ab819ecdd0bcb956b12a6004a0d5b63aa2601 | |
| parent | 9cc5ba0b92c0dfed5a6f9d1fb5b26967ab34dfc5 [diff] |
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>