ARM: uniphier: add PH1-LD11 SoC support
This is a low-cost ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/dram/umc64-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h
index 1b6a838..860d04e 100644
--- a/arch/arm/mach-uniphier/dram/umc64-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc64-regs.h
@@ -18,6 +18,8 @@
#define UMC_INITSET 0x00000040
#define UMC_INITSTAT 0x00000044
#define UMC_CMDCTLE 0x00000050
+#define UMC_CMDCTLF 0x00000054
+#define UMC_CMDCTLG 0x00000058
#define UMC_SPCSETB 0x00000084
#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
@@ -32,6 +34,7 @@
#define UMC_FLOWCTLA 0x00000400
#define UMC_FLOWCTLB 0x00000404
#define UMC_FLOWCTLC 0x00000408
+#define UMC_ACFETCHCTRL 0x00000460
#define UMC_FLOWCTLG 0x00000508
#define UMC_RDATACTL_D0 0x00000600
#define UMC_WDATACTL_D0 0x00000604
@@ -42,6 +45,7 @@
#define UMC_ODTCTL_D1 0x0000061C
#define UMC_RESPCTL 0x00000624
#define UMC_DIRECTBUSCTRLA 0x00000680
+#define UMC_DEBUGC 0x00000718
#define UMC_DCCGCTL 0x00000720
#define UMC_DICGCTLA 0x00000724
#define UMC_DICGCTLB 0x00000728
@@ -70,4 +74,12 @@
#define UMC_MBUS9 0x00002478
#define UMC_MBUS10 0x000024F8
+/* UMC1 register */
+#define UMC_SIORST 0x00000728
+#define UMC_VO0RST 0x0000073c
+#define UMC_VPERST 0x00000744
+#define UMC_RGLRST 0x00000750
+#define UMC_A2DRST 0x00000764
+#define UMC_DMDRST 0x00000770
+
#endif /* UMC_LD20_REGS_H */