diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index c2a5759..61e84e5 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,12 +4,6 @@
 	prompt "DaVinci board select"
 	optional
 
-config TARGET_IPAM390
-	bool "IPAM390 board"
-	select MACH_DAVINCI_DA850_EVM
-	select SOC_DA850
-	select SUPPORT_SPL
-
 config TARGET_DA850EVM
 	bool "DA850 EVM board"
 	select MACH_DAVINCI_DA850_EVM
@@ -136,7 +130,6 @@
 
 endif
 
-source "board/Barix/ipam390/Kconfig"
 source "board/davinci/da8xxevm/Kconfig"
 source "board/lego/ev3/Kconfig"
 
diff --git a/board/Barix/ipam390/Kconfig b/board/Barix/ipam390/Kconfig
deleted file mode 100644
index b85d4da..0000000
--- a/board/Barix/ipam390/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IPAM390
-
-config SYS_BOARD
-	default "ipam390"
-
-config SYS_VENDOR
-	default "Barix"
-
-config SYS_CONFIG_NAME
-	default "ipam390"
-
-endif
diff --git a/board/Barix/ipam390/MAINTAINERS b/board/Barix/ipam390/MAINTAINERS
deleted file mode 100644
index 640e34f..0000000
--- a/board/Barix/ipam390/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IPAM390 BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/Barix/ipam390/
-F:	include/configs/ipam390.h
-F:	configs/ipam390_defconfig
diff --git a/board/Barix/ipam390/Makefile b/board/Barix/ipam390/Makefile
deleted file mode 100644
index 735250a..0000000
--- a/board/Barix/ipam390/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-
-obj-y	+= ipam390.o
diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390
deleted file mode 100644
index be09280..0000000
--- a/board/Barix/ipam390/README.ipam390
+++ /dev/null
@@ -1,229 +0,0 @@
-Summary
-=======
-The README is for the boot procedure on the ipam390 board
-
-In the context of U-Boot, the board is booted in three stages. The initial
-bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
-in the internal ROM. The RBL initializes the internal memory and then
-depending on the exact board and pin configurations will initialize another
-controller (such as NAND) to continue the boot process by loading
-the secondary program loader (SPL). The SPL will initialize the system
-further (some clocks, SDRAM). As on this board is used the falcon boot
-mode, now 2 ways are possible depending on the GPIO 7_14 input pin,
-connected with the "soft reset switch"
-
-If this pin is logical 1 (high level):
-spl code starts the kernel image without delay
-
-If this pin is logical 0 (low level):
-spl code starts the u-boot image
-
-AIS is an image format defined by TI for the images that are to be loaded
-to memory by the RBL. The image is divided into a series of sections and
-the image's entry point is specified. Each section comes with meta data
-like the target address the section is to be copied to and the size of the
-section, which is used by the RBL to load the image. At the end of the
-image the RBL jumps to the image entry point.  The AIS format allows for
-other things such as programming the clocks and SDRAM if the header is
-programmed for it.  We do not take advantage of this and instead use SPL as
-it allows for additional flexibility (run-time detect of board revision,
-loading the next image from a different media, etc).
-
-Compilation
-===========
-run "tools/buildman/buildman -k ipam390" in the u-boot source tree.
-Once this build completes you will have a ../current/ipam390/u-boot.ais file
-that needs to be written to the nand flash.
-
-Flashing the images to NAND
-==========================
-The AIS image can be written to NAND flash using the following commands.
-Assuming that the network is configured and enabled and the u-boot.ais file
-is tftp'able.
-
-U-Boot > print upd_uboot
-upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize}
-U-Boot >
-U-Boot > run upd_uboot
-Using DaVinci-EMAC device
-TFTP from server 192.168.1.1; our IP address is 192.168.20.71
-Filename '/tftpboot/ipam390/u-boot.ais'.
-Load address: 0xc0000000
-Loading: ##################################
-	 1.5 MiB/s
-done
-Bytes transferred = 493716 (78894 hex)
-
-NAND erase.part: device 0 offset 0x20000, size 0x160000
-Erasing at 0x160000 -- 100% complete.
-OK
-
-NAND write: device 0 offset 0x20000, size 0x78894
- 493716 bytes written: OK
-U-Boot >
-
-Recovery
-========
-
-In the case of a "bricked" board, you need to use the TI tools found
-here[1] to create an uboot-uart-ais.bin file
-
-- cd to the u-boot source tree
-
-- compile the u-boot for the ipam390 board:
-$ tools/buildman/buildman -k ipam390
-
-  -> Now we shall have u-boot.bin
-
-- Create u-boot-uart-ais.bin
-$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini ipam390-ais-uart.cfg \
-	-o ../current/ipam390/uboot-uart-ais.bin ./u-boot.bin@0xC1080000;
-
-Note: The ipam390-ais-uart.cfg is found in the board directory
-for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg
-
-- We can now run bootloader on IPAM390 via UART using the command below:
-
-$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin
-NOTE: Do not cancel the command execution! The command takes 20+ seconds
-to upload u-boot over serial and run it!
-Outcome:
-Waiting for the OMAP-L138...
-(AIS Parse): Read magic word 0x41504954.
-(AIS Parse): Waiting for BOOTME... (power on or reset target now)
-(AIS Parse): BOOTME received!
-(AIS Parse): Performing Start-Word Sync...
-(AIS Parse): Performing Ping Opcode Sync...
-(AIS Parse): Processing command 0: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 1: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 2: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 3: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 4: 0x5853590D.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Executing function...
-(AIS Parse): Processing command 5: 0x58535901.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Loading section...
-(AIS Parse): Loaded 326516-Byte section to address 0xC1080000.
-(AIS Parse): Processing command 6: 0x58535906.
-(AIS Parse): Performing Opcode Sync...
-(AIS Parse): Performing jump and close...
-(AIS Parse): AIS complete. Jump to address 0xC1080000.
-(AIS Parse): Waiting for DONE...
-(AIS Parse): Boot completed successfully.
-
-Operation completed successfully.
-
-Falcon Bootmode (boot linux without booting U-Boot)
-===================================================
-
-The Falcon Mode extends this way allowing to start the Linux kernel directly
-from SPL. A new command is added to U-Boot to prepare the parameters that SPL
-must pass to the kernel, using ATAGS or Device Tree.
-
-In normal mode, these parameters are generated each time before
-loading the kernel, passing to Linux the address in memory where
-the parameters can be read.
-With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
-informed to load it before running the kernel.
-
-To boot the kernel, these steps under a Falcon-aware U-Boot are required:
-
-1. Boot the board into U-Boot.
-Use the "spl export" command to generate the kernel parameters area or the DT.
-U-Boot runs as when it boots the kernel, but stops before passing the control
-to the kernel.
-
-Here the command sequence for the ipam390 board:
-- load the linux kernel image into ram:
-
-U-Boot > nand read c0100000 2 200000 400000
-
-NAND read: device 0 offset 0x200000, size 0x400000
- 4194304 bytes read: OK
-
-- generate the bootparms image:
-
-U-Boot > spl export atags c0100000
-## Booting kernel from Legacy Image at c0100000 ...
-   Image Name:   Linux-3.5.1
-   Image Type:   ARM Linux Kernel Image (uncompressed)
-   Data Size:    2504280 Bytes = 2.4 MiB
-   Load Address: c0008000
-   Entry Point:  c0008000
-   Verifying Checksum ... OK
-   Loading Kernel Image ... OK
-subcommand not supported
-subcommand not supported
-Argument image is now in RAM at: 0xc0000100
-
-- copy the bootparms image into nand:
-
-U-Boot > mtdparts
-
-device nand0 <davinci_nand.0>, # parts = 6
- #: name		size		offset		mask_flags
- 0: u-boot-env          0x00020000	0x00000000	0
- 1: u-boot              0x00160000	0x00020000	0
- 2: bootparms           0x00020000	0x00180000	0
- 3: factory-info        0x00060000	0x001a0000	0
- 4: kernel              0x00400000	0x00200000	0
- 5: rootfs              0x07a00000	0x00600000	0
-
-active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000
-
-defaults:
-mtdids  : nand0=davinci_nand.0
-mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)
-U-Boot > nand erase.part bootparms
-
-NAND erase.part: device 0 offset 0x180000, size 0x20000
-Erasing at 0x180000 -- 100% complete.
-OK
-U-Boot > nand write c0000100 180000 20000
-
-NAND write: device 0 offset 0x180000, size 0x20000
- 131072 bytes written: OK
-U-Boot >
-
-You can use also the predefined U-Boot Environment variable "setbootparms",
-which will do all the above steps in one command:
-
-U-Boot > print setbootparms
-setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000
-U-Boot > run setbootparms
-
-NAND read: device 0 offset 0x200000, size 0x400000
- 4194304 bytes read: OK
-## Booting kernel from Legacy Image at c0100000 ...
-   Image Name:   Linux-3.5.1
-   Image Type:   ARM Linux Kernel Image (uncompressed)
-   Data Size:    2504280 Bytes = 2.4 MiB
-   Load Address: c0008000
-   Entry Point:  c0008000
-   Verifying Checksum ... OK
-   Loading Kernel Image ... OK
-subcommand not supported
-subcommand not supported
-Argument image is now in RAM at: 0xc0000100
-
-NAND erase.part: device 0 offset 0x180000, size 0x20000
-Erasing at 0x180000 -- 100% complete.
-OK
-
-NAND write: device 0 offset 0x180000, size 0x20000
- 131072 bytes written: OK
-U-Boot >
-
-Links
-=====
-[1]
- http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/
diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg
deleted file mode 100644
index 709cf23..0000000
--- a/board/Barix/ipam390/ipam390-ais-uart.cfg
+++ /dev/null
@@ -1,202 +0,0 @@
-; General settings that can be overwritten in the host code
-; that calls the AISGen library.
-[General]
-
-; Can be 8 or 16 - used in emifa
-busWidth=8
-
-; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
-BootMode=UART
-
-; 8,16,24 - used for SPI,I2C
-;AddrWidth=8
-
-; NO_CRC,SECTION_CRC,SINGLE_CRC
-crcCheckType=NO_CRC
-
-; This section allows setting the PLL0 system clock with a
-; specified multiplier and divider as shown. The clock source
-; can also be chosen for internal or external.
-;           |------24|------16|-------8|-------0|
-; PLL0CFG0: | CLKMODE| PLLM   | PREDIV | POSTDIV|
-; PLL0CFG1: | RSVD   | PLLDIV1| PLLDIV3| PLLDIV7|
-;[PLL0CONFIG]
-;PLL0CFG0 = 0x00180001
-;PLL0CFG1 = 0x00000205
-
-[PLLANDCLOCKCONFIG]
-PLL0CFG0 = 0x00180001
-PLL0CFG1 = 0x00000205
-PERIPHCLKCFG = 0x00000051
-
-; This section allows setting up the PLL1. Usually this will
-; take place as part of the EMIF3a DDR setup. The format of
-; the input args is as follows:
-;           |------24|------16|-------8|-------0|
-; PLL1CFG0: |    PLLM| POSTDIV| PLLDIV1| PLLDIV2|
-; PLL1CFG1: |           RSVD           | PLLDIV3|
-[PLL1CONFIG]
-PLL1CFG0 = 0x18010001
-PLL1CFG1 = 0x00000002
-
-; This section lets us configure the peripheral interface
-; of the current booting peripheral (I2C, SPI, or UART).
-; Use with caution. The format of the PERIPHCLKCFG field
-; is as follows:
-; SPI:        |------24|------16|-------8|-------0|
-;             |           RSVD           |PRESCALE|
-;
-; I2C:        |------24|------16|-------8|-------0|
-;             |  RSVD  |PRESCALE|  CLKL  |  CLKH  |
-;
-; UART:       |------24|------16|-------8|-------0|
-;             | RSVD   |  OSR   |  DLH   |  DLL   |
-[PERIPHCLKCFG]
-PERIPHCLKCFG = 0x00000051
-
-; This section can be used to configure the PLL1 and the EMIF3a registers
-; for starting the DDR2 interface.
-; See PLL1CONFIG section for the format of the PLL1CFG fields.
-;            |------24|------16|-------8|-------0|
-; PLL1CFG0:  |              PLL1CFG              |
-; PLL1CFG1:  |              PLL1CFG              |
-; DDRPHYC1R: |             DDRPHYC1R             |
-; SDCR:      |              SDCR                 |
-; SDTIMR:    |              SDTIMR               |
-; SDTIMR2:   |              SDTIMR2              |
-; SDRCR:     |              SDRCR                |
-; CLK2XSRC:  |             CLK2XSRC              |
-[EMIF3DDR]
-PLL1CFG0 = 0x18010001
-PLL1CFG1 = 0x00000002
-DDRPHYC1R = 0x000000C2
-SDCR = 0x0017C432
-SDTIMR = 0x26922A09
-SDTIMR2 = 0x4414C722
-SDRCR = 0x00000498
-CLK2XSRC = 0x00000000
-
-; This section can be used to configure the EMIFA to use
-; CS0 as an SDRAM interface.  The fields required to do this
-; are given below.
-;                     |------24|------16|-------8|-------0|
-; SDBCR:              |               SDBCR               |
-; SDTIMR:             |               SDTIMR              |
-; SDRSRPDEXIT:        |             SDRSRPDEXIT           |
-; SDRCR:              |               SDRCR               |
-; DIV4p5_CLK_ENABLE:  |         DIV4p5_CLK_ENABLE         |
-;[EMIF25SDRAM]
-;SDBCR = 0x00004421
-;SDTIMR = 0x42215810
-;SDRSRPDEXIT = 0x00000009
-;SDRCR = 0x00000410
-;DIV4p5_CLK_ENABLE = 0x00000001
-
-; This section can be used to configure the async chip selects
-; of the EMIFA (CS2-CS5).  The fields required to do this
-; are given below.
-;           |------24|------16|-------8|-------0|
-; A1CR:     |                A1CR               |
-; A2CR:     |                A2CR               |
-; A3CR:     |                A3CR               |
-; A4CR:     |                A4CR               |
-; NANDFCR:  |              NANDFCR              |
-;[EMIF25ASYNC]
-;A1CR = 0x00000000
-;A2CR = 0x00000000
-;A3CR = 0x00000000
-;A4CR = 0x00000000
-;NANDFCR = 0x00000000
-[EMIF25ASYNC]
-A1CR = 0x00000000
-A2CR = 0x04202110
-A3CR = 0x00000000
-A4CR = 0x00000000
-NANDFCR = 0x00000012
-
-; This section should be used in place of PLL0CONFIG when
-; the I2C, SPI, or UART modes are being used.  This ensures that
-; the system PLL and the peripheral's clocks are changed together.
-; See PLL0CONFIG section for the format of the PLL0CFG fields.
-; See PERIPHCLKCFG section for the format of the CLKCFG field.
-;               |------24|------16|-------8|-------0|
-; PLL0CFG0:     |              PLL0CFG              |
-; PLL0CFG1:     |              PLL0CFG              |
-; PERIPHCLKCFG: |              CLKCFG               |
-;[PLLANDCLOCKCONFIG]
-;PLL0CFG0 = 0x00180001
-;PLL0CFG1 = 0x00000205
-;PERIPHCLKCFG = 0x00010032
-
-; This section should be used to setup the power state of modules
-; of the two PSCs.  This section can be included multiple times to
-; allow the configuration of any or all of the device modules.
-;           |------24|------16|-------8|-------0|
-; LPSCCFG:  | PSCNUM | MODULE |   PD   | STATE  |
-;[PSCCONFIG]
-;LPSCCFG=
-
-; This section allows setting of a single PINMUX register.
-; This section can be included multiple times to allow setting
-; as many PINMUX registers as needed.
-;         |------24|------16|-------8|-------0|
-; REGNUM: |              regNum               |
-; MASK:   |               mask                |
-; VALUE:  |              value                |
-;[PINMUX]
-;REGNUM = 5
-;MASK = 0x00FF0000
-;VALUE = 0x00880000
-
-; No Params required - simply include this section for the fast boot
-; function to be called
-;[FASTBOOT]
-
-; This section allows setting up the PLL1. Usually this will
-; take place as part of the EMIF3a DDR setup. The format of
-; the input args is as follows:
-;           |------24|------16|-------8|-------0|
-; PLL1CFG0: |    PLLM| POSTDIV| PLLDIV1| PLLDIV2|
-; PLL1CFG1: |           RSVD           | PLLDIV3|
-;[PLL1CONFIG]
-;PLL1CFG0 = 0x15010001
-;PLL1CFG1 = 0x00000002
-
-; This section can be used to configure the PLL1 and the EMIF3a registers
-; for starting the DDR2 interface on ARM-boot D800K002 devices.
-;            |------24|------16|-------8|-------0|
-; DDRPHYC1R: |             DDRPHYC1R             |
-; SDCR:      |              SDCR                 |
-; SDTIMR:    |              SDTIMR               |
-; SDTIMR2:   |              SDTIMR2              |
-; SDRCR:     |              SDRCR                |
-; CLK2XSRC:  |             CLK2XSRC              |
-;[ARM_EMIF3DDR_PATCHFXN]
-;DDRPHYC1R = 0x000000C2
-;SDCR = 0x0017C432
-;SDTIMR = 0x26922A09
-;SDTIMR2 = 0x4414C722
-;SDRCR = 0x00000498
-;CLK2XSRC = 0x00000000
-
-; This section can be used to configure the PLL1 and the EMIF3a registers
-; for starting the DDR2 interface on DSP-boot D800K002 devices.
-;            |------24|------16|-------8|-------0|
-; DDRPHYC1R: |             DDRPHYC1R             |
-; SDCR:      |              SDCR                 |
-; SDTIMR:    |              SDTIMR               |
-; SDTIMR2:   |              SDTIMR2              |
-; SDRCR:     |              SDRCR                |
-; CLK2XSRC:  |             CLK2XSRC              |
-;[DSP_EMIF3DDR_PATCHFXN]
-;DDRPHYC1R = 0x000000C4
-;SDCR = 0x08134632
-;SDTIMR = 0x26922A09
-;SDTIMR2 = 0x0014C722
-;SDRCR = 0x00000492
-;CLK2XSRC = 0x00000000
-
-;[INPUTFILE]
-;FILENAME=u-boot.bin
-;LOADADDRESS=0xC1080000
-;ENTRYPOINTADDRESS=0xC1080000
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
deleted file mode 100644
index da75ead..0000000
--- a/board/Barix/ipam390/ipam390.c
+++ /dev/null
@@ -1,335 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- * Based on:
- * U-Boot:board/davinci/da8xxevm/da850evm.c
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on da830evm.c. Original Copyrights follow:
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include <asm/arch/hardware.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/pinmux_defs.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <hwconfig.h>
-#include <bootstage.h>
-#include <asm/mach-types.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define HAS_RMII 1
-#else
-#define HAS_RMII 0
-#endif
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-void dsp_lpsc_on(unsigned domain, unsigned int id)
-{
-	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-	struct davinci_psc_regs *psc_regs;
-
-	psc_regs = davinci_psc0_regs;
-	mdstat = &psc_regs->psc0.mdstat[id];
-	mdctl = &psc_regs->psc0.mdctl[id];
-	ptstat = &psc_regs->ptstat;
-	ptcmd = &psc_regs->ptcmd;
-
-	while (*ptstat & (0x1 << domain))
-		;
-
-	if ((*mdstat & 0x1f) == 0x03)
-		return;                 /* Already on and enabled */
-
-	*mdctl |= 0x03;
-
-	*ptcmd = 0x1 << domain;
-
-	while (*ptstat & (0x1 << domain))
-		;
-	while ((*mdstat & 0x1f) != 0x03)
-		;		/* Probably an overkill... */
-}
-
-static void dspwake(void)
-{
-	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
-	u32 val;
-
-	/* if the device is ARM only, return */
-	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
-		return;
-
-	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
-		return;
-
-	*resetvect++ = 0x1E000; /* DSP Idle */
-	/* clear out the next 10 words as NOP */
-	memset(resetvect, 0, sizeof(unsigned) * 10);
-
-	/* setup the DSP reset vector */
-	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
-
-	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
-	val = readl(PSC0_MDCTL + (15 * 4));
-	val |= 0x100;
-	writel(val, (PSC0_MDCTL + (15 * 4)));
-}
-
-int misc_init_r(void)
-{
-	dspwake();
-	return 0;
-}
-
-static const struct pinmux_config gpio_pins[] = {
-	/* GP7[14] selects bootmode*/
-	{ pinmux(16), 8, 3 },	/* GP7[14] */
-};
-
-const struct pinmux_resource pinmuxes[] = {
-#ifdef CONFIG_DRIVER_TI_EMAC
-	PINMUX_ITEM(emac_pins_mdio),
-#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
-	PINMUX_ITEM(emac_pins_rmii),
-#else
-	PINMUX_ITEM(emac_pins_mii),
-#endif
-#endif
-	PINMUX_ITEM(uart2_pins_txrx),
-	PINMUX_ITEM(uart2_pins_rtscts),
-	PINMUX_ITEM(uart0_pins_txrx),
-	PINMUX_ITEM(uart0_pins_rtscts),
-#ifdef CONFIG_NAND_DAVINCI
-	PINMUX_ITEM(emifa_pins_cs3),
-	PINMUX_ITEM(emifa_pins_nand),
-#endif
-	PINMUX_ITEM(gpio_pins),
-};
-
-const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-
-const struct lpsc_resource lpsc[] = {
-	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
-	{ DAVINCI_LPSC_EMAC },	/* image download */
-	{ DAVINCI_LPSC_UART2 },	/* console */
-	{ DAVINCI_LPSC_UART0 },	/* console */
-	{ DAVINCI_LPSC_GPIO },
-};
-
-const int lpsc_size = ARRAY_SIZE(lpsc);
-
-#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
-#define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
-#endif
-
-#define REV_AM18X_EVM		0x100
-
-/*
- * get_board_rev() - setup to pass kernel board revision information
- * Returns:
- * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
- *		0000b - 300 MHz
- *		0001b - 372 MHz
- *		0010b - 408 MHz
- *		0011b - 456 MHz
- */
-u32 get_board_rev(void)
-{
-	char *s;
-	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
-	u32 rev = 0;
-
-	s = env_get("maxcpuclk");
-	if (s)
-		maxcpuclk = simple_strtoul(s, NULL, 10);
-
-	if (maxcpuclk >= 456000000)
-		rev = 3;
-	else if (maxcpuclk >= 408000000)
-		rev = 2;
-	else if (maxcpuclk >= 372000000)
-		rev = 1;
-#ifdef CONFIG_DA850_AM18X_EVM
-	rev |= REV_AM18X_EVM;
-#endif
-	return rev;
-}
-
-int board_early_init_f(void)
-{
-	/*
-	 * Power on required peripherals
-	 * ARM does not have access by default to PSC0 and PSC1
-	 * assuming here that the DSP bootloader has set the IOPU
-	 * such that PSC access is available to ARM
-	 */
-	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
-		return 1;
-
-	return 0;
-}
-
-int board_init(void)
-{
-	irq_init();
-
-	/* arch number of the board */
-	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* setup the SUSPSRC for ARM to control emulation suspend */
-	writel(readl(&davinci_syscfg_regs->suspsrc) &
-	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
-		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
-		 DAVINCI_SYSCFG_SUSPSRC_UART0),
-	       &davinci_syscfg_regs->suspsrc);
-
-	/* configure pinmux settings */
-	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
-		return 1;
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-	davinci_emac_mii_mode_sel(HAS_RMII);
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-	/* enable the console UART */
-	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
-		DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
-	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
-#else
-	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Initializes on-board ethernet controllers.
- */
-int board_eth_init(bd_t *bis)
-{
-	if (!davinci_emac_initialize()) {
-		printf("Error: Ethernet init failed!\n");
-		return -1;
-	}
-
-	return 0;
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-static int init_led(int gpio, char *name, int val)
-{
-	int ret;
-
-	ret = gpio_request(gpio, name);
-	if (ret)
-		return -1;
-	ret = gpio_direction_output(gpio, val);
-	if (ret)
-		return -1;
-
-	return gpio;
-}
-
-#define LED_ON	0
-#define LED_OFF	1
-
-#if !defined(CONFIG_SPL_BUILD)
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress(int status)
-{
-	static int red;
-	static int green;
-
-	if (red == 0)
-		red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
-	if (red != CONFIG_IPAM390_GPIO_LED_RED)
-		return;
-	if (green == 0)
-		green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green",
-				 LED_OFF);
-	if (green != CONFIG_IPAM390_GPIO_LED_GREEN)
-		return;
-
-	switch (status) {
-	case BOOTSTAGE_ID_RUN_OS:
-		/*
-		 * set normal state
-		 * LED Red  : on
-		 * LED green: off
-		 */
-		gpio_set_value(red, LED_ON);
-		gpio_set_value(green, LED_OFF);
-		break;
-	case BOOTSTAGE_ID_MAIN_LOOP:
-		/*
-		 * U-Boot operation
-		 * LED Red  : on
-		 * LED green: on
-		 */
-		gpio_set_value(red, LED_ON);
-		gpio_set_value(green, LED_ON);
-		break;
-	}
-}
-#endif
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-	int ret;
-	int bootmode = 0;
-
-	/*
-	 * GP7[14] selects bootmode:
-	 * 1: boot linux
-	 * 0: boot u-boot
-	 * if error accessing gpio boot U-Boot
-	 *
-	 * SPL bootmode
-	 * 0: boot linux
-	 * 1: boot u-boot
-	 */
-	ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode");
-	if (ret)
-		bootmode = 1;
-	if (!bootmode) {
-		ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE);
-		if (ret)
-			bootmode = 1;
-	}
-	if (!bootmode)
-		ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE);
-	if (!bootmode)
-		if (ret == 0)
-			bootmode = 1;
-	/*
-	 * LED red  : on
-	 * LED green: off
-	 */
-	init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
-	init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
-	return bootmode;
-}
-#endif
diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds
deleted file mode 100644
index 06ed3fa..0000000
--- a/board/Barix/ipam390/u-boot-spl-ipam390.lds
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- */
-
-MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
-		LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text      :
-	{
-	__start = .;
-	  *(.vectors)
-	  arch/arm/cpu/arm926ejs/start.o	(.text*)
-	  *(.text*)
-	} >.sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
-	. = ALIGN(4);
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	} >.sram
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} >.sram
-
-	__image_copy_end = .;
-
-	.end :
-	{
-		*(.__end)
-	} >.sram
-}
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
deleted file mode 100644
index f227026..0000000
--- a/configs/ipam390_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_DAVINCI=y
-CONFIG_SYS_TEXT_BASE=0xc1080000
-CONFIG_TARGET_IPAM390=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_TEXT_BASE=0x80000000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot > "
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00180000
-CONFIG_CMD_SPL_WRITE_SIZE=0x400
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)"
-CONFIG_CMD_DIAG=y
-CONFIG_CMD_UBI=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DA8XX_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_NAND=y
-CONFIG_NAND_DAVINCI=y
-CONFIG_DRIVER_TI_EMAC=y
-CONFIG_SYS_NS16550=y
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
deleted file mode 100644
index e4e8e2a..0000000
--- a/include/configs/ipam390.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- * Based on:
- * U-Boot:include/configs/da850evm.h
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on davinci_dvevm.h. Original Copyrights follow:
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Board
- */
-
-/*
- * SoC Configuration
- */
-#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
-#define CONFIG_SYS_OSCIN_FREQ		24000000
-#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
-
-/*
- * Memory Info
- */
-#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
-#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
-#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
-
-/* memtest start addr */
-#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
-
-/* memtest will be run on 16MB */
-#define CONFIG_SYS_MEMTEST_END	(CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
-	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
-	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
-	DAVINCI_SYSCFG_SUSPSRC_UART0 |		\
-	DAVINCI_SYSCFG_SUSPSRC_EMAC)
-
-/*
- * PLL configuration
- */
-
-#define CONFIG_SYS_DA850_PLL0_PLLM     24
-#define CONFIG_SYS_DA850_PLL1_PLLM     24
-
-/*
- * DDR2 memory configuration
- */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
-					DV_DDR_PHY_EXT_STRBEN | \
-					(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
-#define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000498
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR2	0x00000004
-#define CONFIG_SYS_DA850_DDR2_PBBPR	0x00000020
-
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
-	(13 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
-	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
-	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
-	(2 << DV_DDR_SDTMR1_WR_SHIFT) |		\
-	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
-	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
-	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
-	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
-	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
-	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
-	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
-	(14 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
-	(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
-	(1 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
-	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
-
-#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
-	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
-	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
-	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
-	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
-	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
-	(2 << DV_DDR_SDCR_CL_SHIFT) |	\
-	(3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
-	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
-
-#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
-				DAVINCI_ABCR_WSTROBE(2)	| \
-				DAVINCI_ABCR_WHOLD(0)	| \
-				DAVINCI_ABCR_RSETUP(1)	| \
-				DAVINCI_ABCR_RSTROBE(2)	| \
-				DAVINCI_ABCR_RHOLD(1)	| \
-				DAVINCI_ABCR_TA(0)	| \
-				DAVINCI_ABCR_ASIZE_8BIT)
-
-/*
- * Serial Driver info
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART0_BASE /* Base address of UART0 */
-#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
-
-/*
- * Flash & Environment
- */
-#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
-#define CONFIG_ENV_SIZE			(128 << 10)
-#define	CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define	CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS		3
-#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE		0x10
-#define CONFIG_SYS_NAND_MASK_ALE		0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
-#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x120000
-#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
-					CONFIG_SYS_NAND_U_BOOT_SIZE - \
-					CONFIG_SYS_MALLOC_LEN -       \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS		{				\
-			6,   7,  8,  9, 10,	11, 12, 13, 14, 15,	\
-			22, 23, 24, 25, 26,	27, 28, 29, 30, 31,	\
-			38, 39, 40, 41, 42,	43, 44, 45, 46, 47,	\
-			54, 55, 56, 57, 58,	59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	10
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_LOAD
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_BOOTP_DEFAULT
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT	10
-#endif
-
-/*
- * U-Boot general configuration
- */
-#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
-#define CONFIG_MX_CYCLIC
-
-/*
- * Linux Information
- */
-#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
-#define CONFIG_HWCONFIG		/* enable hwconfig */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
-		"root=/dev/mtdblock5 rw noinitrd " \
-		"rootfstype=jffs2 noinitrd\0" \
-	"hwconfig=dsp:wake=yes\0" \
-	"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
-	"bootfile=uImage\0" \
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
-	"mtddevname=uboot-env\0" \
-	"mtddevnum=0\0" \
-	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
-	"u-boot=/tftpboot/ipam390/u-boot.ais\0"			\
-	"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
-		"nand write c0000000 20000 ${filesize}\0"	\
-	"setbootparms=nand read c0100000 200000 400000;"	\
-		"run defbootargs addmtd;"			\
-		"spl export atags c0100000;"			\
-		"nand erase.part bootparms;"			\
-		"nand write c0000100 180000 20000\0"		\
-	"\0"
-
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
-/* defines for SPL */
-#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
-						CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_STACK	0x8001ff00
-#define CONFIG_SPL_MAX_SIZE	0x20000
-#define CONFIG_SPL_MAX_FOOTPRINT	32768
-
-/* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0xc0000000
-
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
-					GENERATED_GBL_DATA_SIZE)
-
-/* add FALCON boot mode */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000
-#define CONFIG_SYS_SPL_ARGS_ADDR	LINUX_BOOT_PARAM_ADDR
-
-/* GPIO support */
-#define CONFIG_IPAM390_GPIO_BOOTMODE	((16 * 7) + 14)
-
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_IPAM390_GPIO_LED_RED	((16 * 7) + 11)
-#define CONFIG_IPAM390_GPIO_LED_GREEN	((16 * 7) + 12)
-
-#include <asm/arch/hardware.h>
-
-#endif /* __CONFIG_H */