| commit | bc42fde9c5d15d1e64092723042dd726172a1be3 | [log] [tgz] |
|---|---|---|
| author | Joakim Tjernlund <joakim.tjernlund@infinera.com> | Tue Sep 12 19:56:41 2017 +0200 |
| committer | York Sun <york.sun@nxp.com> | Wed Aug 08 08:23:48 2018 -0700 |
| tree | c34f38c831d61a5f2943ff96658f1f98e764061f | |
| parent | dd6c9ff9af9ee33019f037c68cd52923b85b6f4c [diff] |
FSL PCI: Configure PCIe reference ratio Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured. This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>