arm926ejs, at91: add common phy_reset function
add common phy reset code into a common function.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Jens Scharsig <esw@bus-elektronik.de>
Cc: Sergey Lapin <slapin@ossfans.org>
Cc: Stelian Pop <stelian@popies.net>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Markus Hubig <mhubig@imko.de>
Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile
index d97053f..5b97838 100644
--- a/arch/arm/cpu/at91-common/Makefile
+++ b/arch/arm/cpu/at91-common/Makefile
@@ -8,4 +8,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c
new file mode 100644
index 0000000..3b6c60c
--- /dev/null
+++ b/arch/arm/cpu/at91-common/phy.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <watchdog.h>
+
+void at91_phy_reset(void)
+{
+ unsigned long erstl;
+ unsigned long start = get_timer(0);
+ unsigned long const timeout = 1000; /* 1000ms */
+ at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+ /*
+ * Need to reset PHY -> 500ms reset
+ * Reset PHY by pulling the NRST line for 500ms to low. To do so
+ * disable user reset for low level on NRST pin and poll the NRST
+ * level in reset status register.
+ */
+ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+ AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+ /* Wait for end of hardware reset */
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+ /* avoid shutdown by watchdog */
+ WATCHDOG_RESET();
+ mdelay(10);
+
+ /* timeout for not getting stuck in an endless loop */
+ if (get_timer(start) >= timeout) {
+ puts("*** ERROR: Timeout waiting for PHY reset!\n");
+ break;
+ }
+ };
+
+ /* Restore NRST value */
+ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+}