riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 043fb96..088205e 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -8,4 +8,5 @@
else
obj-y += dram.o
obj-y += cpu.o
+obj-y += cache.o
endif