diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 8235430..c54b581 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -102,3 +102,107 @@
 	  This allows access to raw blocks and filesystems on an IDE drive
 	  from U-Boot. See also CMD_IDE which provides an 'ide' command for
 	  performing various IDE operations.
+
+if IDE
+
+config SYS_IDE_MAXBUS
+	hex "Maximumm number of IDE buses"
+	default 2
+	help
+	  This is the number of IDE buses provided by the board. Each one
+	  can have one or two devices. One is designated the master and the
+	  other one the slave. It is not required to have one or both on any
+	  controller.
+
+config SYS_IDE_MAXDEVICE
+	hex "Maximum number of IDE devices"
+	default 2
+	help
+	  This is the number of IDE devices which can be connected to the
+	  board. Normally this is 2 * CONFIG_SYS_IDE_MAXBUS since up to two
+	  devices can be connected to each bus. The number of devices actually
+	  connected is determined by probing.
+
+config SYS_ATA_BASE_ADDR
+	hex "Base address of IDE controller"
+	default 0
+	help
+	  This is the address of the IDE controller, from which other addresses
+	  are calculated. Each bus is at a fixed offset from this address,
+	  so it assumed that they are in the same area of the I/O space or
+	  memory.
+
+config SYS_ATA_STRIDE
+	hex "IDE port stride"
+	default 0x1
+	help
+	  This is the distance between each IDE register, in bytes. For an
+	  8-bit controller this is typically 1, meaning that the registers
+	  appear at consecutive bytes. If the value 2 two, that might indicate
+	  a 16-bit register space.
+
+config SYS_ATA_DATA_OFFSET
+	hex "Offset of the data register"
+	default 0x0
+	help
+	  This is the offset of the controller's data register from the base
+	  address of the controller. This is typically 0, but may be something
+	  else if there are some other registers at the start of the
+	  controller space.
+
+config SYS_ATA_REG_OFFSET
+	hex "Offset of the register space"
+	default 0x0
+	help
+	  This is the offset of the controller's 'register' space from the base
+	  address of the controller. The data register (which is typically at
+	  offset 0) has its own CONFIG, to deal with controllers where it is
+	  somewhere else. Register 1 will be at this offset + 1, register 2 at
+	  CONFIG_SYS_ATA_REG_OFFSET + 2, etc.
+
+config SYS_ATA_ALT_OFFSET
+	hex "Offset of the alternative registers"
+	default 0x0
+	help
+	  This is the offset of the controller's 'alternative' space from the
+	  base address of the controller. This allows these registers to be
+	  located separately from the data and register space.
+
+config SYS_ATA_IDE0_OFFSET
+	hex "Offset of bus 0"
+	default 0x1f0
+	help
+	  This is the start offset of bus 0 from the start of the
+	  controller registers. All the other registers are calculated from
+	  this address. using the above options. For x86 hardware this is often
+	  0x1f0.
+
+config SYS_ATA_IDE1_OFFSET
+	hex "Offset of bus 1"
+	default 0x170
+	help
+	  This is the start offset of bus 1 from the start of the
+	  controller registers. All the other registers are calculated from
+	  this address. using the above options. For x86 hardware this is often
+	  0x170.
+
+config ATAPI
+	bool "Enable ATAPI support"
+	help
+	  This enabled Advanced Technology Attachment Packet Interface (ATAPI),
+	  a protocol that allows a greater variety of devices to be connected
+	  to the IDE port than with plain ATA. It allows SCSI commands to be
+	  sent across the bus, e.g. to support optical drives.
+
+config IDE_RESET
+	bool "Support board-specific reset"
+	help
+	  If this is defined, IDE Reset will be performed by calling the
+	  function:
+
+	     ide_set_reset(int reset)
+
+	  where reset is 1 to assert reset and 0 to de-assert it. This function
+	  must be defined in a board-specific file.
+
+endif  # IDE