MSCC: Add support for Jaguar2 SOC family
As the Ocelot and Luton SoCs, this family of SoCs are found
in Microsemi Switches solution.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index 390bbd0..e0e610a 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -12,6 +12,22 @@
void _machine_restart(void)
{
+#if defined(CONFIG_SOC_JR2)
+ register u32 reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
+ /* Set owner */
+ reg &= ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M;
+ reg |= ICPU_GENERAL_CTRL_IF_SI_OWNER(1);
+ /* Set boot mode */
+ reg |= ICPU_GENERAL_CTRL_BOOT_MODE_ENA;
+ writel(reg, BASE_CFG + ICPU_GENERAL_CTRL);
+ /* Read back in order to make BOOT mode setting active */
+ reg = readl(BASE_CFG + ICPU_GENERAL_CTRL);
+ /* Reset CPU only - still executing _here_. but from cache */
+ writel(readl(BASE_CFG + ICPU_RESET) |
+ ICPU_RESET_CORE_RST_CPU_ONLY |
+ ICPU_RESET_CORE_RST_FORCE,
+ BASE_CFG + ICPU_RESET);
+#else
register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
@@ -24,6 +40,7 @@
/* Do the global reset */
writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+#endif
while (1)
; /* NOP */