board: qualcomm: Add support for QCS404 EVB
Add support for Qualcomm QCS404 SoC based evaluation board.
Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/qcs404.rst.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index cb53dc8..0927333 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -69,11 +69,22 @@
select SDM845
select DM_ETH if NET
+config TARGET_QCS404EVB
+ bool "Qualcomm Technologies, Inc. QCS404 EVB"
+ select LINUX_KERNEL_IMAGE_HEADER
+ help
+ Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
+ Features:
+ - Qualcomm Snapdragon QCS404 SoC
+ - 1GiB RAM
+ - 8GiB eMMC, uSD slot
+
endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
source "board/qualcomm/dragonboard845c/Kconfig"
source "board/samsung/starqltechn/Kconfig"
+source "board/qualcomm/qcs404-evb/Kconfig"
endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index cb8c1aa..0d31f10 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -17,3 +17,5 @@
obj-y += pinctrl-apq8096.o
obj-y += pinctrl-qcs404.o
obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
+obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
new file mode 100644
index 0000000..b740903
--- /dev/null
+++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 memory map
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region qcs404_mem_map[] = {
+ {
+ .virt = 0x0UL, /* Peripheral block */
+ .phys = 0x0UL, /* Peripheral block */
+ .size = 0x8000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL, /* DDR */
+ .phys = 0x80000000UL, /* DDR */
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = qcs404_mem_map;