powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe
controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 0e255ff..6a4279c 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -90,6 +90,7 @@
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#ifdef CONFIG_MPC8641
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI