commit 8958f56956cf222eb2cac72b7b861d4926285784
author Wills Wang <wills.wang@live.com> Mon May 30 22:54:54 2016 +0800
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tue May 31 10:17:54 2016 +0200
tree 716a5b29c4dcf7d337fb2f3845bbdfe7a97ba90a
parent 4b97393d463a4cebc9dcbc0714e212ee3dac96a1

mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by: Wills Wang <wills.wang@live.com>

arch/mips/mach-ath79/reset.c

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index a5ee141..073a179 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -89,7 +89,7 @@
 	mdelay(10);
 
 	/* Get Atheros S26 PHY out of reset. */
-	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+	clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
 			0x1f, 0x10);
 	mdelay(10);