diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e682d65..ddef3d0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -609,6 +609,9 @@
 	help
 	  This ARM64 system supports AArch32 execution state.
 
+config S5P
+	def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
+
 choice
 	prompt "Target select"
 	default TARGET_HIKEY
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a9f4ccc..87b210d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -5,9 +5,9 @@
 dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
 dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
 
-dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
-dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
-dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
+dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
+dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb
+dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \
 	exynos4210-smdkv310.dtb \
 	exynos4210-universal_c210.dtb \
 	exynos4210-trats.dtb \
@@ -19,7 +19,7 @@
 
 dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
 
-dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
+dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-spring.dtb \
 	exynos5250-smdk5250.dtb \
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index b5790bd..0ece4b0 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -6,9 +6,8 @@
 #ifndef	_ASM_SPL_H_
 #define	_ASM_SPL_H_
 
-#if defined(CONFIG_ARCH_OMAP2PLUS) \
-	|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
-	|| defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3)
+#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) || \
+	defined(CONFIG_ARCH_K3) || defined(CONFIG_ARCH_OMAP2PLUS)
 /* Platform-specific defines */
 #include <asm/arch/spl.h>
 
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 77fb9d1..8410290 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -54,11 +54,15 @@
 
 if ARCH_EXYNOS4
 
+config EXYNOS4210
+	bool
+
 choice
 	prompt "EXYNOS4 board select"
 
 config TARGET_SMDKV310
 	bool "Exynos4210 SMDKV310 board"
+	select EXYNOS4210
 	select OF_CONTROL
 	select SUPPORT_SPL
 
@@ -70,6 +74,7 @@
 
 config TARGET_ORIGEN
 	bool "Exynos4412 Origen board"
+	select EXYNOS4210
 	select SUPPORT_SPL
 
 config TARGET_TRATS2
@@ -83,6 +88,15 @@
 
 if ARCH_EXYNOS5
 
+config EXYNOS5250
+	bool
+
+config EXYNOS5420
+	bool
+
+config EXYNOS5_DT
+	bool
+
 config SPL_GPIO
 	default y
 
@@ -97,6 +111,8 @@
 
 config TARGET_ODROID_XU3
 	bool "Exynos5422 Odroid board"
+	select EXYNOS5_DT
+	select EXYNOS5420
 	select OF_CONTROL
 
 config TARGET_ARNDALE
@@ -105,36 +121,49 @@
 	select ARM_ERRATA_774769
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select EXYNOS5250
 	select OF_CONTROL
 	select SUPPORT_SPL
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
+	select EXYNOS5_DT
+	select EXYNOS5250
 	select OF_CONTROL
 	select SUPPORT_SPL
 
 config TARGET_SNOW
 	bool "Snow board"
+	select EXYNOS5_DT
+	select EXYNOS5250
 	select OF_CONTROL
 	select SUPPORT_SPL
 
 config TARGET_SPRING
 	bool "Spring board"
+	select EXYNOS5_DT
+	select EXYNOS5250
 	select OF_CONTROL
 	select SUPPORT_SPL
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
+	select EXYNOS5_DT
+	select EXYNOS5420
 	select OF_CONTROL
 	select SUPPORT_SPL
 
 config TARGET_PEACH_PI
 	bool "Peach Pi board"
+	select EXYNOS5_DT
+	select EXYNOS5420
 	select OF_CONTROL
 	select SUPPORT_SPL
 
 config TARGET_PEACH_PIT
 	bool "Peach Pit board"
+	select EXYNOS5_DT
+	select EXYNOS5420
 	select OF_CONTROL
 	select SUPPORT_SPL
 
@@ -189,6 +218,16 @@
 config SYS_SOC
 	default "exynos"
 
+config EXYNOS_ACE_SHA
+	bool "Advanced Crypto Engine SHA support"
+	depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && (LIB_HW_RAND || SHA_HW_ACCEL)
+	default y if ARCH_EXYNOS5
+
+config EXYNOS_TMU
+	bool "Exynos5 thermal management unit support"
+	depends on ARCH_EXYNOS5
+	default y
+
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index e895c13..dd097cf 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -10,8 +10,8 @@
 obj-$(CONFIG_EXYNOS5420)	+= sec_boot.o
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
-obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
+obj-$(CONFIG_ARCH_EXYNOS5)	+= clock_init_exynos5.o
+obj-$(CONFIG_ARCH_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
 obj-y	+= spl_boot.o tzpc.o
 obj-y	+= lowlevel_init.o
diff --git a/arch/arm/mach-exynos/dmc_init_exynos4.c b/arch/arm/mach-exynos/dmc_init_exynos4.c
index ecddc72..58a3c82 100644
--- a/arch/arm/mach-exynos/dmc_init_exynos4.c
+++ b/arch/arm/mach-exynos/dmc_init_exynos4.c
@@ -175,7 +175,7 @@
 	 * 0: full_sync
 	 */
 	writel(1, ASYNC_CONFIG);
-#ifdef CONFIG_ORIGEN
+#ifdef CONFIG_TARGET_ORIGEN
 	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 	writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
 		APB_SFR_INTERLEAVE_CONF_OFFSET);
diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h
index a08d64a..fbb45eb 100644
--- a/arch/arm/mach-exynos/exynos4_setup.h
+++ b/arch/arm/mach-exynos/exynos4_setup.h
@@ -420,7 +420,7 @@
 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET	0x828
 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET	0x830
 
-#ifdef CONFIG_ORIGEN
+#ifdef CONFIG_TARGET_ORIGEN
 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 #define APB_SFR_INTERLEAVE_CONF_VAL	0x20001507
 #define APB_SFR_ARBRITATION_CONF_VAL	0x00000001
@@ -542,7 +542,7 @@
 
 #define CONTROL2_VAL		0x00000000
 
-#ifdef CONFIG_ORIGEN
+#ifdef CONFIG_TARGET_ORIGEN
 #define TIMINGREF_VAL		0x000000BB
 #define TIMINGROW_VAL		0x4046654f
 #define	TIMINGDATA_VAL		0x46400506
diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c
index 2645a8f..1ff5fca 100644
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@@ -49,6 +49,10 @@
 };
 
 #ifdef CONFIG_EXYNOS5420
+
+/* Address for relocating helper code (Last 4 KB of IRAM) */
+#define EXYNOS_RELOCATE_CODE_BASE	(CONFIG_IRAM_TOP - 0x1000)
+
 /*
  * Power up secondary CPUs.
  */
@@ -56,7 +60,7 @@
 {
 	v7_enable_smp(EXYNOS5420_INFORM_BASE);
 	svc32_mode_en();
-	branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
+	branch_bx(EXYNOS_RELOCATE_CODE_BASE);
 }
 
 /*
@@ -153,7 +157,7 @@
 static void secondary_cores_configure(void)
 {
 	/* Clear secondary boot iRAM base */
-	writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
+	writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C));
 
 	/* set lowpower flag and address */
 	writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S
index 59d05e6..40c0720 100644
--- a/arch/arm/mach-exynos/sec_boot.S
+++ b/arch/arm/mach-exynos/sec_boot.S
@@ -21,7 +21,7 @@
 	.ltorg
 /*
  * Secondary core waits here until Primary wake it up.
- * Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
+ * Below code is copied to (CONFIG_IRAM_TOP - 0x1000)
  * This is a workaround code which is supposed to act as a
  * substitute/supplement to the iROM code.
  *