| commit | aa12d515e50d944ed856cdba00513e9de956b74e | [log] [tgz] |
|---|---|---|
| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | Wed Apr 08 21:34:54 2020 -0600 |
| committer | Michal Simek <michal.simek@xilinx.com> | Mon Apr 27 13:57:17 2020 +0200 |
| tree | 498ac555035d59437cb95c80cbf70399f3dc7e5e | |
| parent | 6b31a5b370dec4d66e6b6fd12ec4c71eb6916a15 [diff] |
clk: versal: Fix watchdog clock issue Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt driver. Skip reading clock rate for the mux based clocks with parent clock id is zero. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>