commit 891acfcaf925adb853441d55db526954791b13cb
author Kongyang Liu <seashell11234455@gmail.com> Tue Jun 11 17:41:16 2024 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Wed Sep 11 20:32:06 2024 +0800
tree f85fc4bfae352a673f5590b761b9a5123eca244c
parent 933ef11d00dfcf24c04af6c17ecad10ef686d286

riscv: dts: sophgo: Replace device clocks with real clocks.

Replace device clocks with real clocks from the clock controller, and
remove dummy clocks.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

arch/riscv/dts/cv18xx.dtsi

diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 4b01434..8a7386b 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo,cv1800.h>
 
 / {
 	#address-cells = <1>;
@@ -45,13 +46,6 @@
 		#clock-cells = <0>;
 	};
 
-	sdhci_clk: sdhci-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <375000000>;
-		clock-output-names = "sdhci_clk";
-		#clock-cells = <0>;
-	};
-
 	eth_csrclk: eth-csrclk {
 		compatible = "fixed-clock";
 		clock-frequency = <250000000>;
@@ -66,13 +60,6 @@
 		#clock-cells = <0x0>;
 	};
 
-	spif_clk: spi-flash-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <300000000>;
-		clock-output-names = "spif_clk";
-		#clock-cells = <0>;
-	};
-
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -163,8 +150,8 @@
 			compatible = "sophgo,cv1800b-dwmac";
 			reg = <0x04070000 0x10000>;
 			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&eth_csrclk>, <&eth_ptpclk>;
-			clock-names = "stmmaceth", "ptp_ref";
+			clocks = <&clk CLK_ETH0_500M>, <&clk CLK_AXI4_ETH0>;
+			clock-names = "stmmaceth", "pclk";
 			status = "disabled";
 		};
 
@@ -172,7 +159,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04140000 0x100>;
 			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
+			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -182,7 +170,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04150000 0x100>;
 			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
+			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -192,7 +181,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04160000 0x100>;
 			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
+			clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -202,7 +192,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x04170000 0x100>;
 			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
+			clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -212,7 +203,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x041c0000 0x100>;
 			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc>;
+			clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -222,8 +214,8 @@
 			compatible = "sophgo,cv1800b-dwcmshc";
 			reg = <0x4310000 0x1000>;
 			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sdhci_clk>;
-			clock-names = "core";
+			clocks = <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>;
+			clock-names = "core", "bus";
 			status = "disabled";
 		};
 
@@ -232,7 +224,7 @@
 			reg = <0x10000000 0x10000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			clocks = <&spif_clk>;
+			clocks = <&clk CLK_AHB_SF>;
 			interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};