global: Migrate CONFIG_FPGA_DELAY to CFG

Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY

Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index ca49ee4..4c00cdf 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -17,11 +17,11 @@
 
 /* Note: The assumption is that we cannot possibly run fast enough to
  * overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
  * the board config file to slow things down.
  */
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
 #endif
 
 #ifndef CFG_SYS_FPGA_WAIT
@@ -137,7 +137,7 @@
 		/* Wait for nSTATUS to be released (i.e. deasserted) */
 		ts = get_timer (0);		/* get current time */
 		do {
-			CONFIG_FPGA_DELAY ();
+			CFG_FPGA_DELAY ();
 			if (get_timer (ts) > CFG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for STATUS to go high.\n");
 				(*fn->abort) (cookie);
@@ -147,7 +147,7 @@
 		} while ((*fn->status) (cookie));
 
 		/* Get ready for the burn */
-		CONFIG_FPGA_DELAY ();
+		CFG_FPGA_DELAY ();
 
 		/* Load the data */
 		while (bytecount < bsize) {
@@ -172,13 +172,13 @@
 			do {
 				/* Deassert the clock */
 				(*fn->clk) (false, true, cookie);
-				CONFIG_FPGA_DELAY ();
+				CFG_FPGA_DELAY ();
 				/* Write data */
 				(*fn->data) ((val & 0x01), true, cookie);
-				CONFIG_FPGA_DELAY ();
+				CFG_FPGA_DELAY ();
 				/* Assert the clock */
 				(*fn->clk) (true, true, cookie);
-				CONFIG_FPGA_DELAY ();
+				CFG_FPGA_DELAY ();
 				val >>= 1;
 				i --;
 			} while (i > 0);
@@ -189,7 +189,7 @@
 #endif
 		}
 
-		CONFIG_FPGA_DELAY ();
+		CFG_FPGA_DELAY ();
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		putc (' ');			/* terminate the dotted line */
@@ -210,9 +210,9 @@
 	 */
 
 	for (i = 0; i < 12; i++) {
-		CONFIG_FPGA_DELAY ();
+		CFG_FPGA_DELAY ();
 		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
-		CONFIG_FPGA_DELAY ();
+		CFG_FPGA_DELAY ();
 		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 	}