tree 99fc160c852eac97a538530149068d9d7ba04d18
parent 53f42e845571c16ec8357a6f2d063b85940b8f3a
author Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com> 1739867690 +0800
committer Tom Rini <trini@konsulko.com> 1740502421 -0600

drivers: clk: agilex5: Set PLL to asynchronous mode

PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.

To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.

Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>