| commit | 4568296e3a1924a3c98a39136faf68d53abe94ea | [log] [tgz] |
|---|---|---|
| author | Stefan Agner <stefan.agner@toradex.com> | Wed Aug 03 13:08:55 2016 -0700 |
| committer | Tom Rini <trini@konsulko.com> | Fri Aug 12 09:22:15 2016 -0400 |
| tree | 0f33c7db11beb3a000cf119a7b8905b2597fbec0 | |
| parent | 70ab454503c6759ec5a0d7ddd1bdf4916e990e06 [diff] |
ARM: non-sec: flush code cacheline aligned Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>