diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h
new file mode 100644
index 0000000..6976e1f
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f1/gpio.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+enum stm32_gpio_port {
+	STM32_GPIO_PORT_A = 0,
+	STM32_GPIO_PORT_B,
+	STM32_GPIO_PORT_C,
+	STM32_GPIO_PORT_D,
+	STM32_GPIO_PORT_E,
+	STM32_GPIO_PORT_F,
+	STM32_GPIO_PORT_G,
+};
+
+enum stm32_gpio_pin {
+	STM32_GPIO_PIN_0 = 0,
+	STM32_GPIO_PIN_1,
+	STM32_GPIO_PIN_2,
+	STM32_GPIO_PIN_3,
+	STM32_GPIO_PIN_4,
+	STM32_GPIO_PIN_5,
+	STM32_GPIO_PIN_6,
+	STM32_GPIO_PIN_7,
+	STM32_GPIO_PIN_8,
+	STM32_GPIO_PIN_9,
+	STM32_GPIO_PIN_10,
+	STM32_GPIO_PIN_11,
+	STM32_GPIO_PIN_12,
+	STM32_GPIO_PIN_13,
+	STM32_GPIO_PIN_14,
+	STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_icnf {
+	STM32_GPIO_ICNF_AN = 0,
+	STM32_GPIO_ICNF_IN_FLT,
+	STM32_GPIO_ICNF_IN_PUD,
+	STM32_GPIO_ICNF_RSVD
+};
+
+enum stm32_gpio_ocnf {
+	STM32_GPIO_OCNF_GP_PP = 0,
+	STM32_GPIO_OCNF_GP_OD,
+	STM32_GPIO_OCNF_AF_PP,
+	STM32_GPIO_OCNF_AF_OD
+};
+
+enum stm32_gpio_pupd {
+	STM32_GPIO_PUPD_DOWN = 0,
+	STM32_GPIO_PUPD_UP,
+};
+
+enum stm32_gpio_mode {
+	STM32_GPIO_MODE_IN = 0,
+	STM32_GPIO_MODE_OUT_10M,
+	STM32_GPIO_MODE_OUT_2M,
+	STM32_GPIO_MODE_OUT_50M
+};
+
+enum stm32_gpio_af {
+	STM32_GPIO_AF0 = 0,
+	STM32_GPIO_AF1,
+	STM32_GPIO_AF2,
+	STM32_GPIO_AF3,
+	STM32_GPIO_AF4,
+	STM32_GPIO_AF5,
+	STM32_GPIO_AF6,
+	STM32_GPIO_AF7,
+	STM32_GPIO_AF8,
+	STM32_GPIO_AF9,
+	STM32_GPIO_AF10,
+	STM32_GPIO_AF11,
+	STM32_GPIO_AF12,
+	STM32_GPIO_AF13,
+	STM32_GPIO_AF14,
+	STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+	enum stm32_gpio_port	port;
+	enum stm32_gpio_pin	pin;
+};
+
+struct stm32_gpio_ctl {
+	enum stm32_gpio_icnf	icnf;
+	enum stm32_gpio_ocnf	ocnf;
+	enum stm32_gpio_mode	mode;
+	enum stm32_gpio_pupd	pupd;
+	enum stm32_gpio_af	af;
+};
+
+static inline unsigned stm32_gpio_to_port(unsigned gpio)
+{
+	return gpio / 16;
+}
+
+static inline unsigned stm32_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 16;
+}
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
+		const struct stm32_gpio_ctl *gpio_ctl);
+int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h
new file mode 100644
index 0000000..686cb4f
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f1/stm32.h
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * Copyright 2015 ATS Advanced Telematics Systems GmbH
+ * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ */
+#define STM32_PERIPH_BASE	0x40000000
+#define STM32_APB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00000000)
+#define STM32_APB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00018000)
+
+#define STM32_BUS_MASK		0xFFFF0000
+
+/*
+ * Register maps
+ */
+struct stm32_des_regs {
+	u16 flash_size;
+	u16 pad1;
+	u32 pad2;
+	u32 uid0;
+	u32 uid1;
+	u32 uid2;
+};
+
+struct stm32_rcc_regs {
+	u32 cr;		/* RCC clock control */
+	u32 cfgr;	/* RCC clock configuration */
+	u32 cir;	/* RCC clock interrupt */
+	u32 apb2rstr;	/* RCC APB2 peripheral reset */
+	u32 apb1rstr;	/* RCC APB1 peripheral reset */
+	u32 ahbenr;	/* RCC AHB peripheral clock enable */
+	u32 apb2enr;	/* RCC APB2 peripheral clock enable */
+	u32 apb1enr;	/* RCC APB1 peripheral clock enable */
+	u32 bdcr;	/* RCC Backup domain control */
+	u32 csr;	/* RCC clock control & status */
+};
+
+struct stm32_pwr_regs {
+	u32 cr;
+	u32 csr;
+};
+
+struct stm32_flash_regs {
+	u32 acr;
+	u32 keyr;
+	u32 optkeyr;
+	u32 sr;
+	u32 cr;
+	u32 ar;
+	u32 rsvd1;	/* Reserved */
+	u32 obr;
+	u32 wrpr;
+	u32 rsvd2[8];	/* Reserved */
+	u32 keyr2;
+	u32 rsvd3;
+	u32 sr2;
+	u32 cr2;
+	u32 ar2;
+};
+
+/* Per bank register set for XL devices */
+struct stm32_flash_bank_regs {
+	u32 keyr;
+	u32 rsvd;	/* Reserved */
+	u32 sr;
+	u32 cr;
+	u32 ar;
+};
+
+/*
+ * Registers access macros
+ */
+#define STM32_DES_BASE		(0x1ffff7e0)
+#define STM32_DES		((struct stm32_des_regs *)STM32_DES_BASE)
+
+#define STM32_RCC_BASE		(STM32_AHB1PERIPH_BASE + 0x9000)
+#define STM32_RCC		((struct stm32_rcc_regs *)STM32_RCC_BASE)
+
+#define STM32_PWR_BASE		(STM32_APB1PERIPH_BASE + 0x7000)
+#define STM32_PWR		((struct stm32_pwr_regs *)STM32_PWR_BASE)
+
+#define STM32_FLASH_BASE	(STM32_AHB1PERIPH_BASE + 0xa000)
+#define STM32_FLASH		((struct stm32_flash_regs *)STM32_FLASH_BASE)
+
+#define STM32_FLASH_SR_BSY		(1 << 0)
+
+#define STM32_FLASH_CR_PG		(1 << 0)
+#define STM32_FLASH_CR_PER		(1 << 1)
+#define STM32_FLASH_CR_STRT		(1 << 6)
+#define STM32_FLASH_CR_LOCK		(1 << 7)
+
+enum clock {
+	CLOCK_CORE,
+	CLOCK_AHB,
+	CLOCK_APB1,
+	CLOCK_APB2
+};
+
+int configure_clocks(void);
+unsigned long clock_get(enum clock clck);
+
+#endif /* _MACH_STM32_H_ */