| commit | 883c503619a14f8598f64b90a8bad676e3793bee | [log] [tgz] |
|---|---|---|
| author | Dinesh Maniyam <dinesh.maniyam@intel.com> | Fri Dec 15 15:15:19 2023 +0800 |
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | Mon Jan 22 16:51:17 2024 +0800 |
| tree | 470ce4a501d7b16c7811df9736d72aecef27044a | |
| parent | c851f2fff11c2132a95ab47219cea95727a8b8d8 [diff] |
clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0) MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation but it is wrongly defined as BIT[7] in u-boot code. This register is used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>