tree dbc36687d503021b3773c097b0de59c7ed0beb70
parent 7dd2aaf022ce5afc9f1d58328c05ce85fd059a27
author Peng Fan <peng.fan@nxp.com> 1515561622 +0800
committer Stefano Babic <sbabic@denx.de> 1517742058 +0100

imx: mx8m: add clock driver

Add clock driver to support i.MX8M.

There are two kind PLLs, FRAC pll and SSCG pll. ROM already
configured SYS PLL1/2, we only need to configure the output.
ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
enet clock are configured in the code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>