diff --git a/.travis.yml b/.travis.yml
index 0b7a062..8a220cc 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -206,7 +206,11 @@
     - env:
         - BUILDMAN="mpc85xx -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x sbc8548 -x bsc91*"
     - env:
-        - BUILDMAN="t208xrdb t4qds t102*"
+        - BUILDMAN="t208xrdb"
+    - env:
+        - BUILDMAN="t4qds"
+    - env:
+        - BUILDMAN="t102*"
     - env:
         - BUILDMAN="p1_p2_rdb_pc"
     - env:
diff --git a/MAINTAINERS b/MAINTAINERS
index e950267..9b4b63b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -488,6 +488,13 @@
 T:	git git://git.denx.de/u-boot-usb.git topic-xhci
 F:	drivers/usb/host/xhci*
 
+ROCKUSB
+M:	Eddie Cai <eddie.cai.linux@gmail.com>
+S:	Maintained
+F:	drivers/usb/gadget/f_rockusb.c
+F:	cmd/rockusb.c
+F:	doc/README.rockusb
+
 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f2c35e3..de323bf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -122,6 +122,9 @@
 config ARM_ERRATA_852423
 	bool
 
+config ARM_ERRATA_855873
+	bool
+
 config CPU_ARM720T
 	bool
 	select SYS_CACHE_SHIFT_5
diff --git a/arch/arm/cpu/arm1136/mx31/Makefile b/arch/arm/cpu/arm1136/mx31/Makefile
index dcbd570..774f352 100644
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
@@ -8,7 +8,4 @@
 obj-y	+= generic.o
 obj-y	+= timer.o
 obj-y	+= devices.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y  += relocate.o
-endif
+obj-y	+= relocate.o
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index 796db9c..e4c8e2e 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -10,7 +10,4 @@
 obj-y	+= generic.o
 obj-y	+= timer.o
 obj-y	+= mx35_sdram.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y  += relocate.o
-endif
+obj-y	+= relocate.o
diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index ebc0407..7d608c6 100644
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -4,8 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-obj-y	= generic.o timer.o reset.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y	+= relocate.o
-endif
+obj-y	+= generic.o timer.o reset.o relocate.o
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile
index 0edf144..7d608c6 100644
--- a/arch/arm/cpu/arm926ejs/mx27/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx27/Makefile
@@ -4,8 +4,4 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 
-obj-y	= generic.o reset.o timer.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y	+= relocate.o
-endif
+obj-y	+= generic.o timer.o reset.o relocate.o
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 95a0b52..7e26957 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -239,55 +239,47 @@
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_454179
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_454179
+	orrlt	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_454179:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_430973
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_430973
+	orrlt	r0, r0, #(0x1 << 6)	@ Set IBE bit
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_430973:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_621766
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_621766
+	orrlt	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_621766:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_725233
+	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1 (Cortex A8)
-	bge	skip_errata_725233
+	orrlt	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
 
-	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
-	orr	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_l2aux_ctrl
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_725233:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_852421
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6c03dfb..cefbdfe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,6 +1,7 @@
 config ARCH_LS1012A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_855873
 	select FSL_LSCH2
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_MMDC
@@ -16,6 +17,7 @@
 config ARCH_LS1043A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_855873
 	select FSL_LSCH2
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
@@ -68,6 +70,7 @@
 config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
+	select ARM_ERRATA_855873
 	select FSL_LSCH3
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
@@ -493,8 +496,7 @@
 config SYS_MC_RSV_MEM_ALIGN
 	hex "Management Complex reserved memory alignment"
 	depends on RESV_RAM
-	default 0x20000000 if ARCH_LS2080A
-	default 0x70000000 if ARCH_LS1088A
+	default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
 	help
 	  Reserved memory needs to be aligned for MC to use. Default value
 	  is 512MB.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 115c3fc..0cb6d4e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,8 +7,10 @@
 obj-y += cpu.o
 obj-y += lowlevel.o
 obj-y += soc.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+endif
 obj-$(CONFIG_SPL) += spl.o
 obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 00d2564..1e0030c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -30,6 +30,7 @@
 #endif
 #include <asm/arch/clock.h>
 #include <hwconfig.h>
+#include <fsl_qbman.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -565,6 +566,9 @@
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_qbman_portals();
+#endif
 	return 0;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 39ffe1a..80af318 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -26,6 +26,8 @@
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
+#include <asm/arch/speed.h>
+#include <fsl_qbman.h>
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -442,6 +444,13 @@
 	fdt_fixup_esdhc(blob, bd);
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	fdt_fixup_bportals(blob);
+	fdt_fixup_qportals(blob);
+	do_fixup_by_compat_u32(blob, "fsl,qman",
+			       "clock-frequency", get_qman_freq(), 1);
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 2d7775e..5f23aad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -155,7 +155,21 @@
 	sys_info->freq_localbus = sys_info->freq_systembus /
 						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sys_info->freq_qman = sys_info->freq_systembus;
+#endif
+}
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+	struct sys_info sys_info;
+
+	get_sys_info(&sys_info);
+
+	return sys_info.freq_qman;
 }
+#endif
 
 int get_clocks(void)
 {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ae57c0e..dc4a437 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -341,6 +341,8 @@
 #ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -348,6 +350,8 @@
 #ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -368,6 +372,8 @@
 	/* Disable SATA ECC */
 	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 03e744e..f385ed4 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -196,7 +196,10 @@
 WEAK(apply_core_errata)
 
 	mov	x29, lr			/* Save LR */
-	/* For now, we support Cortex-A57 specific errata only */
+	/* For now, we support Cortex-A53, Cortex-A57 specific errata */
+
+	/* Check if we are running on a Cortex-A53 core */
+	branch_if_a53_core x0, apply_a53_core_errata
 
 	/* Check if we are running on a Cortex-A57 core */
 	branch_if_a57_core x0, apply_a57_core_errata
@@ -204,6 +207,25 @@
 	mov	lr, x29			/* Restore LR */
 	ret
 
+apply_a53_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_855873
+	mrs	x0, midr_el1
+	tst	x0, #(0xf << 20)
+	b.ne	0b
+
+	mrs	x0, midr_el1
+	and	x0, x0, #0xf
+	cmp	x0, #3
+	b.lt	0b
+
+	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
+	/* Enable data cache clean as data cache clean/invalidate */
+	orr	x0, x0, #1 << 44
+	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
+#endif
+	b 0b
+
 apply_a57_core_errata:
 
 #ifdef CONFIG_ARM_ERRATA_828024
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a895c70..f10482e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -213,6 +213,9 @@
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
+dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
+	stm32f469-disco.dtb
+
 dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
 	stm32f769-disco.dtb
 dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts
index 5e1588d..d4d127f 100644
--- a/arch/arm/dts/armada-385-amc.dts
+++ b/arch/arm/dts/armada-385-amc.dts
@@ -53,7 +53,7 @@
 
 	aliases {
 		ethernet0 = &eth0;
-		ethernet1 = &eth1;
+		ethernet1 = &eth2;
 		i2c0 = &i2c0;
 		spi1 = &spi1;
 	};
diff --git a/arch/arm/dts/bcm283x.dtsi b/arch/arm/dts/bcm283x.dtsi
index 05a6f48..e45ba58 100644
--- a/arch/arm/dts/bcm283x.dtsi
+++ b/arch/arm/dts/bcm283x.dtsi
@@ -246,7 +246,7 @@
 
 			jtag_gpio4: jtag_gpio4 {
 				brcm,pins = <4 5 6 12 13>;
-				brcm,function = <BCM2835_FSEL_ALT4>;
+				brcm,function = <BCM2835_FSEL_ALT5>;
 			};
 			jtag_gpio22: jtag_gpio22 {
 				brcm,pins = <22 23 24 25 26 27>;
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
index dde7134..d17cd99 100644
--- a/arch/arm/dts/fsl-ls1012a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -121,3 +121,8 @@
 &duart0 {
 	status = "okay";
 };
+
+&usb0 {
+	status = "okay";
+	phy_type = "ulpi";
+};
diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi
new file mode 100644
index 0000000..736bca7
--- /dev/null
+++ b/arch/arm/dts/stm32f4-pinctrl.dtsi
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x40020000 0x3000>;
+			interrupt-parent = <&exti>;
+			st,syscfg = <&syscfg 0x8>;
+			pins-are-numbered;
+
+			gpioa: gpio@40020000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x0 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
+				st,bank-name = "GPIOA";
+			};
+
+			gpiob: gpio@40020400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x400 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
+				st,bank-name = "GPIOB";
+			};
+
+			gpioc: gpio@40020800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x800 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
+				st,bank-name = "GPIOC";
+			};
+
+			gpiod: gpio@40020c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0xc00 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
+				st,bank-name = "GPIOD";
+			};
+
+			gpioe: gpio@40021000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1000 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
+				st,bank-name = "GPIOE";
+			};
+
+			gpiof: gpio@40021400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1400 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
+				st,bank-name = "GPIOF";
+			};
+
+			gpiog: gpio@40021800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1800 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
+				st,bank-name = "GPIOG";
+			};
+
+			gpioh: gpio@40021c00 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x1c00 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
+				st,bank-name = "GPIOH";
+			};
+
+			gpioi: gpio@40022000 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x2000 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
+				st,bank-name = "GPIOI";
+			};
+
+			gpioj: gpio@40022400 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x2400 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
+				st,bank-name = "GPIOJ";
+			};
+
+			gpiok: gpio@40022800 {
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0x2800 0x400>;
+				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
+				st,bank-name = "GPIOK";
+			};
+
+			usart1_pins_a: usart1@0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
+					bias-disable;
+				};
+			};
+
+			usart3_pins_a: usart3@0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <0>;
+				};
+				pins2 {
+					pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
+					bias-disable;
+				};
+			};
+
+			usbotg_fs_pins_a: usbotg_fs@0 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
+						 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
+						 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			usbotg_fs_pins_b: usbotg_fs@1 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
+						 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
+						 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			usbotg_hs_pins_a: usbotg_hs@0 {
+				pins {
+					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
+						 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			ethernet_mii: mii@0 {
+				pins {
+					pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
+						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
+						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
+						 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
+						 <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
+						 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
+						 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+						 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
+						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
+						 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
+						 <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
+						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
+						 <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
+						 <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
+					slew-rate = <2>;
+				};
+			};
+
+			adc3_in8_pin: adc@200 {
+				pins {
+					pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
+				};
+			};
+
+			pwm1_pins: pwm@1 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
+						 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
+						 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
+				};
+			};
+
+			pwm3_pins: pwm@3 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
+						 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
+				};
+			};
+
+			i2c1_pins: i2c1@0 {
+				pins {
+					pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
+						 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
+					bias-disable;
+					drive-open-drain;
+					slew-rate = <3>;
+				};
+			};
+
+			ltdc_pins: ltdc@0 {
+				pins {
+					pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+						 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+						 <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+						 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+						 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+						 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+						 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+						 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+						 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+						 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
+						 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+						 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+						 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+						 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+						 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+						 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+						 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+						 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+						 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+						 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
+						 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+						 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+						 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+						 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
+						 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+						 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+						 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
+						 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
+					slew-rate = <2>;
+				};
+			};
+
+			dcmi_pins: dcmi@0 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
+						 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
+						 <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
+						 <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
+						 <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
+						 <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
+						 <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
+						 <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
+						 <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
+						 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
+						 <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
+						 <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
+						 <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
+						 <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
+						 <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <3>;
+				};
+			};
+
+			sdio_pins: sdio_pins@0 {
+				pins {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>,
+						 <STM32_PINMUX('C', 9, AF12)>,
+						 <STM32_PINMUX('C', 10, AF12)>,
+						 <STM32_PINMUX('c', 11, AF12)>,
+						 <STM32_PINMUX('C', 12, AF12)>,
+						 <STM32_PINMUX('D', 2, AF12)>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od: sdio_pins_od@0 {
+				pins1 {
+					pinmux = <STM32_PINMUX('C', 8, AF12)>,
+						 <STM32_PINMUX('C', 9, AF12)>,
+						 <STM32_PINMUX('C', 10, AF12)>,
+						 <STM32_PINMUX('C', 11, AF12)>,
+						 <STM32_PINMUX('C', 12, AF12)>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32_PINMUX('D', 2, AF12)>;
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
new file mode 100644
index 0000000..59dda43
--- /dev/null
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+	clocks {
+		u-boot,dm-pre-reloc;
+	};
+
+	aliases {
+		/* Aliases for gpios so as to use sequence */
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+		pin-controller {
+			u-boot,dm-pre-reloc;
+		};
+
+		fmc: fmc@A0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xA0000000 0x1000>;
+			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+			pinctrl-0 = <&fmc_pins>;
+			pinctrl-names = "default";
+			u-boot,dm-pre-reloc;
+
+			/*
+			 * Memory configuration from sdram datasheet
+			 * IS42S16400J
+			 */
+			bank1: bank@1 {
+			       st,sdram-control = /bits/ 8 <NO_COL_8
+							    NO_ROW_12
+							    MWIDTH_16
+							    BANKS_4
+							    CAS_3
+							    SDCLK_2
+							    RD_BURST_EN
+							    RD_PIPE_DL_0>;
+			       st,sdram-timing = /bits/ 8 <TMRD_3
+							   TXSR_7
+							   TRAS_4
+							   TRC_6
+							   TWR_2
+							   TRP_2 TRCD_2>;
+			       st,sdram-refcount = < 1386 >;
+		       };
+		};
+	};
+};
+
+&clk_hse {
+	u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+	u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+	u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	usart1_pins_a: usart1@0	{
+		u-boot,dm-pre-reloc;
+		pins1 {
+			u-boot,dm-pre-reloc;
+		};
+		pins2 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	fmc_pins: fmc@0 {
+		u-boot,dm-pre-reloc;
+		pins
+		{
+			pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
+				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
+				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
+				 <STM32_PINMUX('E',12, AF12)>, /* D09 */
+				 <STM32_PINMUX('E',11, AF12)>, /* D08 */
+				 <STM32_PINMUX('E',10, AF12)>, /* D07 */
+				 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+				 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+				 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+				 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+				 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+				 <STM32_PINMUX('D',15, AF12)>, /* D01 */
+				 <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+
+				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+				 <STM32_PINMUX('F',15, AF12)>, /* A09 */
+				 <STM32_PINMUX('F',14, AF12)>, /* A08 */
+				 <STM32_PINMUX('F',13, AF12)>, /* A07 */
+				 <STM32_PINMUX('F',12, AF12)>, /* A06 */
+				 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+				 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+				 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+				 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+				 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+				 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+				 <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
+				 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+				 <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
+				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
+			slew-rate = <2>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts
new file mode 100644
index 0000000..e914b6b
--- /dev/null
+++ b/arch/arm/dts/stm32f429-disco.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author(s):  Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f429-pinctrl.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "STMicroelectronics STM32F429i-DISCO board";
+	compatible = "st,stm32f429i-disco", "st,stm32f429";
+
+	chosen {
+		bootargs = "root=/dev/ram";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x90000000 0x800000>;
+	};
+
+	aliases {
+		serial0 = &usart1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		red {
+			gpios = <&gpiog 14 0>;
+		};
+		green {
+			gpios = <&gpiog 13 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		autorepeat;
+		button@0 {
+			label = "User";
+			linux,code = <KEY_HOME>;
+			gpios = <&gpioa 0 0>;
+		};
+	};
+
+	/* This turns on vbus for otg for host mode (dwc2) */
+	vcc5v_otg: vcc5v-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpioc 4 0>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <8000000>;
+};
+
+&crc {
+	status = "okay";
+};
+
+&rtc {
+	assigned-clocks = <&rcc 1 CLK_RTC>;
+	assigned-clock-parents = <&rcc 1 CLK_LSI>;
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbotg_hs {
+	compatible = "st,stm32f4x9-fsotg";
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_b>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi
new file mode 100644
index 0000000..77246b3
--- /dev/null
+++ b/arch/arm/dts/stm32f429-pinctrl.dtsi
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			compatible = "st,stm32f429-pinctrl";
+
+			gpioa: gpio@40020000 {
+				gpio-ranges = <&pinctrl 0 0 16>;
+			};
+
+			gpiob: gpio@40020400 {
+				gpio-ranges = <&pinctrl 0 16 16>;
+			};
+
+			gpioc: gpio@40020800 {
+				gpio-ranges = <&pinctrl 0 32 16>;
+			};
+
+			gpiod: gpio@40020c00 {
+				gpio-ranges = <&pinctrl 0 48 16>;
+			};
+
+			gpioe: gpio@40021000 {
+				gpio-ranges = <&pinctrl 0 64 16>;
+			};
+
+			gpiof: gpio@40021400 {
+				gpio-ranges = <&pinctrl 0 80 16>;
+			};
+
+			gpiog: gpio@40021800 {
+				gpio-ranges = <&pinctrl 0 96 16>;
+			};
+
+			gpioh: gpio@40021c00 {
+				gpio-ranges = <&pinctrl 0 112 16>;
+			};
+
+			gpioi: gpio@40022000 {
+				gpio-ranges = <&pinctrl 0 128 16>;
+			};
+
+			gpioj: gpio@40022400 {
+				gpio-ranges = <&pinctrl 0 144 16>;
+			};
+
+			gpiok: gpio@40022800 {
+				gpio-ranges = <&pinctrl 0 160 8>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi
new file mode 100644
index 0000000..6bcf986
--- /dev/null
+++ b/arch/arm/dts/stm32f429.dtsi
@@ -0,0 +1,711 @@
+/*
+ * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
+ * Author(s):  Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/clock/stm32fx-clock.h>
+#include <dt-bindings/mfd/stm32f4-rcc.h>
+
+/ {
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+		};
+
+		clk_i2s_ckin: i2s-ckin {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
+		};
+	};
+
+	soc {
+		timer2: timer@40000000 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000000 0x400>;
+			interrupts = <28>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
+			status = "disabled";
+		};
+
+		timers2: timers@40000000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000000 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@1 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <1>;
+				status = "disabled";
+			};
+		};
+
+		timer3: timer@40000400 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000400 0x400>;
+			interrupts = <29>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
+			status = "disabled";
+		};
+
+		timers3: timers@40000400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000400 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@2 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <2>;
+				status = "disabled";
+			};
+		};
+
+		timer4: timer@40000800 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000800 0x400>;
+			interrupts = <30>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
+			status = "disabled";
+		};
+
+		timers4: timers@40000800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@3 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <3>;
+				status = "disabled";
+			};
+		};
+
+		timer5: timer@40000c00 {
+			compatible = "st,stm32-timer";
+			reg = <0x40000c00 0x400>;
+			interrupts = <50>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
+		};
+
+		timers5: timers@40000c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40000C00 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@4 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <4>;
+				status = "disabled";
+			};
+		};
+
+		timer6: timer@40001000 {
+			compatible = "st,stm32-timer";
+			reg = <0x40001000 0x400>;
+			interrupts = <54>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
+			status = "disabled";
+		};
+
+		timers6: timers@40001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001000 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
+			clock-names = "int";
+			status = "disabled";
+
+			timer@5 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <5>;
+				status = "disabled";
+			};
+		};
+
+		timer7: timer@40001400 {
+			compatible = "st,stm32-timer";
+			reg = <0x40001400 0x400>;
+			interrupts = <55>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
+			status = "disabled";
+		};
+
+		timers7: timers@40001400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001400 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
+			clock-names = "int";
+			status = "disabled";
+
+			timer@6 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <6>;
+				status = "disabled";
+			};
+		};
+
+		timers12: timers@40001800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001800 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@11 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <11>;
+				status = "disabled";
+			};
+		};
+
+		timers13: timers@40001c00 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40001C00 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+		};
+
+		timers14: timers@40002000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 0x400>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+		};
+
+		rtc: rtc@40002800 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40002800 0x400>;
+			clocks = <&rcc 1 CLK_RTC>;
+			clock-names = "ck_rtc";
+			assigned-clocks = <&rcc 1 CLK_RTC>;
+			assigned-clock-parents = <&rcc 1 CLK_LSE>;
+			interrupt-parent = <&exti>;
+			interrupts = <17 1>;
+			interrupt-names = "alarm";
+			st,syscfg = <&pwrcfg>;
+			status = "disabled";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-iwdg";
+			reg = <0x40003000 0x400>;
+			clocks = <&clk_lsi>;
+			status = "disabled";
+		};
+
+		usart2: serial@40004400 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
+			status = "disabled";
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
+			status = "disabled";
+			dmas = <&dma1 1 4 0x400 0x0>,
+			       <&dma1 3 4 0x400 0x0>;
+			dma-names = "rx", "tx";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
+			status = "disabled";
+		};
+
+		usart5: serial@40005000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40005000 0x400>;
+			interrupts = <53>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32f4-i2c";
+			reg = <0x40005400 0x400>;
+			interrupts = <31>,
+				     <32>;
+			resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		dac: dac@40007400 {
+			compatible = "st,stm32f4-dac-core";
+			reg = <0x40007400 0x400>;
+			resets = <&rcc STM32F4_APB1_RESET(DAC)>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
+			clock-names = "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			dac1: dac@1 {
+				compatible = "st,stm32-dac";
+				#io-channels-cells = <1>;
+				reg = <1>;
+				status = "disabled";
+			};
+
+			dac2: dac@2 {
+				compatible = "st,stm32-dac";
+				#io-channels-cells = <1>;
+				reg = <2>;
+				status = "disabled";
+			};
+		};
+
+		usart7: serial@40007800 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007800 0x400>;
+			interrupts = <82>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
+			status = "disabled";
+		};
+
+		usart8: serial@40007c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40007c00 0x400>;
+			interrupts = <83>;
+			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
+			status = "disabled";
+		};
+
+		timers1: timers@40010000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@0 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <0>;
+				status = "disabled";
+			};
+		};
+
+		timers8: timers@40010400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40010400 0x400>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@7 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <7>;
+				status = "disabled";
+			};
+		};
+
+		usart1: serial@40011000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011000 0x400>;
+			interrupts = <37>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
+			status = "disabled";
+			dmas = <&dma2 2 4 0x400 0x0>,
+			       <&dma2 7 4 0x400 0x0>;
+			dma-names = "rx", "tx";
+		};
+
+		usart6: serial@40011400 {
+			compatible = "st,stm32-uart";
+			reg = <0x40011400 0x400>;
+			interrupts = <71>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
+			status = "disabled";
+		};
+
+		adc: adc@40012000 {
+			compatible = "st,stm32f4-adc-core";
+			reg = <0x40012000 0x400>;
+			interrupts = <18>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
+			clock-names = "adc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			adc1: adc@0 {
+				compatible = "st,stm32f4-adc";
+				#io-channel-cells = <1>;
+				reg = <0x0>;
+				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
+				interrupt-parent = <&adc>;
+				interrupts = <0>;
+				dmas = <&dma2 0 0 0x400 0x0>;
+				dma-names = "rx";
+				status = "disabled";
+			};
+
+			adc2: adc@100 {
+				compatible = "st,stm32f4-adc";
+				#io-channel-cells = <1>;
+				reg = <0x100>;
+				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
+				interrupt-parent = <&adc>;
+				interrupts = <1>;
+				dmas = <&dma2 3 1 0x400 0x0>;
+				dma-names = "rx";
+				status = "disabled";
+			};
+
+			adc3: adc@200 {
+				compatible = "st,stm32f4-adc";
+				#io-channel-cells = <1>;
+				reg = <0x200>;
+				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
+				interrupt-parent = <&adc>;
+				interrupts = <2>;
+				dmas = <&dma2 1 2 0x400 0x0>;
+				dma-names = "rx";
+				status = "disabled";
+			};
+		};
+
+		syscfg: system-config@40013800 {
+			compatible = "syscon";
+			reg = <0x40013800 0x400>;
+		};
+
+		exti: interrupt-controller@40013c00 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x40013C00 0x400>;
+			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
+		};
+
+		timers9: timers@40014000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+
+			timer@8 {
+				compatible = "st,stm32-timer-trigger";
+				reg = <8>;
+				status = "disabled";
+			};
+		};
+
+		timers10: timers@40014400 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40014400 0x400>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+		};
+
+		timers11: timers@40014800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "st,stm32-timers";
+			reg = <0x40014800 0x400>;
+			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
+			clock-names = "int";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+			};
+		};
+
+		pwrcfg: power-config@40007000 {
+			compatible = "syscon";
+			reg = <0x40007000 0x400>;
+		};
+
+		sdio: sdio@40012c00 {
+			compatible = "st,stm32f4xx-sdio";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc 0 171>;
+			interrupts = <49>;
+			status = "disabled";
+			pinctrl-0 = <&sdio_pins>;
+			pinctrl-1 = <&sdio_pins_od>;
+			pinctrl-names = "default", "opendrain";
+			max-frequency = <48000000>;
+		};
+
+		ltdc: display-controller@40016800 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x40016800 0x200>;
+			interrupts = <88>, <89>;
+			resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+			clocks = <&rcc 1 CLK_LCD>;
+			clock-names = "lcd";
+			status = "disabled";
+		};
+
+		crc: crc@40023000 {
+			compatible = "st,stm32f4-crc";
+			reg = <0x40023000 0x400>;
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
+			status = "disabled";
+		};
+
+		rcc: rcc@40023810 {
+			#reset-cells = <1>;
+			#clock-cells = <2>;
+			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+			reg = <0x40023800 0x400>;
+			clocks = <&clk_hse>, <&clk_i2s_ckin>;
+			st,syscfg = <&pwrcfg>;
+			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
+			assigned-clock-rates = <1000000>;
+		};
+
+		dma1: dma-controller@40026000 {
+			compatible = "st,stm32-dma";
+			reg = <0x40026000 0x400>;
+			interrupts = <11>,
+				     <12>,
+				     <13>,
+				     <14>,
+				     <15>,
+				     <16>,
+				     <17>,
+				     <47>;
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
+			#dma-cells = <4>;
+		};
+
+		dma2: dma-controller@40026400 {
+			compatible = "st,stm32-dma";
+			reg = <0x40026400 0x400>;
+			interrupts = <56>,
+				     <57>,
+				     <58>,
+				     <59>,
+				     <60>,
+				     <68>,
+				     <69>,
+				     <70>;
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
+			#dma-cells = <4>;
+			st,mem2mem;
+		};
+
+		mac: ethernet@40028000 {
+			compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+			reg = <0x40028000 0x8000>;
+			reg-names = "stmmaceth";
+			interrupts = <61>;
+			interrupt-names = "macirq";
+			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
+					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
+					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
+			st,syscon = <&syscfg 0x4>;
+			snps,pbl = <8>;
+			snps,mixed-burst;
+			status = "disabled";
+		};
+
+		usbotg_hs: usb@40040000 {
+			compatible = "snps,dwc2";
+			reg = <0x40040000 0x40000>;
+			interrupts = <77>;
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
+			clock-names = "otg";
+			status = "disabled";
+		};
+
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32f4x9-fsotg";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67>;
+			clocks = <&rcc 0 39>;
+			clock-names = "otg";
+			status = "disabled";
+		};
+
+		dcmi: dcmi@50050000 {
+			compatible = "st,stm32-dcmi";
+			reg = <0x50050000 0x400>;
+			interrupts = <78>;
+			resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
+			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
+			clock-names = "mclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&dcmi_pins>;
+			dmas = <&dma2 1 1 0x414 0x3>;
+			dma-names = "tx";
+			status = "disabled";
+		};
+
+		rng: rng@50060800 {
+			compatible = "st,stm32-rng";
+			reg = <0x50060800 0x400>;
+			interrupts = <80>;
+			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
+
+		};
+	};
+};
+
+&systick {
+	clocks = <&rcc 1 SYSTICK>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
new file mode 100644
index 0000000..094bab4
--- /dev/null
+++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+	clocks {
+		u-boot,dm-pre-reloc;
+	};
+
+	aliases {
+		/* Aliases for gpios so as to use sequence */
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+		pin-controller {
+			u-boot,dm-pre-reloc;
+		};
+
+		fmc: fmc@A0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xA0000000 0x1000>;
+			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+			st,syscfg = <&syscfg>;
+			pinctrl-0 = <&fmc_pins_d32>;
+			pinctrl-names = "default";
+			st,mem_remap = <4>;
+			u-boot,dm-pre-reloc;
+
+			/*
+			 * Memory configuration from sdram
+			 * MICRON MT48LC4M32B2B5-6A
+			 */
+			bank0: bank@0 {
+			       st,sdram-control = /bits/ 8 <NO_COL_8
+							    NO_ROW_12
+							    MWIDTH_32
+							    BANKS_4
+							    CAS_3
+							    SDCLK_2
+							    RD_BURST_EN
+							    RD_PIPE_DL_0>;
+			       st,sdram-timing = /bits/ 8 <TMRD_2
+							   TXSR_6
+							   TRAS_4
+							   TRC_6
+							   TWR_2
+							   TRP_2
+							   TRCD_2>;
+			       st,sdram-refcount = < 1292 >;
+		       };
+		};
+	};
+};
+
+&clk_hse {
+	u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+	u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+	u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&syscfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	usart3_pins_a: usart3@0	{
+		u-boot,dm-pre-reloc;
+		pins1 {
+			u-boot,dm-pre-reloc;
+		};
+		pins2 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	fmc_pins_d32: fmc_d32@0 {
+		u-boot,dm-pre-reloc;
+		pins
+		{
+			pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
+				 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
+				 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
+				 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
+				 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
+				 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
+				 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
+				 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
+				 <STM32_PINMUX('H',15, AF12)>, /* D23 */
+				 <STM32_PINMUX('H',14, AF12)>, /* D22 */
+				 <STM32_PINMUX('H',13, AF12)>, /* D21 */
+				 <STM32_PINMUX('H',12, AF12)>, /* D20 */
+				 <STM32_PINMUX('H',11, AF12)>, /* D19 */
+				 <STM32_PINMUX('H',10, AF12)>, /* D18 */
+				 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
+				 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
+
+				 <STM32_PINMUX('D',10, AF12)>, /* D15 */
+				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
+				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
+				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
+				 <STM32_PINMUX('E',12, AF12)>, /* D09 */
+				 <STM32_PINMUX('E',11, AF12)>, /* D08 */
+				 <STM32_PINMUX('E',10, AF12)>, /* D07 */
+				 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+				 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+				 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+				 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+				 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+				 <STM32_PINMUX('D',15, AF12)>, /* D01 */
+				 <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+				 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
+				 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
+
+				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+				 <STM32_PINMUX('F',15, AF12)>, /* A09 */
+				 <STM32_PINMUX('F',14, AF12)>, /* A08 */
+				 <STM32_PINMUX('F',13, AF12)>, /* A07 */
+				 <STM32_PINMUX('F',12, AF12)>, /* A06 */
+				 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+				 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+				 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+				 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+				 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+				 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
+				 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+				 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
+				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
+			slew-rate = <2>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts
new file mode 100644
index 0000000..3ecef28
--- /dev/null
+++ b/arch/arm/dts/stm32f469-disco.dts
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f429.dtsi"
+#include "stm32f469-pinctrl.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32F469i-DISCO board";
+	compatible = "st,stm32f469i-disco", "st,stm32f469";
+
+	chosen {
+		bootargs = "root=/dev/ram";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		reg = <0x00000000 0x1000000>;
+	};
+
+	aliases {
+		serial0 = &usart3;
+	};
+
+	mmc_vcard: mmc_vcard {
+		compatible = "regulator-fixed";
+		regulator-name = "mmc_vcard";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	soc {
+		dma-ranges = <0xc0000000 0x0 0x10000000>;
+	};
+
+	/* This turns on vbus for otg for host mode (dwc2) */
+	vcc5v_otg: vcc5v-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpiob 2 0>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
+	};
+};
+
+&rcc {
+	compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
+};
+
+&clk_hse {
+	clock-frequency = <8000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&timers1 {
+	status = "okay";
+
+	pwm {
+		pinctrl-0 = <&pwm1_pins>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+
+	timer@0 {
+		status = "okay";
+	};
+};
+
+&timers3 {
+	status = "okay";
+
+	pwm {
+		pinctrl-0 = <&pwm3_pins>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+
+	timer@2 {
+		status = "okay";
+	};
+};
+
+&sdio {
+	status = "okay";
+	vmmc-supply = <&mmc_vcard>;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_pins_od>;
+	bus-width = <4>;
+};
+
+&usart3 {
+	pinctrl-0 = <&usart3_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbotg_fs {
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi
new file mode 100644
index 0000000..dd64158
--- /dev/null
+++ b/arch/arm/dts/stm32f469-pinctrl.dtsi
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "stm32f4-pinctrl.dtsi"
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			compatible = "st,stm32f469-pinctrl";
+
+			gpioa: gpio@40020000 {
+				gpio-ranges = <&pinctrl 0 0 16>;
+			};
+
+			gpiob: gpio@40020400 {
+				gpio-ranges = <&pinctrl 0 16 16>;
+			};
+
+			gpioc: gpio@40020800 {
+				gpio-ranges = <&pinctrl 0 32 16>;
+			};
+
+			gpiod: gpio@40020c00 {
+				gpio-ranges = <&pinctrl 0 48 16>;
+			};
+
+			gpioe: gpio@40021000 {
+				gpio-ranges = <&pinctrl 0 64 16>;
+			};
+
+			gpiof: gpio@40021400 {
+				gpio-ranges = <&pinctrl 0 80 16>;
+			};
+
+			gpiog: gpio@40021800 {
+				gpio-ranges = <&pinctrl 0 96 16>;
+			};
+
+			gpioh: gpio@40021c00 {
+				gpio-ranges = <&pinctrl 0 112 16>;
+			};
+
+			gpioi: gpio@40022000 {
+				gpio-ranges = <&pinctrl 0 128 16>;
+			};
+
+			gpioj: gpio@40022400 {
+				gpio-ranges = <&pinctrl 0 144 6>,
+					      <&pinctrl 12 156 4>;
+			};
+
+			gpiok: gpio@40022800 {
+				gpio-ranges = <&pinctrl 3 163 5>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index c92c2e2..9e8d2a0 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -65,6 +65,7 @@
 	aliases {
 		serial0 = &usart1;
 		spi0 = &qspi;
+		mmc0 = &sdio;
 		/* Aliases for gpios so as to use sequence */
 		gpio0 = &gpioa;
 		gpio1 = &gpiob;
@@ -238,3 +239,14 @@
 			reg = <0>;
 	};
 };
+
+&sdio {
+	status = "okay";
+	cd-gpios = <&gpioc 13 0>;
+	cd-inverted;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_pins_od>;
+	bus-width = <4>;
+	max-frequency = <25000000>;
+};
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index f62360f..929bf82 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -234,6 +234,91 @@
 				u-boot,dm-pre-reloc;
 			};
 
+			sdio_pins: sdio_pins@0 {
+				pins {
+					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
+						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
+						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
+						 <STM32F746_PC12_FUNC_SDMMC1_CK>,
+						 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od: sdio_pins_od@0 {
+				pins1 {
+					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
+						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
+						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
+						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
+						 <STM32F746_PC12_FUNC_SDMMC1_CK>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_b: sdio_pins_b@0 {
+				pins {
+					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
+						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
+						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
+						 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
+						 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			sdio_pins_od_b: sdio_pins_od_b@0 {
+				pins1 {
+					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
+						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
+						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
+						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
+						 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+
+				pins2 {
+					pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
+					drive-open-drain;
+					slew-rate = <2>;
+				};
+			};
+
+		};
+		sdio: sdio@40012c00 {
+			compatible = "st,stm32f4xx-sdio";
+			reg = <0x40012c00 0x400>;
+			clocks = <&rcc 0 171>;
+			interrupts = <49>;
+			status = "disabled";
+			pinctrl-0 = <&sdio_pins>;
+			pinctrl-1 = <&sdio_pins_od>;
+			pinctrl-names = "default", "opendrain";
+			max-frequency = <48000000>;
+		};
+
+		sdio2: sdio2@40011c00 {
+			compatible = "st,stm32f4xx-sdio";
+			reg = <0x40011c00 0x400>;
+			clocks = <&rcc 0 167>;
+			interrupts = <103>;
+			status = "disabled";
+			pinctrl-0 = <&sdio_pins_b>;
+			pinctrl-1 = <&sdio_pins_od_b>;
+			pinctrl-names = "default", "opendrain";
+			max-frequency = <48000000>;
 		};
 	};
 };
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index f34ffcc..59c9d31 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -60,6 +60,7 @@
 	aliases {
 		serial0 = &usart1;
 		spi0 = &qspi;
+		mmc0 = &sdio2;
 		/* Aliases for gpios so as to use sequence */
 		gpio0 = &gpioa;
 		gpio1 = &gpiob;
@@ -252,3 +253,14 @@
 			reg = <0>;
 	};
 };
+
+&sdio2 {
+	status = "okay";
+	cd-gpios = <&gpioi 15 0>;
+	cd-inverted;
+	pinctrl-names = "default", "opendrain";
+	pinctrl-0 = <&sdio_pins_b>;
+	pinctrl-1 = <&sdio_pins_od_b>;
+	bus-width = <4>;
+	max-frequency = <25000000>;
+};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2561ead..1ff5cac 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -23,6 +23,8 @@
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
+#define CONFIG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
 #define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
@@ -41,6 +43,33 @@
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0x508000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_BMAN_MEM_BASE)
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
+
 #define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
 
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 09f64e7..1e65e4e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
+#define AHCI_PORT_PHY2_CFG	0x28184d1f
+#define AHCI_PORT_PHY3_CFG	0x0e081509
 #define AHCI_PORT_TRANS_CFG    0x08000029
 #define AHCI_PORT_AXICC_CFG	0x3fffffff
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
index de795f6..e94fe8e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/speed.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -7,4 +7,7 @@
 #ifndef _FSL_LAYERSCAPE_SPEED_H
 #define _FSL_LAYERSCAPE_SPEED_H
 void get_sys_info(struct sys_info *sys_info);
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void);
+#endif
 #endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 736b260..5264111 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -85,4 +85,14 @@
 
 int rockchip_get_clk(struct udevice **devp);
 
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
new file mode 100644
index 0000000..0e99f1b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _F_ROCKUSB_H_
+#define _F_ROCKUSB_H_
+#include <blk.h>
+
+#define ROCKUSB_VERSION		"0.1"
+
+#define ROCKUSB_INTERFACE_CLASS	0xff
+#define ROCKUSB_INTERFACE_SUB_CLASS	0x06
+#define ROCKUSB_INTERFACE_PROTOCOL	0x05
+
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0  0x0200
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1  0x0040
+#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE      0x0040
+
+#define EP_BUFFER_SIZE			4096
+/*
+ * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size
+ * (64 or 512 or 1024), else we break on certain controllers like DWC3
+ * that expect bulk OUT requests to be divisible by maxpacket size.
+ */
+
+#define RKUSB_BUF_SIZE		EP_BUFFER_SIZE * 2
+
+#define RKUSB_STATUS_IDLE			0
+#define RKUSB_STATUS_CMD			1
+#define RKUSB_STATUS_RXDATA			2
+#define RKUSB_STATUS_TXDATA			3
+#define RKUSB_STATUS_CSW			4
+#define RKUSB_STATUS_RXDATA_PREPARE		5
+#define RKUSB_STATUS_TXDATA_PREPARE		6
+
+enum rkusb_command {
+K_FW_TEST_UNIT_READY	= 0x00,
+K_FW_READ_FLASH_ID = 0x01,
+K_FW_SET_DEVICE_ID = 0x02,
+K_FW_TEST_BAD_BLOCK = 0x03,
+K_FW_READ_10 = 0x04,
+K_FW_WRITE_10 = 0x05,
+K_FW_ERASE_10 = 0x06,
+K_FW_WRITE_SPARE = 0x07,
+K_FW_READ_SPARE = 0x08,
+
+K_FW_ERASE_10_FORCE = 0x0b,
+K_FW_GET_VERSION = 0x0c,
+
+K_FW_LBA_READ_10 = 0x14,
+K_FW_LBA_WRITE_10 = 0x15,
+K_FW_ERASE_SYS_DISK = 0x16,
+K_FW_SDRAM_READ_10 = 0x17,
+K_FW_SDRAM_WRITE_10 = 0x18,
+K_FW_SDRAM_EXECUTE = 0x19,
+K_FW_READ_FLASH_INFO = 0x1A,
+K_FW_GET_CHIP_VER = 0x1B,
+K_FW_LOW_FORMAT = 0x1C,
+K_FW_SET_RESET_FLAG = 0x1E,
+K_FW_SPI_READ_10 = 0x21,
+K_FW_SPI_WRITE_10 = 0x22,
+
+K_FW_SESSION = 0X30,
+K_FW_RESET = 0xff,
+};
+
+#define CBW_DIRECTION_OUT		0x00
+#define CBW_DIRECTION_IN		0x80
+
+struct cmd_dispatch_info {
+	enum rkusb_command cmd;
+	/* call back function to handle rockusb command */
+	void (*cb)(struct usb_ep *ep, struct usb_request *req);
+};
+
+/* Bulk-only data structures */
+
+/* Command Block Wrapper */
+struct fsg_bulk_cb_wrap {
+	__le32  signature;              /* Contains 'USBC' */
+	u32     tag;                    /* Unique per command id */
+	__le32  data_transfer_length;   /* Size of the data */
+	u8      flags;                  /* Direction in bit 7 */
+	u8      lun;                    /* lun (normally 0) */
+	u8      length;                 /* Of the CDB, <= MAX_COMMAND_SIZE */
+	u8      CDB[16];                /* Command Data Block */
+};
+
+#define USB_BULK_CB_WRAP_LEN    31
+#define USB_BULK_CB_SIG         0x43425355      /* Spells out USBC */
+#define USB_BULK_IN_FLAG        0x80
+
+/* Command status Wrapper */
+struct bulk_cs_wrap {
+	__le32  signature;              /* Should = 'USBS' */
+	u32     tag;                    /* Same as original command */
+	__le32  residue;                /* Amount not transferred */
+	u8      status;                 /* See below */
+};
+
+#define USB_BULK_CS_WRAP_LEN    13
+#define USB_BULK_CS_SIG         0x53425355      /* Spells out 'USBS' */
+#define USB_STATUS_PASS         0
+#define USB_STATUS_FAIL         1
+#define USB_STATUS_PHASE_ERROR  2
+
+#define CSW_GOOD                0x00
+#define CSW_FAIL                0x01
+
+struct f_rockusb {
+	struct usb_function usb_function;
+	struct usb_ep *in_ep, *out_ep;
+	struct usb_request *in_req, *out_req;
+	char *dev_type;
+	unsigned int dev_index;
+	unsigned int tag;
+	unsigned int lba;
+	unsigned int dl_size;
+	unsigned int dl_bytes;
+	struct blk_desc *desc;
+	int reboot_flag;
+	void *buf;
+	void *buf_head;
+};
+
+/* init rockusb device, tell rockusb which device you want to read/write*/
+void rockusb_dev_init(char *dev_type, int dev_index);
+#endif /* _F_ROCKUSB_H_ */
+
diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h
index 831c542..6173fa1 100644
--- a/arch/arm/include/asm/arch-stm32f4/gpio.h
+++ b/arch/arm/include/asm/arch-stm32f4/gpio.h
@@ -131,6 +131,22 @@
 	enum stm32_gpio_af	af;
 };
 
+struct stm32_gpio_regs {
+	u32 moder;	/* GPIO port mode */
+	u32 otyper;	/* GPIO port output type */
+	u32 ospeedr;	/* GPIO port output speed */
+	u32 pupdr;	/* GPIO port pull-up/pull-down */
+	u32 idr;	/* GPIO port input data */
+	u32 odr;	/* GPIO port output data */
+	u32 bsrr;	/* GPIO port bit set/reset */
+	u32 lckr;	/* GPIO port configuration lock */
+	u32 afr[2];	/* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+	struct stm32_gpio_regs *regs;
+};
+
 static inline unsigned stm32_gpio_to_port(unsigned gpio)
 {
 	return gpio / 16;
@@ -141,8 +157,4 @@
 	return gpio % 16;
 }
 
-int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
-		const struct stm32_gpio_ctl *gpio_ctl);
-int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
-
 #endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index e9f3aab..0449fce 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -23,16 +23,6 @@
 
 #define STM32_BUS_MASK		0xFFFF0000
 
-#define STM32_GPIOA_BASE	(STM32_AHB1PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE	(STM32_AHB1PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE	(STM32_AHB1PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE	(STM32_AHB1PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE	(STM32_AHB1PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE	(STM32_AHB1PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE	(STM32_AHB1PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE	(STM32_AHB1PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE	(STM32_AHB1PERIPH_BASE + 0x2000)
-
 /*
  * Register maps
  */
@@ -42,11 +32,6 @@
 	u32 u_id_high;
 };
 
-struct stm32_pwr_regs {
-	u32 cr;
-	u32 csr;
-};
-
 /*
  * Registers access macros
  */
@@ -56,17 +41,6 @@
 #define STM32_RCC_BASE		(STM32_AHB1PERIPH_BASE + 0x3800)
 #define STM32_RCC		((struct stm32_rcc_regs *)STM32_RCC_BASE)
 
-#define STM32_PWR_BASE		(STM32_APB1PERIPH_BASE + 0x7000)
-#define STM32_PWR		((struct stm32_pwr_regs *)STM32_PWR_BASE)
-
-/*
- * Peripheral base addresses
- */
-#define STM32_USART1_BASE	(STM32_APB2PERIPH_BASE + 0x1000)
-#define STM32_USART2_BASE	(STM32_APB1PERIPH_BASE + 0x4400)
-#define STM32_USART3_BASE	(STM32_APB1PERIPH_BASE + 0x4800)
-#define STM32_USART6_BASE	(STM32_APB2PERIPH_BASE + 0x1400)
-
 #define FLASH_CNTL_BASE		(STM32_AHB1PERIPH_BASE + 0x3C00)
 
 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
@@ -75,15 +49,6 @@
 	[5 ... 11] =	128 * 1024
 };
 
-enum clock {
-	CLOCK_CORE,
-	CLOCK_AHB,
-	CLOCK_APB1,
-	CLOCK_APB2
-};
-
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
 void stm32_flash_latency_cfg(int latency);
 
 #endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index ec6463d..3f30470 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -26,6 +26,14 @@
 
 #define CONFIG_KEY_REVOCATION
 
+#if defined(CONFIG_FSL_LAYERSCAPE)
+/*
+ * For fsl layerscape based platforms, ESBC image Address in Header
+ * is 64 bit.
+ */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SYS_RAMBOOT
 /* The key used for verification of next level images
@@ -42,14 +50,6 @@
 
 #endif
 
-#if defined(CONFIG_FSL_LAYERSCAPE)
-/*
- * For fsl layerscape based platforms, ESBC image Address in Header
- * is 64 bit.
- */
-#define CONFIG_ESBC_ADDR_64BIT
-#endif
-
 #ifdef CONFIG_ARCH_LS2080A
 #define CONFIG_EXTRA_ENV \
 	"setenv fdt_high 0xa0000000;"	\
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 967290f..8510781 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -61,6 +61,8 @@
 	select SPL_BOARD_INIT if SPL
 	select SUPPORT_SPL
 	select SPL
+	imply USB_FUNCTION_ROCKUSB
+	imply CMD_ROCKUSB
 	help
 	  The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
 	  including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index cb6ae03..6b76221 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -59,7 +59,8 @@
 	return 0;
 }
 
-int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifndef CONFIG_SPL_BUILD
+static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	cm_print_clock_quick_summary();
 	return 0;
@@ -70,3 +71,4 @@
 	"display clocks",
 	""
 );
+#endif
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 91ddb79..a7dcacc 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -30,14 +30,10 @@
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_reset_manager *reset_manager_base =
-	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
-	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
 /*
  * DesignWare Ethernet initialization
@@ -292,6 +288,12 @@
 	return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
+static struct socfpga_reset_manager *reset_manager_base =
+	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
 static void socfpga_sdram_apply_static_cfg(void)
 {
 	const u32 applymask = 0x8;
@@ -321,7 +323,7 @@
 	: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
 }
 
-int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	if (argc != 2)
 		return CMD_RET_USAGE;
@@ -357,3 +359,4 @@
 	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 	""
 );
+#endif
diff --git a/arch/arm/mach-stm32/stm32f4/Kconfig b/arch/arm/mach-stm32/stm32f4/Kconfig
index a63619e..7005c65 100644
--- a/arch/arm/mach-stm32/stm32f4/Kconfig
+++ b/arch/arm/mach-stm32/stm32f4/Kconfig
@@ -3,6 +3,10 @@
 config TARGET_STM32F429_DISCOVERY
 	bool "STM32F429 Discovery board"
 
+config TARGET_STM32F469_DISCOVERY
+	bool "STM32F469 Discovery board"
+
 source "board/st/stm32f429-discovery/Kconfig"
+source "board/st/stm32f469-discovery/Kconfig"
 
 endif
diff --git a/arch/arm/mach-stm32/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile
index 63db820..86c81bb 100644
--- a/arch/arm/mach-stm32/stm32f4/Makefile
+++ b/arch/arm/mach-stm32/stm32f4/Makefile
@@ -8,4 +8,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += clock.o timer.o
+obj-y += timer.o
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
deleted file mode 100644
index 774591d..0000000
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * (C) Copyright 2014
- * STMicroelectronics
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
-
-#define RCC_CR_HSION		(1 << 0)
-#define RCC_CR_HSEON		(1 << 16)
-#define RCC_CR_HSERDY		(1 << 17)
-#define RCC_CR_HSEBYP		(1 << 18)
-#define RCC_CR_CSSON		(1 << 19)
-#define RCC_CR_PLLON		(1 << 24)
-#define RCC_CR_PLLRDY		(1 << 25)
-
-#define RCC_PLLCFGR_PLLM_MASK	0x3F
-#define RCC_PLLCFGR_PLLN_MASK	0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK	0x30000
-#define RCC_PLLCFGR_PLLQ_MASK	0xF000000
-#define RCC_PLLCFGR_PLLSRC	(1 << 22)
-#define RCC_PLLCFGR_PLLN_SHIFT	6
-#define RCC_PLLCFGR_PLLP_SHIFT	16
-#define RCC_PLLCFGR_PLLQ_SHIFT	24
-
-#define RCC_CFGR_AHB_PSC_MASK	0xF0
-#define RCC_CFGR_APB1_PSC_MASK	0x1C00
-#define RCC_CFGR_APB2_PSC_MASK	0xE000
-#define RCC_CFGR_SW0		(1 << 0)
-#define RCC_CFGR_SW1		(1 << 1)
-#define RCC_CFGR_SW_MASK	0x3
-#define RCC_CFGR_SW_HSI		0
-#define RCC_CFGR_SW_HSE		RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL		RCC_CFGR_SW1
-#define RCC_CFGR_SWS0		(1 << 2)
-#define RCC_CFGR_SWS1		(1 << 3)
-#define RCC_CFGR_SWS_MASK	0xC
-#define RCC_CFGR_SWS_HSI	0
-#define RCC_CFGR_SWS_HSE	RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL	RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT	4
-#define RCC_CFGR_PPRE1_SHIFT	10
-#define RCC_CFGR_PPRE2_SHIFT	13
-
-#define RCC_APB1ENR_PWREN	(1 << 28)
-
-/*
- * RCC USART specific definitions
- */
-#define RCC_ENR_USART1EN		(1 << 4)
-#define RCC_ENR_USART2EN		(1 << 17)
-#define RCC_ENR_USART3EN		(1 << 18)
-#define RCC_ENR_USART6EN		(1 <<  5)
-
-#define PWR_CR_VOS0		(1 << 14)
-#define PWR_CR_VOS1		(1 << 15)
-#define PWR_CR_VOS_MASK		0xC000
-#define PWR_CR_VOS_SCALE_MODE_1	(PWR_CR_VOS0 | PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_2	(PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_3	(PWR_CR_VOS0)
-
-/*
- * RCC GPIO specific definitions
- */
-#define RCC_ENR_GPIO_A_EN	(1 << 0)
-#define RCC_ENR_GPIO_B_EN	(1 << 1)
-#define RCC_ENR_GPIO_C_EN	(1 << 2)
-#define RCC_ENR_GPIO_D_EN	(1 << 3)
-#define RCC_ENR_GPIO_E_EN	(1 << 4)
-#define RCC_ENR_GPIO_F_EN	(1 << 5)
-#define RCC_ENR_GPIO_G_EN	(1 << 6)
-#define RCC_ENR_GPIO_H_EN	(1 << 7)
-#define RCC_ENR_GPIO_I_EN	(1 << 8)
-#define RCC_ENR_GPIO_J_EN	(1 << 9)
-#define RCC_ENR_GPIO_K_EN	(1 << 10)
-
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 8000000)
-#if (CONFIG_SYS_CLK_FREQ == 180000000)
-/* 180 MHz */
-struct pll_psc sys_pll_psc = {
-	.pll_m = 8,
-	.pll_n = 360,
-	.pll_p = 2,
-	.pll_q = 8,
-	.ahb_psc = AHB_PSC_1,
-	.apb1_psc = APB_PSC_4,
-	.apb2_psc = APB_PSC_2
-};
-#else
-/* default 168 MHz */
-struct pll_psc sys_pll_psc = {
-	.pll_m = 8,
-	.pll_n = 336,
-	.pll_p = 2,
-	.pll_q = 7,
-	.ahb_psc = AHB_PSC_1,
-	.apb1_psc = APB_PSC_4,
-	.apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
-int configure_clocks(void)
-{
-	/* Reset RCC configuration */
-	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
-	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
-	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
-		| RCC_CR_PLLON));
-	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
-	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
-	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
-
-	/* Configure for HSE+PLL operation */
-	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
-	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
-		;
-
-	/* Enable high performance mode, System frequency up to 180 MHz */
-	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
-	writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
-
-	setbits_le32(&STM32_RCC->cfgr, ((
-		sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
-		| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
-		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
-
-	writel(sys_pll_psc.pll_m
-		| (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
-		| (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
-		| (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
-		&STM32_RCC->pllcfgr);
-	setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
-
-	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
-
-	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
-		;
-
-	stm32_flash_latency_cfg(5);
-	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
-	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
-
-	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
-			RCC_CFGR_SWS_PLL)
-		;
-
-	return 0;
-}
-
-unsigned long clock_get(enum clock clck)
-{
-	u32 sysclk = 0;
-	u32 shift = 0;
-	/* Prescaler table lookups for clock computation */
-	u8 ahb_psc_table[16] = {
-		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
-	};
-	u8 apb_psc_table[8] = {
-		0, 0, 0, 0, 1, 2, 3, 4
-	};
-
-	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
-			RCC_CFGR_SWS_PLL) {
-		u16 pllm, plln, pllp;
-		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
-		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
-			>> RCC_PLLCFGR_PLLN_SHIFT);
-		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
-			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
-		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
-	}
-
-	switch (clck) {
-	case CLOCK_CORE:
-		return sysclk;
-		break;
-	case CLOCK_AHB:
-		shift = ahb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
-			>> RCC_CFGR_HPRE_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB1:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
-			>> RCC_CFGR_PPRE1_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB2:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
-			>> RCC_CFGR_PPRE2_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	default:
-		return 0;
-		break;
-	}
-}
-
-void clock_setup(int peripheral)
-{
-	switch (peripheral) {
-	case USART1_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
-		break;
-	case GPIO_A_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
-		break;
-	case GPIO_B_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
-		break;
-	case GPIO_C_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
-		break;
-	case GPIO_D_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
-		break;
-	case GPIO_E_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
-		break;
-	case GPIO_F_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
-		break;
-	case GPIO_G_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
-		break;
-	case GPIO_H_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
-		break;
-	case GPIO_I_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
-		break;
-	case GPIO_J_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
-		break;
-	case GPIO_K_CLOCK_CFG:
-		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
-		break;
-	default:
-		break;
-	}
-}
diff --git a/arch/arm/mach-stm32/stm32f4/timer.c b/arch/arm/mach-stm32/stm32f4/timer.c
index 163f461..00b1d4a 100644
--- a/arch/arm/mach-stm32/stm32f4/timer.c
+++ b/arch/arm/mach-stm32/stm32f4/timer.c
@@ -51,12 +51,8 @@
 
 	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
 
-	if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
-		writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
-		       &tim->psc);
-	else
-		writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
-		       &tim->psc);
+	writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1,
+	       &tim->psc);
 
 	writel(0xFFFFFFFF, &tim->arr);
 	writel(TIM_CR1_CEN, &tim->cr1);
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index e9672d2..f678114 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -205,6 +205,7 @@
 		return ret;
 
 	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
+		unsigned long max_size;
 
 		if (!dram_map[i].size)
 			break;
@@ -218,9 +219,32 @@
 							dram_map[i].base)
 			break;
 
+		/*
+		 * Do not use memory that exceeds 32bit address range.  U-Boot
+		 * relocates itself to the end of the effectively available RAM.
+		 * This could be a problem for DMA engines that do not support
+		 * 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.)
+		 */
+		if (dram_map[i].base >= 1ULL << 32)
+			break;
+
+		max_size = (1ULL << 32) - dram_map[i].base;
+
+		if (dram_map[i].size > max_size) {
+			gd->ram_size += max_size;
+			break;
+		}
+
 		gd->ram_size += dram_map[i].size;
 	}
 
+	/*
+	 * LD20 uses the last 64 byte for each channel for dynamic
+	 * DDR PHY training
+	 */
+	if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
+		gd->ram_size -= 64;
+
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index ea46e49..b350bfe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -26,6 +26,7 @@
 #ifdef CONFIG_FSL_CORENET
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#include <fsl_qbman.h>
 #endif
 #include <fsl_usb.h>
 #include <hwconfig.h>
@@ -804,7 +805,7 @@
 #ifdef CONFIG_FSL_CORENET
 	set_liodns();
 #ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
+	setup_qbman_portals();
 #endif
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 297dc4a..1159f06 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -15,6 +15,7 @@
 #include <asm/io.h>
 #include <asm/fsl_fdt.h>
 #include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
 #include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 3777c6f..b298d11 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -14,75 +14,6 @@
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
-static void inhibit_portals(void __iomem *addr, int max_portals,
-			int arch_max_portals, int portal_cinh_size)
-{
-	uint32_t val;
-	int i;
-
-	/* arch_max_portals is the maximum based on memory size. This includes
-	 * the reserved memory in the SoC.  max_portals the number of physical
-	 * portals in the SoC */
-	if (max_portals > arch_max_portals) {
-		printf("ERROR: portal config error\n");
-		max_portals = arch_max_portals;
-	}
-
-	for (i = 0; i < max_portals; i++) {
-		out_be32(addr, -1);
-		val = in_be32(addr);
-		if (!val) {
-			printf("ERROR: Stopped after %d portals\n", i);
-			goto done;
-		}
-		addr += portal_cinh_size;
-	}
-#ifdef DEBUG
-	printf("Cleared %d portals\n", i);
-#endif
-done:
-
-	return;
-}
-
-void setup_portals(void)
-{
-	ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
-	void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
-				CONFIG_SYS_BMAN_SWP_ISDR_REG;
-	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
-				CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_FSL_CORENET
-	int i;
-
-	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
-		u8 sdest = qp_info[i].sdest;
-		u16 fliodn = qp_info[i].fliodn;
-		u16 dliodn = qp_info[i].dliodn;
-		u16 liodn_off = qp_info[i].liodn_offset;
-
-		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
-					dliodn);
-		/* set frame liodn */
-		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
-	}
-#endif
-
-	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
-#ifdef CONFIG_PHYS_64BIT
-	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
-#endif
-	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-
-	/* Change default state of BMan ISDR portals to all 1s */
-	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
-			CONFIG_SYS_BMAN_SP_CINH_SIZE);
-	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
-			CONFIG_SYS_QMAN_SP_CINH_SIZE);
-}
-
 /* Update portal containter to match LAW setup of portal in phy map */
 void fdt_portal(void *blob, const char *compat, const char *container,
 			u64 addr, u32 size)
@@ -142,215 +73,3 @@
 
 	printf("ERROR: %s isn't in a container.  Not supported\n", compat);
 }
-
-static int fdt_qportal(void *blob, int off, int id, char *name,
-		       enum fsl_dpaa_dev dev, int create)
-{
-	int childoff, dev_off, ret = 0;
-	uint32_t dev_handle;
-#ifdef CONFIG_FSL_CORENET
-	int num;
-	u32 liodns[2];
-#endif
-
-	childoff = fdt_subnode_offset(blob, off, name);
-	if (create) {
-		char handle[64], *p;
-
-		strncpy(handle, name, sizeof(handle));
-		p = strchr(handle, '@');
-		if (!strncmp(name, "fman", 4)) {
-			*p = *(p + 1);
-			p++;
-		}
-		*p = '\0';
-
-		dev_off = fdt_path_offset(blob, handle);
-		/* skip this node if alias is not found */
-		if (dev_off == -FDT_ERR_BADPATH)
-			return 0;
-		if (dev_off < 0)
-			return dev_off;
-
-		if (childoff <= 0)
-			childoff = fdt_add_subnode(blob, off, name);
-
-		/* need to update the dev_off after adding a subnode */
-		dev_off = fdt_path_offset(blob, handle);
-		if (dev_off < 0)
-			return dev_off;
-
-		if (childoff > 0) {
-			dev_handle = fdt_get_phandle(blob, dev_off);
-			if (dev_handle <= 0) {
-				dev_handle = fdt_alloc_phandle(blob);
-				ret = fdt_set_phandle(blob, dev_off,
-							 dev_handle);
-				if (ret < 0)
-					return ret;
-			}
-
-			ret = fdt_setprop(blob, childoff, "dev-handle",
-					  &dev_handle, sizeof(dev_handle));
-			if (ret < 0)
-				return ret;
-
-#ifdef CONFIG_FSL_CORENET
-			num = get_dpaa_liodn(dev, &liodns[0], id);
-			ret = fdt_setprop(blob, childoff, "fsl,liodn",
-					  &liodns[0], sizeof(u32) * num);
-			if (!strncmp(name, "pme", 3)) {
-				u32 pme_rev1, pme_rev2;
-				ccsr_pme_t *pme_regs =
-					(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
-
-				pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
-				pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
-				ret = fdt_setprop(blob, childoff,
-					"fsl,pme-rev1", &pme_rev1, sizeof(u32));
-				if (ret < 0)
-					return ret;
-				ret = fdt_setprop(blob, childoff,
-					"fsl,pme-rev2", &pme_rev2, sizeof(u32));
-			}
-#endif
-		} else {
-			return childoff;
-		}
-	} else {
-		if (childoff > 0)
-			ret = fdt_del_node(blob, childoff);
-	}
-
-	return ret;
-}
-
-void fdt_fixup_qportals(void *blob)
-{
-	int off, err;
-	unsigned int maj, min;
-	unsigned int ip_cfg;
-	ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
-	u32 rev_1 = in_be32(&qman->ip_rev_1);
-	u32 rev_2 = in_be32(&qman->ip_rev_2);
-	char compat[64];
-	int compat_len;
-
-	maj = (rev_1 >> 8) & 0xff;
-	min = rev_1 & 0xff;
-	ip_cfg = rev_2 & 0xff;
-
-	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
-					maj, min, ip_cfg) + 1;
-	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
-	while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_FSL_CORENET
-		u32 liodns[2];
-#endif
-		const int *ci = fdt_getprop(blob, off, "cell-index", &err);
-		int i;
-
-		if (!ci)
-			goto err;
-
-		i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
-		int j;
-#endif
-
-		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
-		if (err < 0)
-			goto err;
-
-#ifdef CONFIG_FSL_CORENET
-		liodns[0] = qp_info[i].dliodn;
-		liodns[1] = qp_info[i].fliodn;
-
-		err = fdt_setprop(blob, off, "fsl,liodn",
-				  &liodns, sizeof(u32) * 2);
-		if (err < 0)
-			goto err;
-#endif
-
-		i++;
-
-		err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
-				  IS_E_PROCESSOR(get_svr()));
-		if (err < 0)
-			goto err;
-
-#ifdef CONFIG_FSL_CORENET
-#ifdef CONFIG_SYS_DPAA_PME
-		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
-		if (err < 0)
-			goto err;
-#else
-		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
-#endif
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
-			char name[] = "fman@0";
-
-			name[sizeof(name) - 2] = '0' + j;
-			err = fdt_qportal(blob, off, i, name,
-					  FSL_HW_PORTAL_FMAN1 + j, 1);
-			if (err < 0)
-				goto err;
-		}
-#endif
-#ifdef CONFIG_SYS_DPAA_RMAN
-		err = fdt_qportal(blob, off, i, "rman@0",
-				  FSL_HW_PORTAL_RMAN, 1);
-		if (err < 0)
-			goto err;
-#endif
-
-err:
-		if (err < 0) {
-			printf("ERROR: unable to create props for %s: %s\n",
-				fdt_get_name(blob, off, NULL), fdt_strerror(err));
-			return;
-		}
-
-		off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
-	}
-}
-
-void fdt_fixup_bportals(void *blob)
-{
-	int off, err;
-	unsigned int maj, min;
-	unsigned int ip_cfg;
-	ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
-	u32 rev_1 = in_be32(&bman->ip_rev_1);
-	u32 rev_2 = in_be32(&bman->ip_rev_2);
-	char compat[64];
-	int compat_len;
-
-	maj = (rev_1 >> 8) & 0xff;
-	min = rev_1 & 0xff;
-
-	ip_cfg = rev_2 & 0xff;
-
-	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
-				 maj, min, ip_cfg) + 1;
-	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
-	while (off != -FDT_ERR_NOTFOUND) {
-		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
-		if (err < 0) {
-			printf("ERROR: unable to create props for %s: %s\n",
-				fdt_get_name(blob, off, NULL),
-						 fdt_strerror(err));
-			return;
-		}
-
-		off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
-	}
-
-}
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 8c91e72..0ccb79c 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -8,6 +8,7 @@
 #define _FSL_LIODN_H_
 
 #include <asm/types.h>
+#include <fsl_qbman.h>
 
 struct srio_liodn_id_table {
 	u32 id[2];
@@ -128,12 +129,14 @@
 		CONFIG_SYS_MPC85xx_TDM_OFFSET)
 
 #define SET_QMAN_LIODN(liodn) \
-	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
+	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+		offsetof(struct ccsr_qman, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_OFFSET, \
 		CONFIG_SYS_FSL_QMAN_OFFSET)
 
 #define SET_BMAN_LIODN(liodn) \
-	SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
+	SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+		offsetof(struct ccsr_bman, liodnr) + \
 		CONFIG_SYS_FSL_BMAN_OFFSET, \
 		CONFIG_SYS_FSL_BMAN_OFFSET)
 
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index f13ba14..10d459e 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -41,10 +41,6 @@
 
 extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
 			  u32 *liodns, int liodn_offset);
-extern void setup_portals(void);
-extern void fdt_fixup_qportals(void *blob);
-extern void fdt_fixup_bportals(void *blob);
-
 extern struct qportal_info qp_info[];
 extern void fdt_portal(void *blob, const char *compat, const char *container,
 			u64 addr, u32 size);
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index ee537f4..841f3d9 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2702,66 +2702,6 @@
 	FSL_SRDS_B3_LANE_D = 23,
 };
 
-typedef struct ccsr_qman {
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-	u8	res0[0x200];
-#else
-	struct {
-		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
-		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
-		u32	res;
-		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
-	} qcsp[32];
-#endif
-	/* Not actually reserved, but irrelevant to u-boot */
-	u8	res[0xbf8 - 0x200];
-	u32	ip_rev_1;
-	u32	ip_rev_2;
-	u32	fqd_bare;	/* FQD Extended Base Addr Register */
-	u32	fqd_bar;	/* FQD Base Addr Register */
-	u8	res1[0x8];
-	u32	fqd_ar;		/* FQD Attributes Register */
-	u8	res2[0xc];
-	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
-	u32	pfdr_bar;	/* PFDR Base Addr Register */
-	u8	res3[0x8];
-	u32	pfdr_ar;	/* PFDR Attributes Register */
-	u8	res4[0x4c];
-	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
-	u32	qcsp_bar;	/* QCSP Base Addr Register */
-	u8	res5[0x78];
-	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
-	u32	srcidr;		/* Source ID Register */
-	u32	liodnr;		/* LIODN Register */
-	u8	res6[4];
-	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
-	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
-	u8	res7[0x2e8];
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-	struct {
-		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
-		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
-		u32	res;
-		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
-	} qcsp[50];
-#endif
-} ccsr_qman_t;
-
-typedef struct ccsr_bman {
-	/* Not actually reserved, but irrelevant to u-boot */
-	u8	res[0xbf8];
-	u32	ip_rev_1;
-	u32	ip_rev_2;
-	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
-	u32	fbpr_bar;	/* FBPR Base Addr Register */
-	u8	res1[0x8];
-	u32	fbpr_ar;	/* FBPR Attributes Register */
-	u8	res2[0xf0];
-	u32	srcidr;		/* Source ID Register */
-	u32	liodnr;		/* LIODN Register */
-	u8	res7[0x2f4];
-} ccsr_bman_t;
-
 typedef struct ccsr_pme {
 	u8	res0[0x804];
 	u32	liodnbr;	/* LIODN Base Register */
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index 2e7802f..a79ade7 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -8,8 +8,6 @@
 #
 
 obj-y	+= interrupts.o
-ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_PCI)	+= pci_io.o
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTZ) += bootm.o
diff --git a/board/atmel/common/Makefile b/board/atmel/common/Makefile
index 8a6850b..f68dd74 100644
--- a/board/atmel/common/Makefile
+++ b/board/atmel/common/Makefile
@@ -6,7 +6,5 @@
 #
 
 obj-y += board.o
-ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
 obj-$(CONFIG_DM_VIDEO) += video_display.o
-endif
diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index de3961d..371e5db 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -27,3 +27,8 @@
 M:	Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
 S:	Maintained
 F:	configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+
+LS1088ARDB_SD_SECURE_BOOT BOARD
+M:	Sumit Garg <sumit.garg@nxp.com>
+S:	Maintained
+F:	configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile
index bdcce9e..0e15031 100644
--- a/board/freescale/ls1088a/Makefile
+++ b/board/freescale/ls1088a/Makefile
@@ -5,6 +5,8 @@
 #
 
 obj-y += ls1088a.o
+obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o
 obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o
-obj-y += ddr.o
+endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 96f183e..d12bcae 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -25,6 +25,13 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+	fsl_lsch3_early_init_f();
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QIXIS
 unsigned long long get_qixis_addr(void)
 {
 	unsigned long long addr;
@@ -42,7 +49,9 @@
 
 	return addr;
 }
+#endif
 
+#if !defined(CONFIG_SPL_BUILD)
 int checkboard(void)
 {
 	char buf[64];
@@ -342,12 +351,6 @@
 	return 0;
 }
 
-int board_early_init_f(void)
-{
-	fsl_lsch3_early_init_f();
-	return 0;
-}
-
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
@@ -451,3 +454,4 @@
 	return 0;
 }
 #endif
+#endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index ccda824..a23a5d5 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -18,6 +18,7 @@
 #include <asm/fsl_pci.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <netdev.h>
@@ -81,7 +82,7 @@
 		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
-	setup_portals();
+	setup_qbman_portals();
 
 	return 0;
 }
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 8c9d6b1..d70b1d1 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -126,7 +126,7 @@
 	invalidate_icache();
 
 	set_liodns();
-	setup_portals();
+	setup_qbman_portals();
 
 	ret = trigger_fpga_config();
 	if (ret)
diff --git a/board/samsung/arndale/Makefile b/board/samsung/arndale/Makefile
index be2b366..01bbc07 100644
--- a/board/samsung/arndale/Makefile
+++ b/board/samsung/arndale/Makefile
@@ -5,7 +5,4 @@
 #
 
 obj-y	+= arndale_spl.o
-
-ifndef CONFIG_SPL_BUILD
 obj-y	+= arndale.o
-endif
diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
index d514dc2..5248265 100644
--- a/board/samsung/espresso7420/Makefile
+++ b/board/samsung/espresso7420/Makefile
@@ -5,6 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SPL_BUILD
 obj-y	+= espresso7420.o
-endif
diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README
index ef1e3bf..a7bc0d4 100644
--- a/board/solidrun/clearfog/README
+++ b/board/solidrun/clearfog/README
@@ -17,16 +17,29 @@
 Please use the correct device node for your setup instead
 of "/dev/sdX" here!
 
+Boot selection:
+---------------
+
+Before powering up the board, boot selection should be done via the SW1 dip
+switch (0: OFF, 1: ON):
+
+ - SPI:     00010
+ - SD/eMMC: 00111
+ - M.2 SSD: 11100
+ - UART:    01001 [1]
+
+[1]: According to SolidRun's manual, 11110 should be used for UART booting on
+     the ClearFog 'Pro' variant.
+     However, this doesn't work (anymore) at least on Rev. 2.1 (but '01001' as
+     mentionend for the 'Base' variant does).
+
 Boot from UART:
 ---------------
 
 Connect the on-board micro-USB (CF Pro: CON11, CF Base: CON5)
 to your host.
 
-Set the SW1 DIP switches to UART boot (0: OFF, 1: ON):
-
-  ClearFog Base: 01001
-  ClearFog Pro:  11110
+Set the SW1 DIP switches to UART boot (see above).
 
 Run the following command to initiate U-Boot download:
 
diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile
index 7abfb9a..86a7fc4 100644
--- a/board/spear/spear600/Makefile
+++ b/board/spear/spear600/Makefile
@@ -5,6 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifndef CONFIG_SPL_BUILD
-obj-y	:= spear600.o
-endif
+obj-y	+= spear600.o
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index 1c34a8e..3d90218 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -13,277 +13,35 @@
 
 #include <common.h>
 #include <dm.h>
-#include <stm32_rcc.h>
+
 #include <asm/io.h>
-#include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/fmc.h>
-#include <dm/platform_data/serial_stm32.h>
-#include <asm/arch/stm32_periph.h>
-#include <asm/arch/stm32_defs.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
-	.mode = STM32_GPIO_MODE_OUT,
-	.otype = STM32_GPIO_OTYPE_PP,
-	.speed = STM32_GPIO_SPEED_50M,
-	.pupd = STM32_GPIO_PUPD_NO,
-	.af = STM32_GPIO_AF0
-};
-
-const struct stm32_gpio_ctl gpio_ctl_usart = {
-	.mode = STM32_GPIO_MODE_AF,
-	.otype = STM32_GPIO_OTYPE_PP,
-	.speed = STM32_GPIO_SPEED_50M,
-	.pupd = STM32_GPIO_PUPD_UP,
-	.af = STM32_GPIO_USART
-};
-
-static const struct stm32_gpio_dsc usart_gpio[] = {
-	{STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX},	/* TX */
-	{STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX},	/* RX */
-};
-
-int uart_setup_gpio(void)
-{
-	int i;
-	int rv = 0;
-
-	clock_setup(GPIO_A_CLOCK_CFG);
-	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
-		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
-		if (rv)
-			goto out;
-	}
-
-out:
-	return rv;
-}
-
-const struct stm32_gpio_ctl gpio_ctl_fmc = {
-	.mode = STM32_GPIO_MODE_AF,
-	.otype = STM32_GPIO_OTYPE_PP,
-	.speed = STM32_GPIO_SPEED_100M,
-	.pupd = STM32_GPIO_PUPD_NO,
-	.af = STM32_GPIO_AF12
-};
-
-static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
-	/* Chip is LQFP144, see DM00077036.pdf for details */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10},	/* 79, FMC_D15 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9},	/* 78, FMC_D14 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8},	/* 77, FMC_D13 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15},	/* 68, FMC_D12 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14},	/* 67, FMC_D11 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13},	/* 66, FMC_D10 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12},	/* 65, FMC_D9 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11},	/* 64, FMC_D8 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10},	/* 63, FMC_D7 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9},	/* 60, FMC_D6 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8},	/* 59, FMC_D5 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7},	/* 58, FMC_D4 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1},	/* 115, FMC_D3 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0},	/* 114, FMC_D2 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15},	/* 86, FMC_D1 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14},	/* 85, FMC_D0 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1},	/* 142, FMC_NBL1 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0},	/* 141, FMC_NBL0 */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5},	/* 90, FMC_A15, BA1 */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4},	/* 89, FMC_A14, BA0 */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1},	/* 57, FMC_A11 */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0},	/* 56, FMC_A10 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15},	/* 55, FMC_A9 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14},	/* 54, FMC_A8 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13},	/* 53, FMC_A7 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12},	/* 50, FMC_A6 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5},	/* 15, FMC_A5 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4},	/* 14, FMC_A4 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3},	/* 13, FMC_A3 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2},	/* 12, FMC_A2 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1},	/* 11, FMC_A1 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0},	/* 10, FMC_A0 */
-	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_6},	/* 136, SDRAM_NE */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11},	/* 49, SDRAM_NRAS */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15},	/* 132, SDRAM_NCAS */
-	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_0},	/* 26, SDRAM_NWE */
-	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_5},	/* 135, SDRAM_CKE */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8},	/* 93, SDRAM_CLK */
-};
-
-static int fmc_setup_gpio(void)
-{
-	int rv = 0;
-	int i;
-
-	clock_setup(GPIO_B_CLOCK_CFG);
-	clock_setup(GPIO_C_CLOCK_CFG);
-	clock_setup(GPIO_D_CLOCK_CFG);
-	clock_setup(GPIO_E_CLOCK_CFG);
-	clock_setup(GPIO_F_CLOCK_CFG);
-	clock_setup(GPIO_G_CLOCK_CFG);
-
-	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
-		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
-				&gpio_ctl_fmc);
-		if (rv)
-			goto out;
-	}
-
-out:
-	return rv;
-}
-
-/*
- * STM32 RCC FMC specific definitions
- */
-#define STM32_RCC_ENR_FMC	(1 << 0)	/* FMC module clock  */
-
-static inline u32 _ns2clk(u32 ns, u32 freq)
-{
-	u32 tmp = freq/1000000;
-	return (tmp * ns) / 1000;
-}
-
-#define NS2CLK(ns) (_ns2clk(ns, freq))
-
-/*
- * Following are timings for IS42S16400J, from corresponding datasheet
- */
-#define SDRAM_CAS	3	/* 3 cycles */
-#define SDRAM_NB	1	/* Number of banks */
-#define SDRAM_MWID	1	/* 16 bit memory */
-
-#define SDRAM_NR	0x1	/* 12-bit row */
-#define SDRAM_NC	0x0	/* 8-bit col */
-#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
-#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
-
-#define SDRAM_TRRD	(NS2CLK(14) - 1)
-#define SDRAM_TRCD	(NS2CLK(15) - 1)
-#define SDRAM_TRP	(NS2CLK(15) - 1)
-#define SDRAM_TRAS	(NS2CLK(42) - 1)
-#define SDRAM_TRC	(NS2CLK(63) - 1)
-#define SDRAM_TRFC	(NS2CLK(63) - 1)
-#define SDRAM_TCDL	(1 - 1)
-#define SDRAM_TRDL	(2 - 1)
-#define SDRAM_TBDL	(1 - 1)
-#define SDRAM_TREF	1386
-#define SDRAM_TCCD	(1 - 1)
-
-#define SDRAM_TXSR	(NS2CLK(70) - 1)/* Row cycle time after precharge */
-#define SDRAM_TMRD	(3 - 1)		/* Page 10, Mode Register Set */
-
-/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
-#define SDRAM_TWR	max(\
-	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
-	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
-)
-
-#define SDRAM_MODE_BL_SHIFT	0
-#define SDRAM_MODE_CAS_SHIFT	4
-#define SDRAM_MODE_BL		0
-#define SDRAM_MODE_CAS		SDRAM_CAS
-
 int dram_init(void)
 {
-	u32 freq;
 	int rv;
+	struct udevice *dev;
 
-	rv = fmc_setup_gpio();
-	if (rv)
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
 		return rv;
-
-	setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
-
-	/*
-	 * Get frequency for NS2CLK calculation.
-	 */
-	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
-
-	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
-		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
-		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
-		&STM32_SDRAM_FMC->sdcr1);
-
-	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
-		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
-		| SDRAM_NB << FMC_SDCR_NB_SHIFT
-		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
-		| SDRAM_NR << FMC_SDCR_NR_SHIFT
-		| SDRAM_NC << FMC_SDCR_NC_SHIFT
-		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
-		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
-		&STM32_SDRAM_FMC->sdcr2);
-
-	writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
-		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
-		&STM32_SDRAM_FMC->sdtr1);
-
-	writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
-		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
-		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
-		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
-		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
-		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
-		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
-		&STM32_SDRAM_FMC->sdtr2);
-
-	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-	FMC_BUSY_WAIT();
-
-	writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
-		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
-		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
-		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
-		&STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	FMC_BUSY_WAIT();
-
-	/* Refresh timer */
-	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
-
-	/*
-	 * Fill in global info with description of SRAM configuration
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
-	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+	}
 
-	gd->ram_size = CONFIG_SYS_RAM_SIZE;
+	if (fdtdec_setup_memory_size() != 0)
+		rv = -EINVAL;
 
 	return rv;
 }
 
-static const struct stm32_serial_platdata serial_platdata = {
-	.base = (struct stm32_usart *)STM32_USART1_BASE,
-};
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
 
-U_BOOT_DEVICE(stm32_serials) = {
-	.name = "serial_stm32",
-	.platdata = &serial_platdata,
-};
+	return 0;
+}
 
 u32 get_board_rev(void)
 {
@@ -292,15 +50,6 @@
 
 int board_early_init_f(void)
 {
-	int res;
-
-	configure_clocks();
-
-	res = uart_setup_gpio();
-	if (res)
-		return res;
-	clock_setup(USART1_CLOCK_CFG);
-
 	return 0;
 }
 
diff --git a/board/st/stm32f469-discovery/Kconfig b/board/st/stm32f469-discovery/Kconfig
new file mode 100644
index 0000000..de61b6f
--- /dev/null
+++ b/board/st/stm32f469-discovery/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STM32F469_DISCOVERY
+
+config SYS_BOARD
+	string
+	default "stm32f469-discovery"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stm32f4"
+
+config SYS_CONFIG_NAME
+	string
+	default "stm32f469-discovery"
+
+endif
diff --git a/board/st/stm32f469-discovery/MAINTAINERS b/board/st/stm32f469-discovery/MAINTAINERS
new file mode 100644
index 0000000..d3c791a
--- /dev/null
+++ b/board/st/stm32f469-discovery/MAINTAINERS
@@ -0,0 +1,6 @@
+STM32F469-DISCOVERY BOARD
+M:	Patrice Chotard <patrice.chotard@st.com>
+S:	Maintained
+F:	board/st/stm32f469-discovery/
+F:	include/configs/stm32f469-discovery.h
+F:	configs/stm32f469-discovery_defconfig
diff --git a/board/st/stm32f469-discovery/Makefile b/board/st/stm32f469-discovery/Makefile
new file mode 100644
index 0000000..9ecd61e
--- /dev/null
+++ b/board/st/stm32f469-discovery/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) STMicroelectronics SA 2017
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= stm32f469-discovery.o
diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c
new file mode 100644
index 0000000..36f7b2e
--- /dev/null
+++ b/board/st/stm32f469-discovery/stm32f469-discovery.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	int rv;
+	struct udevice *dev;
+
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+	if (fdtdec_setup_memory_size() != 0)
+		rv = -EINVAL;
+
+	return rv;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char serialno[25];
+	u32 u_id_low, u_id_mid, u_id_high;
+
+	if (!env_get("serial#")) {
+		u_id_low  = readl(&STM32_U_ID->u_id_low);
+		u_id_mid  = readl(&STM32_U_ID->u_id_mid);
+		u_id_high = readl(&STM32_U_ID->u_id_high);
+		sprintf(serialno, "%08x%08x%08x",
+			u_id_high, u_id_mid, u_id_low);
+		env_set("serial#", serialno);
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
index 30f518a..f458627 100644
--- a/board/varisys/cyrus/cyrus.c
+++ b/board/varisys/cyrus/cyrus.c
@@ -69,7 +69,7 @@
 	set_liodns();
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
+	setup_qbman_portals();
 #endif
 	print_lbc_regs();
 	return 0;
diff --git a/cmd/Kconfig b/cmd/Kconfig
index c033223..83dc778 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -914,6 +914,14 @@
 	help
 	  Enables the command "sdp" which is used to have U-Boot emulating the
 	  Serial Download Protocol (SDP) via USB.
+config CMD_ROCKUSB
+	bool "rockusb"
+	depends on USB_FUNCTION_ROCKUSB
+	help
+          Rockusb protocol is widely used by Rockchip SoC based devices. It can
+	  read/write info, image to/from devices. This enable rockusb command
+	  support to communication with rockusb device. for more detail about
+	  this command, please read doc/README.rockusb.
 
 config CMD_USB_MASS_STORAGE
 	bool "UMS usb mass storage"
diff --git a/cmd/Makefile b/cmd/Makefile
index ab45bf4..ce65cef 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,6 +105,7 @@
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
 obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
+obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o
 obj-$(CONFIG_SANDBOX) += host.o
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_CMD_NVME) += nvme.o
diff --git a/cmd/rockusb.c b/cmd/rockusb.c
new file mode 100644
index 0000000..af81cdc
--- /dev/null
+++ b/cmd/rockusb.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2017 Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <g_dnl.h>
+#include <usb.h>
+#include <asm/arch/f_rockusb.h>
+
+static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	int controller_index, dev_index;
+	char *usb_controller;
+	char *devtype;
+	char *devnum;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	usb_controller = argv[1];
+	controller_index = simple_strtoul(usb_controller, NULL, 0);
+
+	if (argc >= 4) {
+		devtype = argv[2];
+		devnum  = argv[3];
+	} else {
+		return CMD_RET_USAGE;
+	}
+	dev_index = simple_strtoul(devnum, NULL, 0);
+	rockusb_dev_init(devtype, dev_index);
+
+	ret = board_usb_init(controller_index, USB_INIT_DEVICE);
+	if (ret) {
+		printf("USB init failed: %d\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	g_dnl_clear_detach();
+	ret = g_dnl_register("usb_dnl_rockusb");
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	if (!g_dnl_board_usb_cable_connected()) {
+		puts("\rUSB cable not detected, Command exit.\n");
+		ret = CMD_RET_FAILURE;
+		goto exit;
+	}
+
+	while (1) {
+		if (g_dnl_detach())
+			break;
+		if (ctrlc())
+			break;
+		usb_gadget_handle_interrupts(controller_index);
+	}
+	ret = CMD_RET_SUCCESS;
+
+exit:
+	g_dnl_unregister();
+	g_dnl_clear_detach();
+	board_usb_cleanup(controller_index, USB_INIT_DEVICE);
+
+	return ret;
+}
+
+U_BOOT_CMD(rockusb, 4, 1, do_rockusb,
+	   "use the rockusb protocol",
+	   "<USB_controller> <devtype> <dev[:part]>  e.g. rockusb 0 mmc 0\n"
+);
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index b8e083c..4a09a5c 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -34,6 +34,7 @@
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index fc96401..04484e0 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -52,6 +52,9 @@
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 681e2a5..6c33cc90 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -55,6 +55,9 @@
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PALMAS=y
 CONFIG_DM_REGULATOR=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index c74a006..2a74784 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -22,6 +22,7 @@
 CONFIG_CMD_SF=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -78,6 +79,7 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
@@ -86,3 +88,8 @@
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 # CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 9576c30..81ed7d0 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -24,6 +24,7 @@
 CONFIG_CMD_SF=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -79,6 +80,7 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
@@ -88,3 +90,8 @@
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 # CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 197c242..0565c03 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -23,6 +23,7 @@
 CONFIG_CMD_SF=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -78,6 +79,7 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
@@ -88,3 +90,8 @@
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
 # CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index e944f97..6024b86 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -20,6 +20,7 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -74,6 +75,14 @@
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
 CONFIG_DISPLAY_ROCKCHIP_MIPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 008776e..d76e8c4 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -78,3 +78,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index bd7e1a0..e9eb20c 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -21,6 +21,7 @@
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -80,6 +81,7 @@
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
@@ -88,3 +90,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..a7466f1
--- /dev/null
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1088ARDB=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SECURE_BOOT=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_HASH_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SCSI_AHCI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 7478f9b1..d0bcbd8 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -83,3 +83,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 283a964..5a41c5c 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index d99c4f5..17043c2 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MVEBU_ARMADA_37XX=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_DEBUG_UART=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index bebc877..aea47c5 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -69,6 +69,7 @@
 CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
@@ -81,3 +82,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 7453aca..6b860bb 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -78,3 +78,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index c76a0b9..43dce46 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -20,6 +20,7 @@
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -70,6 +71,8 @@
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
@@ -78,3 +81,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index f7bcce3..0b3ec11 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -20,6 +20,7 @@
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_DOS_PARTITION=y
 # CONFIG_SPL_DOS_PARTITION is not set
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 8ed6169..2685881 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -35,6 +35,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 54c3495..f49d0ab 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -35,6 +35,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 2787b60..59b2dcf 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -37,6 +37,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index ecf6de3..17780af 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -34,6 +34,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 97a6c5e..d4ceb92 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -36,6 +36,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SPL_DM=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index bba90d9..10f0c82 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -32,6 +32,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 5bae037..ed057cf 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -36,6 +36,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 079d465..857f2f7 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -35,6 +35,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 35773e6..71bd8f1 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -36,6 +36,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 961b862..c8239e7 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -36,6 +36,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
 CONFIG_CMD_UBI=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index c5dbe89..d34d302 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -39,6 +39,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_PART=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
 CONFIG_CMD_UBI=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 9339e36..52bd931 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -1,7 +1,9 @@
 CONFIG_ARM=y
 CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
 CONFIG_STM32F4=y
 CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
@@ -14,7 +16,19 @@
 CONFIG_CMD_IMLS=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIMER=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_STM32_RCC=y
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
-CONFIG_OF_LIBFDT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_STM32=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_STM32_RESET=y
+CONFIG_STM32X7_SERIAL=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
new file mode 100644
index 0000000..afffddf
--- /dev/null
+++ b/configs/stm32f469-discovery_defconfig
@@ -0,0 +1,42 @@
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xF00
+CONFIG_STM32F4=y
+CONFIG_TARGET_STM32F469_DISCOVERY=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f469-disco"
+CONFIG_BOOTDELAY=3
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+# CONFIG_BLK is not set
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_MISC=y
+CONFIG_STM32_RCC=y
+CONFIG_DM_MMC=y
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_STM32=y
+CONFIG_RAM=y
+CONFIG_STM32_SDRAM=y
+CONFIG_DM_RESET=y
+CONFIG_STM32_RESET=y
+CONFIG_STM32X7_SERIAL=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index b661761..321321f 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -15,7 +15,11 @@
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
@@ -25,14 +29,23 @@
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+# CONFIG_BLK is not set
 CONFIG_CLK=y
 CONFIG_DM_GPIO=y
 CONFIG_MISC=y
 CONFIG_STM32_RCC=y
-# CONFIG_MMC is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index 1315be3..c79dffd 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -81,3 +81,8 @@
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig
index bbcf3b0..2edc3a9 100644
--- a/configs/uniphier_v8_defconfig
+++ b/configs/uniphier_v8_defconfig
@@ -34,6 +34,7 @@
 CONFIG_MMC_UNIPHIER=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_NAND=y
 CONFIG_NAND_DENALI_DT=y
 CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 7091586..30ad478 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -17,6 +17,9 @@
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -59,6 +62,28 @@
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_VBUS_DRAW=0
+CONFIG_G_DNL_MANUFACTURER="Rockchip"
+CONFIG_G_DNL_VENDOR_NUM=0x2207
+CONFIG_G_DNL_PRODUCT_NUM=0x320a
diff --git a/doc/README.rockusb b/doc/README.rockusb
new file mode 100644
index 0000000..5405dc4
--- /dev/null
+++ b/doc/README.rockusb
@@ -0,0 +1,51 @@
+Rockusb (Rockchip USB protocol)
+=====================================================
+
+Overview
+--------
+
+Rockusb protocol is widely used by Rockchip SoC based devices. It can
+read/write info, image to/from devices. This document briefly describes how to
+use Rockusb for upgrading firmware (e.g. kernel, u-boot, rootfs, etc.).
+
+Tools
+--------
+There are many tools can support Rockusb protocol. rkdeveloptool
+(https://github.com/rockchip-linux/rkdeveloptool) is open source,
+It is maintained by Rockchip. People don't want to build from source
+can download from here
+(https://github.com/rockchip-linux/rkbin/blob/master/tools/rkdeveloptool)
+
+Usage
+--------
+The Usage of Rockusb command is:
+
+rockusb <USB_controller> <devtype> <dev[:part]>
+
+e.g. rockusb 0 mmc 0
+
+On your U-Boot console, type this command to enter rockusb mode.
+On your host PC. use lsusb command. you should see a usb device
+using 0x2207 as its USB verdor id.
+
+for more detail about the rkdeveloptool. please read the usage.
+
+rkdeveloptool -h
+
+use rkdeveloptool wl command to write lba. BeginSec is the lba on device
+you want to write.
+
+sudo rkdeveloptool wl  <BeginSec> <File>
+
+to flash U-Boot image use below command. U-Boot binary is made by mkimage.
+see doc/README.rockchip for more detail about how to get U-Boot binary.
+
+sudo rkdeveloptool wl  64 <U-Boot binary>
+
+There are plenty of Rockusb command. but wl(write lba) and
+rd(reboot) command. These two command can let people flash
+image to device.
+
+To do
+-----
+* Fully support Rockusb protocol
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 634f071..63116e0 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -12,7 +12,6 @@
 
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
 #include <asm/arch/stm32_pwr.h>
 
 #include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -88,6 +87,12 @@
  */
 #define RCC_APB2ENR_SYSCFGEN		BIT(14)
 
+enum periph_clock {
+	SYSCFG_CLOCK_CFG,
+	TIMER2_CLOCK_CFG,
+	STMMAC_CLOCK_CFG,
+};
+
 struct stm32_clk_info stm32f4_clk_info = {
 	/* 180 MHz */
 	.sys_pll_psc = {
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 280ebb9..510a00a 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -347,6 +347,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 9);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index fca6899..6451c95 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -590,6 +590,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 9);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index ff52b55..c8a2413 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -402,6 +402,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 9);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index ac53239..b64c107 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -876,6 +876,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3288_cru, cru_softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 12);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 4d522a7..fa0c777 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -614,6 +614,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3328_cru, softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 12);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return ret;
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index bfeef39..a831991 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -543,6 +543,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3368_cru, softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 15);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return ret;
 }
 
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 2e85ac7..2f4c4e3 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1046,6 +1046,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3399_cru, softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 21);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return 0;
 }
 
@@ -1221,6 +1228,19 @@
 	return 0;
 }
 
+static int rk3399_pmuclk_bind(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	int ret;
+
+	ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 2);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+	return 0;
+}
+
 static const struct udevice_id rk3399_pmuclk_ids[] = {
 	{ .compatible = "rockchip,rk3399-pmucru" },
 	{ }
@@ -1234,6 +1254,7 @@
 	.ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
 	.ops		= &rk3399_pmuclk_ops,
 	.probe		= rk3399_pmuclk_probe,
+	.bind		= rk3399_pmuclk_bind,
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	.platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
 #endif
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index a119548..224c813 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -240,6 +240,13 @@
 		sys_child->priv = priv;
 	}
 
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+	ret = offsetof(struct rk3368_cru, softrst_con[0]);
+	ret = rockchip_reset_bind(dev, ret, 13);
+	if (ret)
+		debug("Warning: software reset driver bind faile\n");
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 201d7bf..8525679 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -48,7 +48,6 @@
 obj-$(CONFIG_TCA642X)		+= tca642x.o
 obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
 obj-$(CONFIG_LPC32XX_GPIO)	+= lpc32xx_gpio.o
-obj-$(CONFIG_STM32_GPIO)	+= stm32_gpio.o
 obj-$(CONFIG_STM32F7_GPIO)	+= stm32f7_gpio.o
 obj-$(CONFIG_GPIO_UNIPHIER)	+= gpio-uniphier.o
 obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
deleted file mode 100644
index c04cef4..0000000
--- a/drivers/gpio/stm32_gpio.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2011
- * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * Copyright 2015 ATS Advanced Telematics Systems GmbH
- * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const unsigned long io_base[] = {
-	STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
-	STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
-	STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
-};
-
-struct stm32_gpio_regs {
-	u32 moder;	/* GPIO port mode */
-	u32 otyper;	/* GPIO port output type */
-	u32 ospeedr;	/* GPIO port output speed */
-	u32 pupdr;	/* GPIO port pull-up/pull-down */
-	u32 idr;	/* GPIO port input data */
-	u32 odr;	/* GPIO port output data */
-	u32 bsrr;	/* GPIO port bit set/reset */
-	u32 lckr;	/* GPIO port configuration lock */
-	u32 afr[2];	/* GPIO alternate function */
-};
-
-#define CHECK_DSC(x)	(!x || x->port > 8 || x->pin > 15)
-#define CHECK_CTL(x)	(!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
-			x->pupd > 2 || x->speed > 3)
-
-int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
-		const struct stm32_gpio_ctl *ctl)
-{
-	struct stm32_gpio_regs *gpio_regs;
-	u32 i;
-	int rv;
-
-	if (CHECK_DSC(dsc)) {
-		rv = -EINVAL;
-		goto out;
-	}
-	if (CHECK_CTL(ctl)) {
-		rv = -EINVAL;
-		goto out;
-	}
-
-	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
-	i = (dsc->pin & 0x07) * 4;
-	clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
-
-	i = dsc->pin * 2;
-
-	clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
-	clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
-	clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
-	clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
-
-	rv = 0;
-out:
-	return rv;
-}
-
-int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
-{
-	struct stm32_gpio_regs	*gpio_regs;
-	int rv;
-
-	if (CHECK_DSC(dsc)) {
-		rv = -EINVAL;
-		goto out;
-	}
-
-	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-
-	if (state)
-		writel(1 << dsc->pin, &gpio_regs->bsrr);
-	else
-		writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
-
-	rv = 0;
-out:
-	return rv;
-}
-
-int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
-{
-	struct stm32_gpio_regs	*gpio_regs;
-	int rv;
-
-	if (CHECK_DSC(dsc)) {
-		rv = -EINVAL;
-		goto out;
-	}
-
-	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
-	rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
-out:
-	return rv;
-}
-
-/* Common GPIO API */
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
-	return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	struct stm32_gpio_dsc dsc;
-	struct stm32_gpio_ctl ctl;
-
-	dsc.port = stm32_gpio_to_port(gpio);
-	dsc.pin = stm32_gpio_to_pin(gpio);
-	ctl.af = STM32_GPIO_AF0;
-	ctl.mode = STM32_GPIO_MODE_IN;
-	ctl.otype = STM32_GPIO_OTYPE_PP;
-	ctl.pupd = STM32_GPIO_PUPD_NO;
-	ctl.speed = STM32_GPIO_SPEED_50M;
-
-	return stm32_gpio_config(&dsc, &ctl);
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	struct stm32_gpio_dsc dsc;
-	struct stm32_gpio_ctl ctl;
-	int res;
-
-	dsc.port = stm32_gpio_to_port(gpio);
-	dsc.pin = stm32_gpio_to_pin(gpio);
-	ctl.af = STM32_GPIO_AF0;
-	ctl.mode = STM32_GPIO_MODE_OUT;
-	ctl.pupd = STM32_GPIO_PUPD_NO;
-	ctl.speed = STM32_GPIO_SPEED_50M;
-
-	res = stm32_gpio_config(&dsc, &ctl);
-	if (res < 0)
-		goto out;
-	res = stm32_gpout_set(&dsc, value);
-out:
-	return res;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	struct stm32_gpio_dsc dsc;
-
-	dsc.port = stm32_gpio_to_port(gpio);
-	dsc.pin = stm32_gpio_to_pin(gpio);
-
-	return stm32_gpin_get(&dsc);
-}
-
-int gpio_set_value(unsigned gpio, int value)
-{
-	struct stm32_gpio_dsc dsc;
-
-	dsc.port = stm32_gpio_to_port(gpio);
-	dsc.pin = stm32_gpio_to_pin(gpio);
-
-	return stm32_gpout_set(&dsc, value);
-}
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ada7624..e8d598c 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,3 +53,4 @@
 obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
 obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
new file mode 100644
index 0000000..3b3dd02
--- /dev/null
+++ b/drivers/misc/fsl_portals.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#ifdef CONFIG_PPC
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
+#include <fsl_qbman.h>
+
+#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+void setup_qbman_portals(void)
+{
+	void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
+				CONFIG_SYS_BMAN_SWP_ISDR_REG;
+	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
+				CONFIG_SYS_QMAN_SWP_ISDR_REG;
+#ifdef CONFIG_PPC
+	struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+
+	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
+#ifdef CONFIG_PHYS_64BIT
+	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+#endif
+	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+#endif
+#ifdef CONFIG_FSL_CORENET
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+		u8 sdest = qp_info[i].sdest;
+		u16 fliodn = qp_info[i].fliodn;
+		u16 dliodn = qp_info[i].dliodn;
+		u16 liodn_off = qp_info[i].liodn_offset;
+
+		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
+					dliodn);
+		/* set frame liodn */
+		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
+	}
+#endif
+
+	/* Change default state of BMan ISDR portals to all 1s */
+	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+			CONFIG_SYS_BMAN_SP_CINH_SIZE);
+	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+			CONFIG_SYS_QMAN_SP_CINH_SIZE);
+}
+
+void inhibit_portals(void __iomem *addr, int max_portals,
+		     int arch_max_portals, int portal_cinh_size)
+{
+	u32 val;
+	int i;
+
+	/* arch_max_portals is the maximum based on memory size. This includes
+	 * the reserved memory in the SoC.  max_portals the number of physical
+	 * portals in the SoC
+	 */
+	if (max_portals > arch_max_portals) {
+		printf("ERROR: portal config error\n");
+		max_portals = arch_max_portals;
+	}
+
+	for (i = 0; i < max_portals; i++) {
+		out_be32(addr, -1);
+		val = in_be32(addr);
+		if (!val) {
+			printf("ERROR: Stopped after %d portals\n", i);
+			return;
+		}
+		addr += portal_cinh_size;
+	}
+	debug("Cleared %d portals\n", i);
+}
+
+#ifdef CONFIG_PPC
+static int fdt_qportal(void *blob, int off, int id, char *name,
+		       enum fsl_dpaa_dev dev, int create)
+{
+	int childoff, dev_off, ret = 0;
+	u32 dev_handle;
+#ifdef CONFIG_FSL_CORENET
+	int num;
+	u32 liodns[2];
+#endif
+
+	childoff = fdt_subnode_offset(blob, off, name);
+	if (create) {
+		char handle[64], *p;
+
+		strncpy(handle, name, sizeof(handle));
+		p = strchr(handle, '@');
+		if (!strncmp(name, "fman", 4)) {
+			*p = *(p + 1);
+			p++;
+		}
+		*p = '\0';
+
+		dev_off = fdt_path_offset(blob, handle);
+		/* skip this node if alias is not found */
+		if (dev_off == -FDT_ERR_BADPATH)
+			return 0;
+		if (dev_off < 0)
+			return dev_off;
+
+		if (childoff <= 0)
+			childoff = fdt_add_subnode(blob, off, name);
+
+		/* need to update the dev_off after adding a subnode */
+		dev_off = fdt_path_offset(blob, handle);
+		if (dev_off < 0)
+			return dev_off;
+
+		if (childoff > 0) {
+			dev_handle = fdt_get_phandle(blob, dev_off);
+			if (dev_handle <= 0) {
+				dev_handle = fdt_alloc_phandle(blob);
+				ret = fdt_set_phandle(blob, dev_off,
+						      dev_handle);
+				if (ret < 0)
+					return ret;
+			}
+
+			ret = fdt_setprop(blob, childoff, "dev-handle",
+					  &dev_handle, sizeof(dev_handle));
+			if (ret < 0)
+				return ret;
+
+#ifdef CONFIG_FSL_CORENET
+			num = get_dpaa_liodn(dev, &liodns[0], id);
+			ret = fdt_setprop(blob, childoff, "fsl,liodn",
+					  &liodns[0], sizeof(u32) * num);
+			if (!strncmp(name, "pme", 3)) {
+				u32 pme_rev1, pme_rev2;
+				ccsr_pme_t *pme_regs =
+					(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+
+				pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
+				pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
+				ret = fdt_setprop(blob, childoff,
+						  "fsl,pme-rev1", &pme_rev1,
+						  sizeof(u32));
+				if (ret < 0)
+					return ret;
+				ret = fdt_setprop(blob, childoff,
+						  "fsl,pme-rev2", &pme_rev2,
+						  sizeof(u32));
+			}
+#endif
+		} else {
+			return childoff;
+		}
+	} else {
+		if (childoff > 0)
+			ret = fdt_del_node(blob, childoff);
+	}
+
+	return ret;
+}
+#endif /* CONFIG_PPC */
+
+void fdt_fixup_qportals(void *blob)
+{
+	int off, err;
+	unsigned int maj, min;
+	unsigned int ip_cfg;
+	struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
+	u32 rev_1 = in_be32(&qman->ip_rev_1);
+	u32 rev_2 = in_be32(&qman->ip_rev_2);
+	char compat[64];
+	int compat_len;
+
+	maj = (rev_1 >> 8) & 0xff;
+	min = rev_1 & 0xff;
+	ip_cfg = rev_2 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+			     maj, min, ip_cfg) + 1;
+	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
+	while (off != -FDT_ERR_NOTFOUND) {
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+		u32 liodns[2];
+#endif
+		const int *ci = fdt_getprop(blob, off, "cell-index", &err);
+		int i;
+
+		if (!ci)
+			goto err;
+
+		i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+		int j;
+#endif
+
+#endif /* CONFIG_PPC */
+		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+		if (err < 0)
+			goto err;
+#ifdef CONFIG_PPC
+#ifdef CONFIG_FSL_CORENET
+		liodns[0] = qp_info[i].dliodn;
+		liodns[1] = qp_info[i].fliodn;
+		err = fdt_setprop(blob, off, "fsl,liodn",
+				  &liodns, sizeof(u32) * 2);
+		if (err < 0)
+			goto err;
+#endif
+
+		i++;
+
+		err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
+				  IS_E_PROCESSOR(get_svr()));
+		if (err < 0)
+			goto err;
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_DPAA_PME
+		err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
+		if (err < 0)
+			goto err;
+#else
+		fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+			char name[] = "fman@0";
+
+			name[sizeof(name) - 2] = '0' + j;
+			err = fdt_qportal(blob, off, i, name,
+					  FSL_HW_PORTAL_FMAN1 + j, 1);
+			if (err < 0)
+				goto err;
+		}
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+		err = fdt_qportal(blob, off, i, "rman@0",
+				  FSL_HW_PORTAL_RMAN, 1);
+		if (err < 0)
+			goto err;
+#endif
+#endif /* CONFIG_PPC */
+
+err:
+		if (err < 0) {
+			printf("ERROR: unable to create props for %s: %s\n",
+			       fdt_get_name(blob, off, NULL),
+			       fdt_strerror(err));
+			return;
+		}
+
+		off = fdt_node_offset_by_compatible(blob, off,
+						    "fsl,qman-portal");
+	}
+}
+
+void fdt_fixup_bportals(void *blob)
+{
+	int off, err;
+	unsigned int maj, min;
+	unsigned int ip_cfg;
+	struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
+	u32 rev_1 = in_be32(&bman->ip_rev_1);
+	u32 rev_2 = in_be32(&bman->ip_rev_2);
+	char compat[64];
+	int compat_len;
+
+	maj = (rev_1 >> 8) & 0xff;
+	min = rev_1 & 0xff;
+
+	ip_cfg = rev_2 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+			     maj, min, ip_cfg) + 1;
+	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
+	while (off != -FDT_ERR_NOTFOUND) {
+		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
+		if (err < 0) {
+			printf("ERROR: unable to create props for %s: %s\n",
+			       fdt_get_name(blob, off, NULL),
+			       fdt_strerror(err));
+			return;
+		}
+
+		off = fdt_node_offset_by_compatible(blob, off,
+						    "fsl,bman-portal");
+	}
+}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index d42d915..46b17b1 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -160,12 +160,12 @@
 	  This MAC is present in Andestech SoCs.
 
 config MVNETA
-	bool "Marvell Armada 385 network interface support"
-	depends on ARMADA_XP || ARMADA_38X
+	bool "Marvell Armada XP/385/3700 network interface support"
+	depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
 	select PHYLIB
 	help
 	  This driver supports the network interface units in the
-	  Marvell ARMADA XP and 38X SoCs
+	  Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs
 
 config MVPP2
 	bool "Marvell Armada 375/7K/8K network interface support"
@@ -373,4 +373,28 @@
 	  The PHY does not have a RXERR line (RMII only).
 	  (so program the FEC to ignore it).
 
+config SYS_DPAA_QBMAN
+	bool "Device tree fixup for QBMan on freescale SOCs"
+	depends on (ARM || PPC) && !SPL_BUILD
+	default y if ARCH_B4860 || \
+		     ARCH_B4420 || \
+		     ARCH_P1023 || \
+		     ARCH_P2041 || \
+		     ARCH_T1023 || \
+		     ARCH_T1024 || \
+		     ARCH_T1040 || \
+		     ARCH_T1042 || \
+		     ARCH_T2080 || \
+		     ARCH_T2081 || \
+		     ARCH_T4240 || \
+		     ARCH_T4160 || \
+		     ARCH_P4080 || \
+		     ARCH_P3041 || \
+		     ARCH_P5040 || \
+		     ARCH_P5020 || \
+		     ARCH_LS1043A || \
+		     ARCH_LS1046A
+	help
+	  QBman fixups to allow deep sleep in DPAA 1 SOCs
+
 endif # NETDEVICES
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 5eb12ef..5410897 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -29,7 +29,6 @@
 obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
-obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c
deleted file mode 100644
index d48e1e6..0000000
--- a/drivers/pci/tsi108_pci.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * (C) Copyright 2004 Tundra Semiconductor Corp.
- * Alex Bounine <alexandreb@tundra.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * PCI initialisation for the Tsi108 EMU board.
- */
-
-#include <config.h>
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <tsi108.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-struct pci_controller local_hose;
-
-void tsi108_clear_pci_error (void)
-{
-	u32 err_stat, err_addr, pci_stat;
-
-	/*
-	 * Quietly clear errors signalled as result of PCI/X configuration read
-	 * requests.
-	 */
-	/* Read PB Error Log Registers */
-	err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
-				     TSI108_PB_REG_OFFSET + PB_ERRCS);
-	err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
-				     TSI108_PB_REG_OFFSET + PB_AERR);
-	if (err_stat & PB_ERRCS_ES) {
-		/* Clear PCI/X bus errors if applicable */
-		if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
-			/* Clear error flag */
-			*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
-				  TSI108_PB_REG_OFFSET + PB_ERRCS) =
-			    PB_ERRCS_ES;
-
-			/* Clear read error reported in PB_ISR */
-			*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
-				  TSI108_PB_REG_OFFSET + PB_ISR) =
-			    PB_ISR_PBS_RD_ERR;
-
-		/* Clear errors reported by PCI CSR (Normally Master Abort) */
-			pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
-						     TSI108_PCI_REG_OFFSET +
-						     PCI_CSR);
-			*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
-					  TSI108_PCI_REG_OFFSET + PCI_CSR) =
-			    pci_stat;
-
-			*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
-					  TSI108_PCI_REG_OFFSET +
-					  PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
-		}
-	}
-
-	return;
-}
-
-unsigned int __get_pci_config_dword (u32 addr)
-{
-	unsigned int retval;
-
-	__asm__ __volatile__ ("       lwbrx %0,0,%1\n"
-			     "1:     eieio\n"
-			     "2:\n"
-			     ".section .fixup,\"ax\"\n"
-			     "3:     li %0,-1\n"
-			     "       b 2b\n"
-			     ".section __ex_table,\"a\"\n"
-			     "       .align 2\n"
-			     "       .long 1b,3b\n"
-			     ".section .text.__get_pci_config_dword"
-				: "=r"(retval) : "r"(addr));
-
-	return (retval);
-}
-
-static int tsi108_read_config_dword (struct pci_controller *hose,
-				    pci_dev_t dev, int offset, u32 * value)
-{
-	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
-	dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
-	*value = __get_pci_config_dword(dev);
-	if (0xFFFFFFFF == *value)
-		tsi108_clear_pci_error ();
-	return 0;
-}
-
-static int tsi108_write_config_dword (struct pci_controller *hose,
-				     pci_dev_t dev, int offset, u32 value)
-{
-	dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
-	dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
-
-	out_le32 ((volatile unsigned *)dev, value);
-
-	return 0;
-}
-
-void pci_init_board (void)
-{
-	struct pci_controller *hose = (struct pci_controller *)&local_hose;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	pci_set_region (hose->regions + 0,
-		       CONFIG_SYS_PCI_MEMORY_BUS,
-		       CONFIG_SYS_PCI_MEMORY_PHYS,
-		       CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* PCI memory space */
-	pci_set_region (hose->regions + 1,
-		       CONFIG_SYS_PCI_MEM_BUS,
-		       CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region (hose->regions + 2,
-		       CONFIG_SYS_PCI_IO_BUS,
-		       CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
-	hose->region_count = 3;
-
-	pci_set_ops (hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    tsi108_read_config_dword,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    tsi108_write_config_dword);
-
-	pci_register_hose (hose);
-
-	hose->last_busno = pci_hose_scan (hose);
-
-	debug ("Done PCI initialization\n");
-	return;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-	int nodeoffset;
-	int tmp[2];
-	const char *path;
-
-	nodeoffset = fdt_path_offset(blob, "/aliases");
-	if (nodeoffset >= 0) {
-		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
-		if (path) {
-			tmp[0] = cpu_to_be32(local_hose.first_busno);
-			tmp[1] = cpu_to_be32(local_hose.last_busno);
-			do_fixup_by_path(blob, path, "bus-range",
-				&tmp, sizeof(tmp), 1);
-		}
-	}
-}
-#endif /* CONFIG_OF_LIBFDT */
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index a9388ff..07d4f3e 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -1,14 +1,14 @@
 if ARCH_MVEBU
 
 config PINCTRL_ARMADA_37XX
-	depends on ARMADA_3700
+	depends on ARMADA_3700 && PINCTRL_FULL
 	bool "Armada 37xx pin control driver"
 	help
 	   Support pin multiplexing and pin configuration control on
 	   Marvell's Armada-37xx SoC.
 
 config PINCTRL_ARMADA_8K
-	depends on ARMADA_8K
+	depends on ARMADA_8K && PINCTRL_FULL
 	bool "Armada 7k/8k pin control driver"
 	help
 	   Support pin multiplexing and pin configuration control on
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 51fdfb3..2066e11 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -182,6 +182,8 @@
 };
 
 static const struct udevice_id stm32_pinctrl_ids[] = {
+	{ .compatible = "st,stm32f429-pinctrl" },
+	{ .compatible = "st,stm32f469-pinctrl" },
 	{ .compatible = "st,stm32f746-pinctrl" },
 	{ .compatible = "st,stm32h743-pinctrl" },
 	{ }
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 6e92b22..ec2edd6 100644
--- a/drivers/ram/stm32_sdram.c
+++ b/drivers/ram/stm32_sdram.c
@@ -11,6 +11,9 @@
 #include <ram.h>
 #include <asm/io.h>
 
+#define MEM_MODE_MASK	GENMASK(2, 0)
+#define NOT_FOUND	0xff
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_fmc_regs {
@@ -253,9 +256,31 @@
 {
 	struct stm32_sdram_params *params = dev_get_platdata(dev);
 	struct bank_params *bank_params;
+	struct ofnode_phandle_args args;
+	u32 *syscfg_base;
+	u32 mem_remap;
 	ofnode bank_node;
 	char *bank_name;
 	u8 bank = 0;
+	int ret;
+
+	mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
+	if (mem_remap != NOT_FOUND) {
+		ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
+						 &args);
+		if (ret) {
+			debug("%s: can't find syscon device (%d)\n", __func__,
+			      ret);
+			return ret;
+		}
+
+		syscfg_base = (u32 *)ofnode_get_addr(args.node);
+
+		/* set memory mapping selection */
+		clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
+	} else {
+		debug("%s: cannot find st,mem_remap property\n", __func__);
+	}
 
 	dev_for_each_subnode(bank_node, dev) {
 		/* extract the bank index from DT */
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ce46e27..3964b9e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -74,4 +74,13 @@
 	  resets that are supported by watchdog. The main limitation though
 	  is that some reset signals, like I2C or MISC reset multiple devices.
 
+config RESET_ROCKCHIP
+	bool "Reset controller driver for Rockchip SoCs"
+	depends on DM_RESET && ARCH_ROCKCHIP && CLK
+	default y
+	help
+	  Support for reset controller on rockchip SoC. The main limitation
+	  though is that some reset signals, like I2C or MISC reset multiple
+	  devices.
+
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 252cefe..7d7e080 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,3 +12,4 @@
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c
new file mode 100644
index 0000000..01047a2
--- /dev/null
+++ b/drivers/reset/reset-rockchip.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <linux/io.h>
+#include <asm/arch/hardware.h>
+#include <dm/lists.h>
+/*
+ * Each reg has 16 bits reset signal for devices
+ * Note: Not including rk2818 and older SoCs
+ */
+#define ROCKCHIP_RESET_NUM_IN_REG	16
+
+struct rockchip_reset_priv {
+	void __iomem *base;
+	/* Rockchip reset reg locate at cru controller */
+	u32 reset_reg_offset;
+	/* Rockchip reset reg number */
+	u32 reset_reg_num;
+};
+
+static int rockchip_reset_request(struct reset_ctl *reset_ctl)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
+
+	if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int rockchip_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int bank =  reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+	int offset =  reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id,
+	      priv->base + (bank * 4));
+
+	rk_setreg(priv->base + (bank * 4), BIT(offset));
+
+	return 0;
+}
+
+static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int bank =  reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
+	int offset =  reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
+
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
+	      reset_ctl, reset_ctl->dev, reset_ctl->id,
+	      priv->base + (bank * 4));
+
+	rk_clrreg(priv->base + (bank * 4), BIT(offset));
+
+	return 0;
+}
+
+struct reset_ops rockchip_reset_ops = {
+	.request = rockchip_reset_request,
+	.free = rockchip_reset_free,
+	.rst_assert = rockchip_reset_assert,
+	.rst_deassert = rockchip_reset_deassert,
+};
+
+static int rockchip_reset_probe(struct udevice *dev)
+{
+	struct rockchip_reset_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+
+	addr = dev_read_addr_size(dev, "reg", &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0))
+		return -EINVAL;
+
+	addr += priv->reset_reg_offset;
+	priv->base = ioremap(addr, size);
+
+	debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__,
+	      priv->base, priv->reset_reg_offset, priv->reset_reg_num);
+
+	return 0;
+}
+
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+	struct udevice *rst_dev;
+	struct rockchip_reset_priv *priv;
+	int ret;
+
+	 ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset",
+					  dev_ofnode(pdev), &rst_dev);
+	if (ret) {
+		debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+		return ret;
+	}
+	priv = malloc(sizeof(struct rockchip_reset_priv));
+	priv->reset_reg_offset = reg_offset;
+	priv->reset_reg_num = reg_number;
+	rst_dev->priv = priv;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_reset) = {
+	.name = "rockchip_reset",
+	.id = UCLASS_RESET,
+	.probe = rockchip_reset_probe,
+	.ops = &rockchip_reset_ops,
+	.priv_auto_alloc_size = sizeof(struct rockchip_reset_priv),
+};
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
deleted file mode 100644
index c793ba6..0000000
--- a/drivers/serial/serial_stm32.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <serial.h>
-#include <asm/arch/stm32.h>
-#include <dm/platform_data/serial_stm32.h>
-
-struct stm32_usart {
-	u32 sr;
-	u32 dr;
-	u32 brr;
-	u32 cr1;
-	u32 cr2;
-	u32 cr3;
-	u32 gtpr;
-};
-
-#define USART_CR1_RE			(1 << 2)
-#define USART_CR1_TE			(1 << 3)
-#define USART_CR1_UE			(1 << 13)
-
-#define USART_SR_FLAG_RXNE	(1 << 5)
-#define USART_SR_FLAG_TXE		(1 << 7)
-
-#define USART_BRR_F_MASK		0xF
-#define USART_BRR_M_SHIFT	4
-#define USART_BRR_M_MASK	0xFFF0
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
-{
-	struct stm32_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
-	u32  clock, int_div, frac_div, tmp;
-
-	if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE)
-		clock = clock_get(CLOCK_APB1);
-	else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE)
-		clock = clock_get(CLOCK_APB2);
-	else
-		return -EINVAL;
-
-	int_div = (25 * clock) / (4 * baudrate);
-	tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK;
-	frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT));
-	tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK;
-	writel(tmp, &usart->brr);
-
-	return 0;
-}
-
-static int stm32_serial_getc(struct udevice *dev)
-{
-	struct stm32_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
-
-	if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
-		return -EAGAIN;
-
-	return readl(&usart->dr);
-}
-
-static int stm32_serial_putc(struct udevice *dev, const char c)
-{
-	struct stm32_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
-
-	if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
-		return -EAGAIN;
-
-	writel(c, &usart->dr);
-
-	return 0;
-}
-
-static int stm32_serial_pending(struct udevice *dev, bool input)
-{
-	struct stm32_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
-
-	if (input)
-		return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
-	else
-		return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
-}
-
-static int stm32_serial_probe(struct udevice *dev)
-{
-	struct stm32_serial_platdata *plat = dev->platdata;
-	struct stm32_usart *const usart = plat->base;
-	setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
-
-	return 0;
-}
-
-static const struct dm_serial_ops stm32_serial_ops = {
-	.putc = stm32_serial_putc,
-	.pending = stm32_serial_pending,
-	.getc = stm32_serial_getc,
-	.setbrg = stm32_serial_setbrg,
-};
-
-U_BOOT_DRIVER(serial_stm32) = {
-	.name = "serial_stm32",
-	.id = UCLASS_SERIAL,
-	.ops = &stm32_serial_ops,
-	.probe = stm32_serial_probe,
-	.flags = DM_FLAG_PRE_RELOC,
-};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 102a63b..c387f5e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -134,6 +134,14 @@
 	  allows to download images into memory and execute (jump to) them
 	  using the same protocol as implemented by the i.MX family's boot ROM.
 
+config USB_FUNCTION_ROCKUSB
+        bool "Enable USB rockusb gadget"
+        help
+          Rockusb protocol is widely used by Rockchip SoC based devices. It can
+          read/write info, image to/from devices. This enables the USB part of
+          the rockusb gadget.for more detail about Rockusb protocol, please see
+          doc/README.rockusb
+
 endif # USB_GADGET_DOWNLOAD
 
 config USB_ETHER
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 7258099..ee8bc99 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -30,6 +30,7 @@
 obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
 obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
 obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o
+obj-$(CONFIG_USB_FUNCTION_ROCKUSB) += f_rockusb.o
 endif
 endif
 ifdef CONFIG_USB_ETHER
diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c
new file mode 100644
index 0000000..d5a10f1
--- /dev/null
+++ b/drivers/usb/gadget/f_rockusb.c
@@ -0,0 +1,718 @@
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/compiler.h>
+#include <version.h>
+#include <g_dnl.h>
+#include <asm/arch/f_rockusb.h>
+
+static inline struct f_rockusb *func_to_rockusb(struct usb_function *f)
+{
+	return container_of(f, struct f_rockusb, usb_function);
+}
+
+static struct usb_endpoint_descriptor fs_ep_in = {
+	.bLength            = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType    = USB_DT_ENDPOINT,
+	.bEndpointAddress   = USB_DIR_IN,
+	.bmAttributes       = USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize     = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor fs_ep_out = {
+	.bLength		= USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType	= USB_DT_ENDPOINT,
+	.bEndpointAddress	= USB_DIR_OUT,
+	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize		= cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor hs_ep_in = {
+	.bLength		= USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType	= USB_DT_ENDPOINT,
+	.bEndpointAddress	= USB_DIR_IN,
+	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize		= cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_ep_out = {
+	.bLength		= USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType	= USB_DT_ENDPOINT,
+	.bEndpointAddress	= USB_DIR_OUT,
+	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize		= cpu_to_le16(512),
+};
+
+static struct usb_interface_descriptor interface_desc = {
+	.bLength		= USB_DT_INTERFACE_SIZE,
+	.bDescriptorType	= USB_DT_INTERFACE,
+	.bInterfaceNumber	= 0x00,
+	.bAlternateSetting	= 0x00,
+	.bNumEndpoints		= 0x02,
+	.bInterfaceClass	= ROCKUSB_INTERFACE_CLASS,
+	.bInterfaceSubClass	= ROCKUSB_INTERFACE_SUB_CLASS,
+	.bInterfaceProtocol	= ROCKUSB_INTERFACE_PROTOCOL,
+};
+
+static struct usb_descriptor_header *rkusb_fs_function[] = {
+	(struct usb_descriptor_header *)&interface_desc,
+	(struct usb_descriptor_header *)&fs_ep_in,
+	(struct usb_descriptor_header *)&fs_ep_out,
+};
+
+static struct usb_descriptor_header *rkusb_hs_function[] = {
+	(struct usb_descriptor_header *)&interface_desc,
+	(struct usb_descriptor_header *)&hs_ep_in,
+	(struct usb_descriptor_header *)&hs_ep_out,
+	NULL,
+};
+
+static const char rkusb_name[] = "Rockchip Rockusb";
+
+static struct usb_string rkusb_string_defs[] = {
+	[0].s = rkusb_name,
+	{  }			/* end of list */
+};
+
+static struct usb_gadget_strings stringtab_rkusb = {
+	.language	= 0x0409,	/* en-us */
+	.strings	= rkusb_string_defs,
+};
+
+static struct usb_gadget_strings *rkusb_strings[] = {
+	&stringtab_rkusb,
+	NULL,
+};
+
+static struct f_rockusb *rockusb_func;
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
+static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size);
+
+struct f_rockusb *get_rkusb(void)
+{
+	struct f_rockusb *f_rkusb = rockusb_func;
+
+	if (!f_rkusb) {
+		f_rkusb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_rkusb));
+		if (!f_rkusb)
+			return 0;
+
+		rockusb_func = f_rkusb;
+		memset(f_rkusb, 0, sizeof(*f_rkusb));
+	}
+
+	if (!f_rkusb->buf_head) {
+		f_rkusb->buf_head = memalign(CONFIG_SYS_CACHELINE_SIZE,
+					     RKUSB_BUF_SIZE);
+		if (!f_rkusb->buf_head)
+			return 0;
+
+		f_rkusb->buf = f_rkusb->buf_head;
+		memset(f_rkusb->buf_head, 0, RKUSB_BUF_SIZE);
+	}
+	return f_rkusb;
+}
+
+static struct usb_endpoint_descriptor *rkusb_ep_desc(
+struct usb_gadget *g,
+struct usb_endpoint_descriptor *fs,
+struct usb_endpoint_descriptor *hs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
+static void rockusb_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	int status = req->status;
+
+	if (!status)
+		return;
+	debug("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual);
+}
+
+/* config the rockusb device*/
+static int rockusb_bind(struct usb_configuration *c, struct usb_function *f)
+{
+	int id;
+	struct usb_gadget *gadget = c->cdev->gadget;
+	struct f_rockusb *f_rkusb = func_to_rockusb(f);
+	const char *s;
+
+	id = usb_interface_id(c, f);
+	if (id < 0)
+		return id;
+	interface_desc.bInterfaceNumber = id;
+
+	id = usb_string_id(c->cdev);
+	if (id < 0)
+		return id;
+
+	rkusb_string_defs[0].id = id;
+	interface_desc.iInterface = id;
+
+	f_rkusb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in);
+	if (!f_rkusb->in_ep)
+		return -ENODEV;
+	f_rkusb->in_ep->driver_data = c->cdev;
+
+	f_rkusb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out);
+	if (!f_rkusb->out_ep)
+		return -ENODEV;
+	f_rkusb->out_ep->driver_data = c->cdev;
+
+	f->descriptors = rkusb_fs_function;
+
+	if (gadget_is_dualspeed(gadget)) {
+		hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress;
+		hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+		f->hs_descriptors = rkusb_hs_function;
+	}
+
+	s = env_get("serial#");
+	if (s)
+		g_dnl_set_serialnumber((char *)s);
+
+	return 0;
+}
+
+static void rockusb_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+	/* clear the configuration*/
+	memset(rockusb_func, 0, sizeof(*rockusb_func));
+}
+
+static void rockusb_disable(struct usb_function *f)
+{
+	struct f_rockusb *f_rkusb = func_to_rockusb(f);
+
+	usb_ep_disable(f_rkusb->out_ep);
+	usb_ep_disable(f_rkusb->in_ep);
+
+	if (f_rkusb->out_req) {
+		free(f_rkusb->out_req->buf);
+		usb_ep_free_request(f_rkusb->out_ep, f_rkusb->out_req);
+		f_rkusb->out_req = NULL;
+	}
+	if (f_rkusb->in_req) {
+		free(f_rkusb->in_req->buf);
+		usb_ep_free_request(f_rkusb->in_ep, f_rkusb->in_req);
+		f_rkusb->in_req = NULL;
+	}
+	if (f_rkusb->buf_head) {
+		free(f_rkusb->buf_head);
+		f_rkusb->buf_head = NULL;
+		f_rkusb->buf = NULL;
+	}
+}
+
+static struct usb_request *rockusb_start_ep(struct usb_ep *ep)
+{
+	struct usb_request *req;
+
+	req = usb_ep_alloc_request(ep, 0);
+	if (!req)
+		return NULL;
+
+	req->length = EP_BUFFER_SIZE;
+	req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE);
+	if (!req->buf) {
+		usb_ep_free_request(ep, req);
+		return NULL;
+	}
+	memset(req->buf, 0, req->length);
+
+	return req;
+}
+
+static int rockusb_set_alt(struct usb_function *f, unsigned int interface,
+			   unsigned int alt)
+{
+	int ret;
+	struct usb_composite_dev *cdev = f->config->cdev;
+	struct usb_gadget *gadget = cdev->gadget;
+	struct f_rockusb *f_rkusb = func_to_rockusb(f);
+	const struct usb_endpoint_descriptor *d;
+
+	debug("%s: func: %s intf: %d alt: %d\n",
+	      __func__, f->name, interface, alt);
+
+	d = rkusb_ep_desc(gadget, &fs_ep_out, &hs_ep_out);
+	ret = usb_ep_enable(f_rkusb->out_ep, d);
+	if (ret) {
+		printf("failed to enable out ep\n");
+		return ret;
+	}
+
+	f_rkusb->out_req = rockusb_start_ep(f_rkusb->out_ep);
+	if (!f_rkusb->out_req) {
+		printf("failed to alloc out req\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	f_rkusb->out_req->complete = rx_handler_command;
+
+	d = rkusb_ep_desc(gadget, &fs_ep_in, &hs_ep_in);
+	ret = usb_ep_enable(f_rkusb->in_ep, d);
+	if (ret) {
+		printf("failed to enable in ep\n");
+		goto err;
+	}
+
+	f_rkusb->in_req = rockusb_start_ep(f_rkusb->in_ep);
+	if (!f_rkusb->in_req) {
+		printf("failed alloc req in\n");
+		ret = -EINVAL;
+		goto err;
+	}
+	f_rkusb->in_req->complete = rockusb_complete;
+
+	ret = usb_ep_queue(f_rkusb->out_ep, f_rkusb->out_req, 0);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	rockusb_disable(f);
+	return ret;
+}
+
+static int rockusb_add(struct usb_configuration *c)
+{
+	struct f_rockusb *f_rkusb = get_rkusb();
+	int status;
+
+	debug("%s: cdev: 0x%p\n", __func__, c->cdev);
+
+	f_rkusb->usb_function.name = "f_rockusb";
+	f_rkusb->usb_function.bind = rockusb_bind;
+	f_rkusb->usb_function.unbind = rockusb_unbind;
+	f_rkusb->usb_function.set_alt = rockusb_set_alt;
+	f_rkusb->usb_function.disable = rockusb_disable;
+	f_rkusb->usb_function.strings = rkusb_strings;
+
+	status = usb_add_function(c, &f_rkusb->usb_function);
+	if (status) {
+		free(f_rkusb);
+		rockusb_func = f_rkusb;
+	}
+	return status;
+}
+
+void rockusb_dev_init(char *dev_type, int dev_index)
+{
+	struct f_rockusb *f_rkusb = get_rkusb();
+
+	f_rkusb->dev_type = dev_type;
+	f_rkusb->dev_index = dev_index;
+}
+
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_rockusb, rockusb_add);
+
+static int rockusb_tx_write(const char *buffer, unsigned int buffer_size)
+{
+	struct usb_request *in_req = rockusb_func->in_req;
+	int ret;
+
+	memcpy(in_req->buf, buffer, buffer_size);
+	in_req->length = buffer_size;
+	usb_ep_dequeue(rockusb_func->in_ep, in_req);
+	ret = usb_ep_queue(rockusb_func->in_ep, in_req, 0);
+	if (ret)
+		printf("Error %d on queue\n", ret);
+	return 0;
+}
+
+static int rockusb_tx_write_str(const char *buffer)
+{
+	return rockusb_tx_write(buffer, strlen(buffer));
+}
+
+#ifdef DEBUG
+static void printcbw(char *buf)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+
+	memcpy((char *)cbw, buf, USB_BULK_CB_WRAP_LEN);
+
+	debug("cbw: signature:%x\n", cbw->signature);
+	debug("cbw: tag=%x\n", cbw->tag);
+	debug("cbw: data_transfer_length=%d\n", cbw->data_transfer_length);
+	debug("cbw: flags=%x\n", cbw->flags);
+	debug("cbw: lun=%d\n", cbw->lun);
+	debug("cbw: length=%d\n", cbw->length);
+	debug("cbw: ucOperCode=%x\n", cbw->CDB[0]);
+	debug("cbw: ucReserved=%x\n", cbw->CDB[1]);
+	debug("cbw: dwAddress:%x %x %x %x\n", cbw->CDB[5], cbw->CDB[4],
+	      cbw->CDB[3], cbw->CDB[2]);
+	debug("cbw: ucReserved2=%x\n", cbw->CDB[6]);
+	debug("cbw: uslength:%x %x\n", cbw->CDB[8], cbw->CDB[7]);
+}
+
+static void printcsw(char *buf)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw,
+				 sizeof(struct bulk_cs_wrap));
+	memcpy((char *)csw, buf, USB_BULK_CS_WRAP_LEN);
+	debug("csw: signature:%x\n", csw->signature);
+	debug("csw: tag:%x\n", csw->tag);
+	debug("csw: residue:%x\n", csw->residue);
+	debug("csw: status:%x\n", csw->status);
+}
+#endif
+
+static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw,
+				 sizeof(struct bulk_cs_wrap));
+	csw->signature = cpu_to_le32(USB_BULK_CS_SIG);
+	csw->tag = tag;
+	csw->residue = cpu_to_be32(residue);
+	csw->status = status;
+#ifdef DEBUG
+	printcsw((char *)&csw);
+#endif
+	return rockusb_tx_write((char *)csw, size);
+}
+
+static unsigned int rx_bytes_expected(struct usb_ep *ep)
+{
+	struct f_rockusb *f_rkusb = get_rkusb();
+	int rx_remain = f_rkusb->dl_size - f_rkusb->dl_bytes;
+	unsigned int rem;
+	unsigned int maxpacket = ep->maxpacket;
+
+	if (rx_remain <= 0)
+		return 0;
+	else if (rx_remain > EP_BUFFER_SIZE)
+		return EP_BUFFER_SIZE;
+
+	rem = rx_remain % maxpacket;
+	if (rem > 0)
+		rx_remain = rx_remain + (maxpacket - rem);
+
+	return rx_remain;
+}
+
+/* usb_request complete call back to handle down load image */
+static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
+{
+	struct f_rockusb *f_rkusb = get_rkusb();
+	unsigned int transfer_size = 0;
+	const unsigned char *buffer = req->buf;
+	unsigned int buffer_size = req->actual;
+
+	transfer_size = f_rkusb->dl_size - f_rkusb->dl_bytes;
+	if (!f_rkusb->desc) {
+		char *type = f_rkusb->dev_type;
+		int index = f_rkusb->dev_index;
+
+		f_rkusb->desc = blk_get_dev(type, index);
+		if (!f_rkusb->desc ||
+		    f_rkusb->desc->type == DEV_TYPE_UNKNOWN) {
+			puts("invalid mmc device\n");
+			rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+					     USB_BULK_CS_WRAP_LEN);
+			return;
+		}
+	}
+
+	if (req->status != 0) {
+		printf("Bad status: %d\n", req->status);
+		rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+				     USB_BULK_CS_WRAP_LEN);
+		return;
+	}
+
+	if (buffer_size < transfer_size)
+		transfer_size = buffer_size;
+
+	memcpy((void *)f_rkusb->buf, buffer, transfer_size);
+	f_rkusb->dl_bytes += transfer_size;
+	int blks = 0, blkcnt = transfer_size  / 512;
+
+	debug("dl %x bytes, %x blks, write lba %x, dl_size:%x, dl_bytes:%x, ",
+	      transfer_size, blkcnt, f_rkusb->lba, f_rkusb->dl_size,
+	      f_rkusb->dl_bytes);
+	blks = blk_dwrite(f_rkusb->desc, f_rkusb->lba, blkcnt, f_rkusb->buf);
+	if (blks != blkcnt) {
+		printf("failed writing to device %s: %d\n", f_rkusb->dev_type,
+		       f_rkusb->dev_index);
+		rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL,
+				     USB_BULK_CS_WRAP_LEN);
+		return;
+	}
+	f_rkusb->lba += blkcnt;
+
+	/* Check if transfer is done */
+	if (f_rkusb->dl_bytes >= f_rkusb->dl_size) {
+		req->complete = rx_handler_command;
+		req->length = EP_BUFFER_SIZE;
+		f_rkusb->buf = f_rkusb->buf_head;
+		printf("transfer 0x%x bytes done\n", f_rkusb->dl_size);
+		f_rkusb->dl_size = 0;
+		rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD,
+				     USB_BULK_CS_WRAP_LEN);
+	} else {
+		req->length = rx_bytes_expected(ep);
+		if (f_rkusb->buf == f_rkusb->buf_head)
+			f_rkusb->buf = f_rkusb->buf_head + EP_BUFFER_SIZE;
+		else
+			f_rkusb->buf = f_rkusb->buf_head;
+
+		debug("remain %x bytes, %x sectors\n", req->length,
+		      req->length / 512);
+	}
+
+	req->actual = 0;
+	usb_ep_queue(ep, req, 0);
+}
+
+static void cb_test_unit_ready(struct usb_ep *ep, struct usb_request *req)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+
+	memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+
+	rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+			     CSW_GOOD, USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_read_storage_id(struct usb_ep *ep, struct usb_request *req)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+	char emmc_id[] = "EMMC ";
+
+	printf("read storage id\n");
+	memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+	rockusb_tx_write_str(emmc_id);
+	rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+			     USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_write_lba(struct usb_ep *ep, struct usb_request *req)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+	struct f_rockusb *f_rkusb = get_rkusb();
+	int sector_count;
+
+	memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+	sector_count = (int)get_unaligned_be16(&cbw->CDB[7]);
+	f_rkusb->lba = get_unaligned_be32(&cbw->CDB[2]);
+	f_rkusb->dl_size = sector_count * 512;
+	f_rkusb->dl_bytes = 0;
+	f_rkusb->tag = cbw->tag;
+	debug("require write %x bytes, %x sectors to lba %x\n",
+	      f_rkusb->dl_size, sector_count, f_rkusb->lba);
+
+	if (f_rkusb->dl_size == 0)  {
+		rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length,
+				     CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+	} else {
+		req->complete = rx_handler_dl_image;
+		req->length = rx_bytes_expected(ep);
+	}
+}
+
+void __weak rkusb_set_reboot_flag(int flag)
+{
+	struct f_rockusb *f_rkusb = get_rkusb();
+
+	printf("rockkusb set reboot flag: %d\n", f_rkusb->reboot_flag);
+}
+
+static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
+{
+	struct f_rockusb *f_rkusb = get_rkusb();
+
+	rkusb_set_reboot_flag(f_rkusb->reboot_flag);
+	do_reset(NULL, 0, 0, NULL);
+}
+
+static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+	struct f_rockusb *f_rkusb = get_rkusb();
+
+	f_rkusb->reboot_flag = 0;
+	memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+	f_rkusb->reboot_flag = cbw->CDB[1];
+	rockusb_func->in_req->complete = compl_do_reset;
+	rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD,
+			     USB_BULK_CS_WRAP_LEN);
+}
+
+static void cb_not_support(struct usb_ep *ep, struct usb_request *req)
+{
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+
+	memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+	printf("Rockusb command %x not support yet\n", cbw->CDB[0]);
+	rockusb_tx_write_csw(cbw->tag, 0, CSW_FAIL, USB_BULK_CS_WRAP_LEN);
+}
+
+static const struct cmd_dispatch_info cmd_dispatch_info[] = {
+	{
+		.cmd = K_FW_TEST_UNIT_READY,
+		.cb = cb_test_unit_ready,
+	},
+	{
+		.cmd = K_FW_READ_FLASH_ID,
+		.cb = cb_read_storage_id,
+	},
+	{
+		.cmd = K_FW_SET_DEVICE_ID,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_TEST_BAD_BLOCK,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_READ_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_WRITE_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_ERASE_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_WRITE_SPARE,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_READ_SPARE,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_ERASE_10_FORCE,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_GET_VERSION,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_LBA_READ_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_LBA_WRITE_10,
+		.cb = cb_write_lba,
+	},
+	{
+		.cmd = K_FW_ERASE_SYS_DISK,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SDRAM_READ_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SDRAM_WRITE_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SDRAM_EXECUTE,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_READ_FLASH_INFO,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_GET_CHIP_VER,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_LOW_FORMAT,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SET_RESET_FLAG,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SPI_READ_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SPI_WRITE_10,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_SESSION,
+		.cb = cb_not_support,
+	},
+	{
+		.cmd = K_FW_RESET,
+		.cb = cb_reboot,
+	},
+};
+
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
+{
+	void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
+
+	ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw,
+				 sizeof(struct fsg_bulk_cb_wrap));
+	char *cmdbuf = req->buf;
+	int i;
+
+	if (req->status || req->length == 0)
+		return;
+
+	memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN);
+#ifdef DEBUG
+	printcbw(req->buf);
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
+		if (cmd_dispatch_info[i].cmd == cbw->CDB[0]) {
+			func_cb = cmd_dispatch_info[i].cb;
+			break;
+		}
+	}
+
+	if (!func_cb) {
+		printf("unknown command: %s\n", (char *)req->buf);
+		rockusb_tx_write_str("FAILunknown command");
+	} else {
+		if (req->actual < req->length) {
+			u8 *buf = (u8 *)req->buf;
+
+			buf[req->actual] = 0;
+			func_cb(ep, req);
+		} else {
+			puts("buffer overflow\n");
+			rockusb_tx_write_str("FAILbuffer overflow");
+		}
+	}
+
+	*cmdbuf = '\0';
+	req->actual = 0;
+	usb_ep_queue(ep, req, 0);
+}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index c79f866..90b2f78 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -186,6 +186,12 @@
 	---help---
 	  Enables support for generic EHCI controller.
 
+config USB_EHCI_FSL
+	bool  "Support for FSL on-chip EHCI USB controller"
+	default n
+	select  CONFIG_EHCI_HCD_INIT_AFTER_RESET
+	---help---
+	  Enables support for the on-chip EHCI controller on FSL chips.
 endif # USB_EHCI_HCD
 
 config USB_OHCI_HCD
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 62c431b..17d1fae 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -106,14 +106,14 @@
 	ehci = (struct usb_ehci *)priv->hcd_base;
 	hccr = (struct ehci_hccr *)(&ehci->caplength);
 	hcor = (struct ehci_hcor *)
-		((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+		((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
 	if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
 		return -ENXIO;
 
-	debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
-	      (u32)hccr, (u32)hcor,
-	      (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
+	      (void *)hccr, (void *)hcor,
+	      HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
 	return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
 }
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 7ee44ea..aedc24b 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -312,13 +312,16 @@
 {
 	struct musb_host_data *host = dev_get_priv(dev);
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+	void *base = dev_read_addr_ptr(dev);
 	int ret;
 
+	if (!base)
+		return -EINVAL;
+
 	priv->desc_before_addr = true;
 
 #ifdef CONFIG_USB_MUSB_HOST
-	host->host = musb_init_controller(&musb_plat, NULL,
-					  (void *)SUNXI_USB0_BASE);
+	host->host = musb_init_controller(&musb_plat, NULL, base);
 	if (!host->host)
 		return -EIO;
 
@@ -326,7 +329,7 @@
 	if (!ret)
 		printf("Allwinner mUSB OTG (Host)\n");
 #else
-	ret = musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
+	ret = musb_register(&musb_plat, NULL, base);
 	if (!ret)
 		printf("Allwinner mUSB OTG (Peripheral)\n");
 #endif
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 9d2e0ed..cd65192 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -842,8 +842,8 @@
 
 			get_name(dentptr, s_name);
 
-			if (strcmp(filename, s_name)
-			    && strcmp(filename, l_name)) {
+			if (strncasecmp(filename, s_name, sizeof(s_name)) &&
+			    strncasecmp(filename, l_name, sizeof(l_name))) {
 				debug("Mismatch: |%s|%s|\n",
 					s_name, l_name);
 				dentptr++;
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index b1b6725..25e6c1f 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -571,7 +571,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	25
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 3cf2f09..dbdf3dc 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -10,7 +10,6 @@
 #define __MIGO_R_H
 
 #define CONFIG_CPU_SH7722	1
-#define CONFIG_MIGO_R		1
 
 #define CONFIG_DISPLAY_BOARDINFO
 #undef  CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 17ae6cf..1863bec 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -270,7 +270,6 @@
 #define CONFIG_LOADADDR		1000000
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
 #define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
 #define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 8e71fdf..6b9f366 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -437,7 +437,6 @@
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index dd3cd6e..2354dc8 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -641,7 +641,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 791c6ef..733e44f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -648,7 +648,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index fb79b6a..e96d3a0 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -531,7 +531,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ceb9daa..1231c1a 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -641,7 +641,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 43fcc6f..6fbac5f 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -534,7 +534,7 @@
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #define CONFIG_PCIE4		/* PCIE controller 4 */
-#define CONFIG_FSL_PCIE_RESET
+#define CONFIG_FSL_PCIE_RESET   /* pcie reset fix link width 2x-4x*/
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
@@ -578,13 +578,11 @@
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e1c57de..85bda94 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -522,7 +522,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 099e9e1..73e91bc 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -381,7 +381,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	50
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index ecf7f64..b63c38c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -542,7 +542,6 @@
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	50
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index c09769d..4c2a2bd 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -11,7 +11,6 @@
 #define __AP325RXA_H
 
 #define CONFIG_CPU_SH7723	1
-#define CONFIG_AP325RXA	1
 
 #define CONFIG_DISPLAY_BOARDINFO
 #undef  CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index 717ec80..37aaec3 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -10,7 +10,6 @@
 #define __AP_SH4A_4A_H
 
 #define CONFIG_CPU_SH7734	1
-#define CONFIG_AP_SH4A_4A	1
 #define CONFIG_400MHZ_MODE	1
 
 #define CONFIG_SYS_TEXT_BASE 0x8BFC0000
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
index 36d74f3..d2f4c44 100644
--- a/include/configs/aspenite.h
+++ b/include/configs/aspenite.h
@@ -16,7 +16,6 @@
 #define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
 #define CONFIG_ARMADA100		1	/* SOC Family Name */
 #define CONFIG_ARMADA168		1	/* SOC Used on this Board */
-#define CONFIG_MACH_ASPENITE			/* Machine type */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 
 /*
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 60068d1..7686592 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -21,7 +21,6 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_MACH_DAVINCI_CALIMAIN
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index de9bc53..0e9dae6 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -453,7 +453,6 @@
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 942fbe2..e413b51 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -316,7 +316,6 @@
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
index 1802a6e..72386a6 100644
--- a/include/configs/dockstar.h
+++ b/include/configs/dockstar.h
@@ -17,7 +17,6 @@
  */
 #define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
 #define CONFIG_KW88F6281	1	/* SOC Name */
-#define CONFIG_MACH_DOCKSTAR	/* Machine type */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 
 /*
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 8cb3efc..c6fb59f 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -23,7 +23,6 @@
  */
 
 #define CONFIG_CPU_SH7724	1
-#define CONFIG_ECOVEC		1
 
 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 2b7a5d7..b77cfc5 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -35,7 +35,6 @@
 #define CONFIG_MARVELL		1
 #define CONFIG_FEROCEON		1	/* CPU Core subversion */
 #define CONFIG_88F5182		1	/* SOC Name */
-#define CONFIG_MACH_EDMINIV2	1	/* Machine type */
 
 #include <asm/arch/orion5x.h>
 /*
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 628406a..a5ac8cb 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -11,7 +11,6 @@
 #define __ESPT_H
 
 #define CONFIG_CPU_SH7763	1
-#define CONFIG_ESPT	1
 #define __LITTLE_ENDIAN		1
 
 #define CONFIG_ENV_OVERWRITE    1
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
index 16e55b0..0dc8ed1 100644
--- a/include/configs/goflexhome.h
+++ b/include/configs/goflexhome.h
@@ -20,7 +20,6 @@
  */
 #define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
 #define CONFIG_KW88F6281	1	/* SOC Name */
-#define CONFIG_MACH_GOFLEXHOME		/* Machine type */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 
 /*
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index b13c6c9..dcb2a69 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -14,7 +14,6 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
-#define CONFIG_MACH_GURUPLUG	/* Machine type */
 
 /*
  * Standard filesystems
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 277f8be..ed58d1e 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -26,7 +26,6 @@
 #define CONFIG_MARVELL
 #define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
 #define CONFIG_KW88F6281		/* SOC Name */
-#define CONFIG_MACH_KM_KIRKWOOD		/* Machine type */
 
 #define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD
 
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 6aa2b9d..a0c932a 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -296,7 +296,6 @@
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
 /* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index af5f37c..bf4262a 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -107,17 +107,6 @@
 #define CONFIG_SF_DEFAULT_BUS        1
 #define CONFIG_SF_DEFAULT_CS         0
 
-/*
-* USB
-*/
-/* EHCI Support - disbaled by default */
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
 /*  MMC  */
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 6669f2f..d088e83 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -394,17 +394,6 @@
 #endif
 
 /*
- * USB
- */
-/* EHCI Support - disbaled by default */
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
-/*
  * Video
  */
 #ifdef CONFIG_VIDEO_FSL_DCU_FB
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 3db7ef1..15d6638 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -24,26 +24,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
 
-/*
- * USB
- */
-
-/*
- * EHCI Support - disbaled by default as
- * there is no signal coming out of soc on
- * this board for this controller. However,
- * the silicon still has this controller,
- * and anyone can use this controller by
- * taking signals out on their board.
- */
-
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
 
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e208f7d..5c2ad69 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -155,10 +155,6 @@
 #endif
 #endif
 
-#ifndef SPL_NO_QBMAN
-#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
-#endif
-
 /* FMan ucode */
 #ifndef SPL_NO_FMAN
 #define CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 6587296..e684884 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -7,6 +7,19 @@
 #ifndef __LS1088_COMMON_H
 #define __LS1088_COMMON_H
 
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_BOARDINFO
+#define SPL_NO_QIXIS
+#define SPL_NO_PCI
+#define SPL_NO_ENV
+#define SPL_NO_RTC
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#define SPL_NO_QSPI
+#define SPL_NO_IFC
+#undef CONFIG_DISPLAY_CPUINFO
+#endif
 
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
@@ -74,8 +87,10 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
 /* IFC */
 #define CONFIG_FSL_IFC
+#endif
 
 /*
  * During booting, IFC is mapped at the region of 0x30000000.
@@ -172,6 +187,7 @@
 
 /* #define CONFIG_DISPLAY_CPUINFO */
 
+#ifndef SPL_NO_ENV
 /* Allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
@@ -211,6 +227,7 @@
 				" cp.b $kernel_start $kernel_load" \
 				" $kernel_size && bootm $kernel_load"
 #endif
+#endif
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
@@ -219,7 +236,9 @@
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
+#ifndef SPL_NO_ENV
 #define CONFIG_CMDLINE_EDITING		1
+#endif
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		64	/* max command args */
 
@@ -235,7 +254,20 @@
 
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
 #define CONFIG_SYS_SPL_MALLOC_START    0x80200000
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN         0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
 #endif
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 1438bec..3c6c666 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -9,7 +9,9 @@
 
 #include "ls1088a_common.h"
 
+#ifndef SPL_NO_BOARDINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
+#endif
 
 #define CONFIG_MISC_INIT_R
 
@@ -29,7 +31,9 @@
 #endif
 
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_QIXIS_I2C_ACCESS
+#endif
 #define SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
 #endif
@@ -97,7 +101,11 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
 #endif
 #endif
+
+#ifndef SPL_NO_IFC
 #define CONFIG_NAND_FSL_IFC
+#endif
+
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 
@@ -139,7 +147,10 @@
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 
+#ifndef SPL_NO_QIXIS
 #define CONFIG_FSL_QIXIS
+#endif
+
 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		2
 #define QIXIS_QMAP_MASK			0xe0
@@ -223,6 +234,8 @@
 #define I2C_RETIMER_ADDR		0x18
 #define I2C_MUX_CH_DEFAULT		0x8
 #define I2C_MUX_CH5			0xD
+
+#ifndef SPL_NO_RTC
 /*
 * RTC configuration
 */
@@ -230,6 +243,7 @@
 #define CONFIG_RTC_PCF8563 1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 #define CONFIG_CMD_DATE
+#endif
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
@@ -240,12 +254,14 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
 
+#ifndef SPL_NO_QSPI
 /* QSPI device */
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_QSPI
 #define FSL_QSPI_FLASH_SIZE		(1 << 26)
 #define FSL_QSPI_FLASH_NUM		2
 #endif
+#endif
 
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MEMTEST
@@ -260,6 +276,7 @@
 
 #define CONFIG_FSL_MEMAC
 
+#ifndef SPL_NO_ENV
 /* Initial environment variables */
 #if defined(CONFIG_QSPI_BOOT)
 #define MC_INIT_CMD				\
@@ -408,6 +425,7 @@
 #define CONFIG_ETHPRIME		"DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE
 #endif
+#endif
 
 /*  MMC  */
 #ifdef CONFIG_MMC
@@ -415,6 +433,7 @@
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
+#ifndef SPL_NO_ENV
 #undef CONFIG_CMDLINE_EDITING
 #include <config_distro_defaults.h>
 
@@ -423,6 +442,7 @@
 	func(SCSI, scsi, 0) \
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
+#endif
 
 #include <asm/fsl_secure_boot.h>
 
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
index 14b0492..a6e1726 100644
--- a/include/configs/mpr2.h
+++ b/include/configs/mpr2.h
@@ -18,7 +18,6 @@
 
 /* CPU and platform */
 #define CONFIG_CPU_SH7720	1
-#define CONFIG_MPR2		1
 
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
index 7a9aa82..cade328 100644
--- a/include/configs/ms7720se.h
+++ b/include/configs/ms7720se.h
@@ -10,7 +10,6 @@
 #define __MS7720SE_H
 
 #define CONFIG_CPU_SH7720	1
-#define CONFIG_MS7720SE		1
 
 #define CONFIG_BOOTFILE		"/boot/zImage"
 #define CONFIG_LOADADDR		0x8E000000
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 431d747..3db6c24 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -10,7 +10,6 @@
 #define __MS7722SE_H
 
 #define CONFIG_CPU_SH7722	1
-#define CONFIG_MS7722SE		1
 
 #define CONFIG_DISPLAY_BOARDINFO
 #undef  CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index e942758..1cd7ae0 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -12,7 +12,6 @@
 #define CONFIG_CPU_SH7750	1
 /* #define CONFIG_CPU_SH7751	1 */
 /* #define CONFIG_CPU_TYPE_R	1 */
-#define CONFIG_MS7750SE		1
 #define __LITTLE_ENDIAN__	1
 
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index af16b94..9f2db09 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -44,9 +44,6 @@
 /*
  * Other required minimal configurations
  */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
 #define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
 #define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
 #define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
@@ -107,4 +104,24 @@
 
 #define CONFIG_SUPPORT_VFAT
 
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(SCSI, scsi, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"scriptaddr=0x4d00000\0"	\
+	"pxefile_addr_r=0x4e00000\0"	\
+	"fdt_addr_r=0x4f00000\0"	\
+	"kernel_addr_r=0x5000000\0"	\
+	"ramdisk_addr_r=0x8000000\0"	\
+	BOOTENV
+
 #endif /* _CONFIG_MVEBU_ARMADA_37XX_H */
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
index 1bea7f5..0165d9c 100644
--- a/include/configs/openrd.h
+++ b/include/configs/openrd.h
@@ -19,7 +19,6 @@
  */
 #define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
 #define CONFIG_KW88F6281	1	/* SOC Name */
-#define CONFIG_MACH_OPENRD_BASE	/* Machine type */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
 
 /*
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index 1fef8b5..9258a3b 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -10,7 +10,6 @@
 #define __R0P7734_H
 
 #define CONFIG_CPU_SH7734	1
-#define CONFIG_R0P7734		1
 #define CONFIG_400MHZ_MODE	1
 
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index cdbe96e..6ca66b8 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -2,8 +2,6 @@
 #define __CONFIG_H
 
 #define CONFIG_CPU_SH7751	1
-#define CONFIG_CPU_SH_TYPE_R	1
-#define CONFIG_R2DPLUS		1
 #define __LITTLE_ENDIAN__	1
 
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
index 215767c..a5aa11c 100644
--- a/include/configs/rsk7203.h
+++ b/include/configs/rsk7203.h
@@ -11,7 +11,6 @@
 #define __RSK7203_H
 
 #define CONFIG_CPU_SH7203	1
-#define CONFIG_RSK7203	1
 
 #define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
 
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index 11b8e0a..2ecc328 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -12,7 +12,6 @@
 #define __RSK7264_H
 
 #define CONFIG_CPU_SH7264	1
-#define CONFIG_RSK7264		1
 
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
index 709563d..88d50ef 100644
--- a/include/configs/rsk7269.h
+++ b/include/configs/rsk7269.h
@@ -11,7 +11,6 @@
 #define __RSK7269_H
 
 #define CONFIG_CPU_SH7269	1
-#define CONFIG_RSK7269		1
 
 #define CONFIG_DISPLAY_BOARDINFO
 
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 86835e7..1aa1671 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -15,7 +15,6 @@
 #define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
 #define CONFIG_S5P		1	/* which is in a S5P Family */
 #define CONFIG_S5PC110		1	/* which is in a S5PC110 */
-#define CONFIG_MACH_GONI	1	/* working with Goni */
 
 #include <linux/sizes.h>
 #include <asm/arch/cpu.h>		/* get chip and board defs */
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index 13d22a2..2f81cc5 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -10,7 +10,6 @@
 #define __SH7752EVB_H
 
 #define CONFIG_CPU_SH7752	1
-#define CONFIG_SH7752EVB	1
 
 #define CONFIG_SYS_TEXT_BASE	0x5ff80000
 
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 66f8c7a..bcb85a6 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -10,7 +10,6 @@
 #define __SH7753EVB_H
 
 #define CONFIG_CPU_SH7753	1
-#define CONFIG_SH7753EVB	1
 
 #define CONFIG_SYS_TEXT_BASE	0x5ff80000
 
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 43de7e5..bee1a1d 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -10,7 +10,6 @@
 #define __SH7757LCR_H
 
 #define CONFIG_CPU_SH7757	1
-#define CONFIG_SH7757LCR	1
 #define CONFIG_SH7757LCR_DDR_ECC	1
 
 #define CONFIG_SYS_TEXT_BASE	0x8ef80000
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 61fb64e..0598b25 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -11,7 +11,6 @@
 #define __SH7763RDP_H
 
 #define CONFIG_CPU_SH7763	1
-#define CONFIG_SH7763RDP	1
 #define __LITTLE_ENDIAN		1
 
 #define CONFIG_ENV_OVERWRITE    1
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index f77e47a..c90cbe1 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -10,7 +10,6 @@
 #define __SH7785LCR_H
 
 #define CONFIG_CPU_SH7785	1
-#define CONFIG_SH7785LCR	1
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"bootdevice=0:1\0"						\
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 9acd4d3..ebed1d5 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -14,7 +14,6 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
-#define CONFIG_MACH_SHEEVAPLUG	/* Machine type */
 
 /*
  * Commands configuration
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index 024d75a..1ad3698 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -24,7 +24,6 @@
  * Configuration of the external SDRAM memory
  */
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_RAM_SIZE		(8 << 20)
 #define CONFIG_SYS_RAM_CS		1
 #define CONFIG_SYS_RAM_FREQ_DIV		2
 #define CONFIG_SYS_RAM_BASE		0xD0000000
@@ -42,9 +41,7 @@
 #define CONFIG_RED_LED			110
 #define CONFIG_GREEN_LED		109
 
-#define CONFIG_STM32_GPIO
 #define CONFIG_STM32_FLASH
-#define CONFIG_STM32_SERIAL
 
 #define CONFIG_STM32_HSE_HZ		8000000
 
diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h
new file mode 100644
index 0000000..1409999
--- /dev/null
+++ b/include/configs/stm32f469-discovery.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_STM32F4DISCOVERY
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
+#define CONFIG_SYS_TEXT_BASE		0x08000000
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_RAM_FREQ_DIV		2
+#define CONFIG_SYS_RAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_LOAD_ADDR		0x00400000
+#define CONFIG_LOADADDR			0x00400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_STM32_HSE_HZ		8000000
+#define CONFIG_SYS_CLK_FREQ		180000000 /* 180 MHz */
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define CONFIG_BOOTCOMMAND						\
+	"run boot_sd"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 12cbe9b..5ab06f6 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -215,8 +215,6 @@
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_NR_DRAM_BANKS		3
-/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
-#define CONFIG_SYS_MEM_TOP_HIDE		64
 
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)
 
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
index c2b911f..ab91d2b 100644
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -30,8 +30,10 @@
 /* Timing = value +1 cycles */
 #define TMRD_1		(1 - 1)
 #define TMRD_2		(2 - 1)
+#define TMRD_3		(3 - 1)
 #define TXSR_1		(1 - 1)
 #define TXSR_6		(6 - 1)
+#define TXSR_7		(7 - 1)
 #define TRAS_1		(1 - 1)
 #define TRAS_4		(4 - 1)
 #define TRC_6		(6 - 1)
diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h
new file mode 100644
index 0000000..36448a5
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f4-rcc.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the STM32F4 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
+#define _DT_BINDINGS_MFD_STM32F4_RCC_H
+
+/* AHB1 */
+#define STM32F4_RCC_AHB1_GPIOA	0
+#define STM32F4_RCC_AHB1_GPIOB	1
+#define STM32F4_RCC_AHB1_GPIOC	2
+#define STM32F4_RCC_AHB1_GPIOD	3
+#define STM32F4_RCC_AHB1_GPIOE	4
+#define STM32F4_RCC_AHB1_GPIOF	5
+#define STM32F4_RCC_AHB1_GPIOG	6
+#define STM32F4_RCC_AHB1_GPIOH	7
+#define STM32F4_RCC_AHB1_GPIOI	8
+#define STM32F4_RCC_AHB1_GPIOJ	9
+#define STM32F4_RCC_AHB1_GPIOK	10
+#define STM32F4_RCC_AHB1_CRC	12
+#define STM32F4_RCC_AHB1_BKPSRAM	18
+#define STM32F4_RCC_AHB1_CCMDATARAM	20
+#define STM32F4_RCC_AHB1_DMA1	21
+#define STM32F4_RCC_AHB1_DMA2	22
+#define STM32F4_RCC_AHB1_DMA2D	23
+#define STM32F4_RCC_AHB1_ETHMAC	25
+#define STM32F4_RCC_AHB1_ETHMACTX	26
+#define STM32F4_RCC_AHB1_ETHMACRX	27
+#define STM32F4_RCC_AHB1_ETHMACPTP	28
+#define STM32F4_RCC_AHB1_OTGHS		29
+#define STM32F4_RCC_AHB1_OTGHSULPI	30
+
+#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
+
+/* AHB2 */
+#define STM32F4_RCC_AHB2_DCMI	0
+#define STM32F4_RCC_AHB2_CRYP	4
+#define STM32F4_RCC_AHB2_HASH	5
+#define STM32F4_RCC_AHB2_RNG	6
+#define STM32F4_RCC_AHB2_OTGFS	7
+
+#define STM32F4_AHB2_RESET(bit)	(STM32F4_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F4_AHB2_CLOCK(bit)	(STM32F4_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F4_RCC_AHB3_FMC	0
+#define STM32F4_RCC_AHB3_QSPI	1
+
+#define STM32F4_AHB3_RESET(bit)	(STM32F4_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F4_AHB3_CLOCK(bit)	(STM32F4_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F4_RCC_APB1_TIM2	0
+#define STM32F4_RCC_APB1_TIM3	1
+#define STM32F4_RCC_APB1_TIM4	2
+#define STM32F4_RCC_APB1_TIM5	3
+#define STM32F4_RCC_APB1_TIM6	4
+#define STM32F4_RCC_APB1_TIM7	5
+#define STM32F4_RCC_APB1_TIM12	6
+#define STM32F4_RCC_APB1_TIM13	7
+#define STM32F4_RCC_APB1_TIM14	8
+#define STM32F4_RCC_APB1_WWDG	11
+#define STM32F4_RCC_APB1_SPI2	14
+#define STM32F4_RCC_APB1_SPI3	15
+#define STM32F4_RCC_APB1_UART2	17
+#define STM32F4_RCC_APB1_UART3	18
+#define STM32F4_RCC_APB1_UART4	19
+#define STM32F4_RCC_APB1_UART5	20
+#define STM32F4_RCC_APB1_I2C1	21
+#define STM32F4_RCC_APB1_I2C2	22
+#define STM32F4_RCC_APB1_I2C3	23
+#define STM32F4_RCC_APB1_CAN1	25
+#define STM32F4_RCC_APB1_CAN2	26
+#define STM32F4_RCC_APB1_PWR	28
+#define STM32F4_RCC_APB1_DAC	29
+#define STM32F4_RCC_APB1_UART7	30
+#define STM32F4_RCC_APB1_UART8	31
+
+#define STM32F4_APB1_RESET(bit)	(STM32F4_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F4_APB1_CLOCK(bit)	(STM32F4_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F4_RCC_APB2_TIM1	0
+#define STM32F4_RCC_APB2_TIM8	1
+#define STM32F4_RCC_APB2_USART1	4
+#define STM32F4_RCC_APB2_USART6	5
+#define STM32F4_RCC_APB2_ADC1	8
+#define STM32F4_RCC_APB2_ADC2	9
+#define STM32F4_RCC_APB2_ADC3	10
+#define STM32F4_RCC_APB2_SDIO	11
+#define STM32F4_RCC_APB2_SPI1	12
+#define STM32F4_RCC_APB2_SPI4	13
+#define STM32F4_RCC_APB2_SYSCFG	14
+#define STM32F4_RCC_APB2_TIM9	16
+#define STM32F4_RCC_APB2_TIM10	17
+#define STM32F4_RCC_APB2_TIM11	18
+#define STM32F4_RCC_APB2_SPI5	20
+#define STM32F4_RCC_APB2_SPI6	21
+#define STM32F4_RCC_APB2_SAI1	22
+#define STM32F4_RCC_APB2_LTDC	26
+#define STM32F4_RCC_APB2_DSI	27
+
+#define STM32F4_APB2_RESET(bit)	(STM32F4_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F4_APB2_CLOCK(bit)	(STM32F4_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
new file mode 100644
index 0000000..b8dfe31
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -0,0 +1,30 @@
+#ifndef _DT_BINDINGS_STM32_PINFUNC_H
+#define _DT_BINDINGS_STM32_PINFUNC_H
+
+/*  define PIN modes */
+#define GPIO	0x0
+#define AF0	0x1
+#define AF1	0x2
+#define AF2	0x3
+#define AF3	0x4
+#define AF4	0x5
+#define AF5	0x6
+#define AF6	0x7
+#define AF7	0x8
+#define AF8	0x9
+#define AF9	0xa
+#define AF10	0xb
+#define AF11	0xc
+#define AF12	0xd
+#define AF13	0xe
+#define AF14	0xf
+#define AF15	0x10
+#define ANALOG	0x11
+
+/* define Pins number*/
+#define PIN_NO(port, line)	(((port) - 'A') * 0x10 + (line))
+
+#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
+
+#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
+
diff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h
index 6348c6a..549323f 100644
--- a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h
@@ -154,7 +154,6 @@
 #define STM32F746_PA15_FUNC_EVENTOUT 0xf10
 #define STM32F746_PA15_FUNC_ANALOG 0xf11
 
-
 #define STM32F746_PB0_FUNC_GPIO 0x1000
 #define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002
 #define STM32F746_PB0_FUNC_TIM3_CH3 0x1003
@@ -188,6 +187,9 @@
 #define STM32F746_PB3_FUNC_TIM2_CH2 0x1302
 #define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306
 #define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307
+
+#define STM32F769_PB3_FUNC_SDMMC2_D2 0x130b
+
 #define STM32F746_PB3_FUNC_EVENTOUT 0x1310
 #define STM32F746_PB3_FUNC_ANALOG 0x1311
 
@@ -197,6 +199,9 @@
 #define STM32F746_PB4_FUNC_SPI1_MISO 0x1406
 #define STM32F746_PB4_FUNC_SPI3_MISO 0x1407
 #define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408
+
+#define STM32F769_PB4_FUNC_SDMMC2_D3 0x140b
+
 #define STM32F746_PB4_FUNC_EVENTOUT 0x1410
 #define STM32F746_PB4_FUNC_ANALOG 0x1411
 
@@ -505,6 +510,9 @@
 #define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606
 #define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607
 #define STM32F746_PD6_FUNC_USART2_RX 0x3608
+
+#define STM32F769_PD6_FUNC_SDMMC2_CLK 0x360c
+
 #define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d
 #define STM32F746_PD6_FUNC_DCMI_D10 0x360e
 #define STM32F746_PD6_FUNC_LCD_B2 0x360f
@@ -514,6 +522,9 @@
 #define STM32F746_PD7_FUNC_GPIO 0x3700
 #define STM32F746_PD7_FUNC_USART2_CK 0x3708
 #define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709
+
+#define STM32F769_PD7_FUNC_SDMMC2_CMD 0x370c
+
 #define STM32F746_PD7_FUNC_FMC_NE1 0x370d
 #define STM32F746_PD7_FUNC_EVENTOUT 0x3710
 #define STM32F746_PD7_FUNC_ANALOG 0x3711
@@ -893,6 +904,9 @@
 #define STM32F746_PG9_FUNC_USART6_RX 0x6909
 #define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a
 #define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b
+
+#define STM32F769_PG9_FUNC_SDMMC2_D0 0x690c
+
 #define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d
 #define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e
 #define STM32F746_PG9_FUNC_EVENTOUT 0x6910
@@ -901,6 +915,9 @@
 #define STM32F746_PG10_FUNC_GPIO 0x6a00
 #define STM32F746_PG10_FUNC_LCD_G3 0x6a0a
 #define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b
+
+#define STM32F769_PG10_FUNC_SDMMC2_D1 0x6a0c
+
 #define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d
 #define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e
 #define STM32F746_PG10_FUNC_LCD_B2 0x6a0f
diff --git a/include/fsl_qbman.h b/include/fsl_qbman.h
new file mode 100644
index 0000000..06262ec
--- /dev/null
+++ b/include/fsl_qbman.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_QBMAN_H__
+#define __FSL_QBMAN_H__
+void fdt_fixup_qportals(void *blob);
+void fdt_fixup_bportals(void *blob);
+void inhibit_portals(void __iomem *addr, int max_portals,
+		     int arch_max_portals, int portal_cinh_size);
+void setup_qbman_portals(void);
+
+struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	u8	res0[0x200];
+#else
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal Dynamic Debug cfg */
+	} qcsp[32];
+#endif
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8 - 0x200];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fqd_bare;	/* FQD Extended Base Addr Register */
+	u32	fqd_bar;	/* FQD Base Addr Register */
+	u8	res1[0x8];
+	u32	fqd_ar;		/* FQD Attributes Register */
+	u8	res2[0xc];
+	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
+	u32	pfdr_bar;	/* PFDR Base Addr Register */
+	u8	res3[0x8];
+	u32	pfdr_ar;	/* PFDR Attributes Register */
+	u8	res4[0x4c];
+	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
+	u32	qcsp_bar;	/* QCSP Base Addr Register */
+	u8	res5[0x78];
+	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res6[4];
+	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
+	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
+	u8	res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
+	} qcsp[50];
+#endif
+};
+
+struct ccsr_bman {
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
+	u32	fbpr_bar;	/* FBPR Base Addr Register */
+	u8	res1[0x8];
+	u32	fbpr_ar;	/* FBPR Attributes Register */
+	u8	res2[0xf0];
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res7[0x2f4];
+};
+
+#endif /* __FSL_QBMAN_H__ */
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 87d2d95..04a09eb 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -38,6 +38,7 @@
 #define REPEAT_BYTE(x)	((~0ul / 0xff) * (x))
 
 #define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
+#define ALIGN_DOWN(x, a)	ALIGN((x) - ((a) - 1), (a))
 #define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
 #define PTR_ALIGN(p, a)		((typeof(p))ALIGN((unsigned long)(p), (a)))
 #define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a27dc4f..4e87d66 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -33,7 +33,6 @@
 CONFIG_AMCORE
 CONFIG_ANDES_PCU
 CONFIG_ANDES_PCU_BASE
-CONFIG_AP325RXA
 CONFIG_APBH_DMA
 CONFIG_APBH_DMA_BURST
 CONFIG_APBH_DMA_BURST8
@@ -41,7 +40,6 @@
 CONFIG_APER_1_BASE
 CONFIG_APER_SIZE
 CONFIG_APUS_FAST_EXCEPT
-CONFIG_AP_SH4A_4A
 CONFIG_ARCH_ADPAG101P
 CONFIG_ARCH_CPU_INIT
 CONFIG_ARCH_HAS_ILOG2_U32
@@ -333,7 +331,6 @@
 CONFIG_CPU_SH7763
 CONFIG_CPU_SH7780
 CONFIG_CPU_SH7785
-CONFIG_CPU_SH_TYPE_R
 CONFIG_CPU_TYPE_R
 CONFIG_CPU_VR41XX
 CONFIG_CQSPI_DECODER
@@ -504,7 +501,6 @@
 CONFIG_ECC_SRAM_ADDR_MASK
 CONFIG_ECC_SRAM_ADDR_SHIFT
 CONFIG_ECC_SRAM_REQ_BIT
-CONFIG_ECOVEC
 CONFIG_ECOVEC_ROMIMAGE_ADDR
 CONFIG_EDB9301
 CONFIG_EDB9302
@@ -596,7 +592,6 @@
 CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1
 CONFIG_ESDHC_HC_BLK_ADDR
 CONFIG_ESPRESSO7420
-CONFIG_ESPT
 CONFIG_ET1100_BASE
 CONFIG_ETH1ADDR
 CONFIG_ETH2ADDR
@@ -1294,18 +1289,8 @@
 CONFIG_MACB2_PHY
 CONFIG_MACB3_PHY
 CONFIG_MACB_SEARCH_PHY
-CONFIG_MACH_ASPENITE
-CONFIG_MACH_DAVINCI_CALIMAIN
 CONFIG_MACH_DAVINCI_DA850_EVM
-CONFIG_MACH_DOCKSTAR
-CONFIG_MACH_EDMINIV2
-CONFIG_MACH_GOFLEXHOME
-CONFIG_MACH_GONI
-CONFIG_MACH_GURUPLUG
-CONFIG_MACH_KM_KIRKWOOD
 CONFIG_MACH_OMAPL138_LCDK
-CONFIG_MACH_OPENRD_BASE
-CONFIG_MACH_SHEEVAPLUG
 CONFIG_MACH_SPECIFIC
 CONFIG_MACH_TYPE
 CONFIG_MACH_TYPE_COMPAT_REV
@@ -1343,7 +1328,6 @@
 CONFIG_MENUPROMPT
 CONFIG_MENU_SHOW
 CONFIG_MFG_ENV_SETTINGS
-CONFIG_MIGO_R
 CONFIG_MII
 CONFIG_MIIM_ADDRESS
 CONFIG_MII_DEFAULT_TSEC
@@ -1412,11 +1396,7 @@
 CONFIG_MPC8XXX_SPI
 CONFIG_MPC8xxx_DISABLE_BPTR
 CONFIG_MPLL_FREQ
-CONFIG_MPR2
 CONFIG_MP_CLK_FREQ
-CONFIG_MS7720SE
-CONFIG_MS7722SE
-CONFIG_MS7750SE
 CONFIG_MSHC_FREQ
 CONFIG_MTD_CONCAT
 CONFIG_MTD_DEVICE
@@ -1760,8 +1740,6 @@
 CONFIG_QSPI_QUAD_SUPPORT
 CONFIG_QSPI_SEL_GPIO
 CONFIG_QUOTA
-CONFIG_R0P7734
-CONFIG_R2DPLUS
 CONFIG_R7780MP
 CONFIG_R8A66597_BASE_ADDR
 CONFIG_R8A66597_ENDIAN
@@ -1835,9 +1813,6 @@
 CONFIG_ROM_STUBS
 CONFIG_ROOTFS_OFFSET
 CONFIG_ROOTPATH
-CONFIG_RSK7203
-CONFIG_RSK7264
-CONFIG_RSK7269
 CONFIG_RTC_DS1337
 CONFIG_RTC_DS1337_NOOSC
 CONFIG_RTC_DS1338
@@ -1934,16 +1909,11 @@
 CONFIG_SH4_PCI
 CONFIG_SH73A0
 CONFIG_SH7751_PCI
-CONFIG_SH7752EVB
-CONFIG_SH7753EVB
-CONFIG_SH7757LCR
 CONFIG_SH7757LCR_DDR_ECC
-CONFIG_SH7763RDP
 CONFIG_SH7780_PCI
 CONFIG_SH7780_PCI_BAR
 CONFIG_SH7780_PCI_LAR
 CONFIG_SH7780_PCI_LSR
-CONFIG_SH7785LCR
 CONFIG_SHARP_LM8V31
 CONFIG_SHARP_LQ035Q7DH06
 CONFIG_SHEEVA_88SV131
diff --git a/tools/mrvl_uart.sh b/tools/mrvl_uart.sh
new file mode 100755
index 0000000..6b04d7a
--- /dev/null
+++ b/tools/mrvl_uart.sh
@@ -0,0 +1,119 @@
+#!/bin/bash
+#
+######################################################
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0
+# https://spdx.org/licenses
+#
+# Author: Konstantin Porotchkin kostap@marvell.com
+#
+# Version 0.3
+#
+# UART recovery downloader for Armada SoCs
+#
+######################################################
+
+port=$1
+file=$2
+speed=$3
+
+pattern_repeat=1500
+default_baudrate=115200
+tmpfile=/tmp/xmodem.pattern
+tools=( dd stty sx minicom )
+
+case "$3" in
+    2)
+        fast_baudrate=230400
+        prefix="\xF2"
+        ;;
+    4)
+        fast_baudrate=460800
+        prefix="\xF4"
+        ;;
+    8)
+    	fast_baudrate=921600
+        prefix="\xF8"
+        ;;
+    *)
+    	fast_baudrate=$default_baudrate
+        prefix="\xBB"
+esac
+
+if [[ -z "$port" || -z "$file" ]]
+then
+    echo -e "\nMarvell recovery image downloader for Armada SoC family."
+    echo -e "Command syntax:"
+    echo -e "\t$(basename $0) <port> <file> [2|4|8]"
+    echo -e "\tport  - serial port the target board connected to"
+    echo -e "\tfile  - recovery boot image for target download"
+    echo -e "\t2|4|8 - times to increase the default serial port speed by"
+    echo -e "For example - load the image over ttyUSB0 @ 460800 baud:"
+    echo -e "$(basename $0) /dev/ttyUSB0 /tmp/flash-image.bin 4\n"
+    echo -e "=====WARNING====="
+    echo -e "- The speed-up option is not awailable in SoC families prior to A8K+"
+    echo -e "- This utility is not compatible with Armada 37xx SoC family\n"
+fi
+
+# Sanity checks
+if [ -c "$port" ]
+then
+   echo -e "Using device connected on serial port \"$port\""
+else
+   echo "Wrong serial port name!"
+   exit 1
+fi
+
+if [ -f "$file" ]
+then
+   echo -e "Loading flash image file \"$file\""
+else
+   echo "File $file does not exist!"
+   exit 1
+fi
+
+# Verify required tools installation
+for tool in ${tools[@]}
+do
+    toolname=`which $tool`
+    if [ -z "$toolname" ]
+    then
+        echo -e "Missing installation of \"$tool\" --> Exiting"
+        exit 1
+    fi
+done
+
+
+echo -e "Recovery will run at $fast_baudrate baud"
+echo -e "========================================"
+
+if [ -f "$tmpfile" ]
+then
+    rm -f $tmpfile
+fi
+
+# Send the escape sequence to target board using default debug port speed
+stty -F $port raw ignbrk time 5 $default_baudrate
+counter=0
+while [ $counter -lt $pattern_repeat ]; do
+    echo -n -e "$prefix\x11\x22\x33\x44\x55\x66\x77" >> $tmpfile
+    let counter=counter+1
+done
+
+echo -en "Press the \"Reset\" button on the target board and "
+echo -en "the \"Enter\" key on the host keyboard simultaneously"
+read
+dd if=$tmpfile of=$port &>/dev/null
+
+# Speed up the binary image transfer
+stty -F $port raw ignbrk time 5 $fast_baudrate
+sx -vv $file > $port < $port
+#sx-at91 $port $file
+
+# return the port to the default speed
+stty -F $port raw ignbrk time 5 $default_baudrate
+
+# Optional - fire up Minicom
+minicom -D $port
+