ARM: socfpga: use the pl310 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index e1ea8eb7..d887f02 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -59,20 +59,10 @@
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_enable(void)
{
- /* Disable the L2 cache */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x0, &pl310->pl310_tag_latency_ctrl);
- writel(0x10, &pl310->pl310_data_latency_ctrl);
-
- /* enable BRESP, instruction and data prefetch, full line of zeroes */
- setbits_le32(&pl310->pl310_aux_ctrl,
- L310_AUX_CTRL_DATA_PREFETCH_MASK |
- L310_AUX_CTRL_INST_PREFETCH_MASK |
- L310_SHARED_ATT_OVERRIDE_ENABLE);
+ struct udevice *dev;
- /* Enable the L2 cache */
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+ if (uclass_get_device(UCLASS_CACHE, 0, &dev))
+ pr_err("cache controller driver NOT found!\n");
}
void v7_outer_cache_disable(void)