tree 1c1e7f54e906684be5ffb570bedea526ae94afa9
parent 230ab8a0b35d0a1f9741bc06231a1b14924bed5d
author Lukas Auer <lukas.auer@aisec.fraunhofer.de> 1542882388 +0100
committer Andes <uboot@andestech.com> 1543211852 +0800

riscv: do not blindly modify the mstatus CSR

The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.

This instruction and others encode zero as an immediate.  RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>