tree 36e2b08b16920c55baaa66c614b61faa0b6cdf4e
parent bd8355b558d10be3e1e6daf595f9913cadd323e4
author Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> 1495702555 +0530
committer Michal Simek <michal.simek@xilinx.com> 1526023423 +0200

nand: zynq: Add support for 16-bit buswidth

This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>