commit 844493d7e99cb795f3e28130ee09ba7a6441162f
author Tom Rini <trini@konsulko.com> Sun Jan 26 16:17:47 2025 -0600
committer Tom Rini <trini@konsulko.com> Sun Jan 26 16:17:47 2025 -0600
tree e385efbf9c2a6fb8e0d075e9965c542a0e46e62d
parent 9c8af15f86b602d32dc0a1e638467c05b8792439

Squashed 'dts/upstream/' changes from 9b6ba2666d63..8531b4b4988c

8531b4b4988c Merge tag 'v6.13-rc7-dts-raw'
4dc7423c0128 Merge tag 'char-misc-6.13-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
a8433d3afa99 Merge tag 'soc-fixes-6.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
232823fd4930 Merge tag 'drm-fixes-2025-01-11' of https://gitlab.freedesktop.org/drm/kernel
ddf448187a99 Merge tag 'v6.13-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
326341ea6a5a Merge tag 'mediatek-drm-fixes-20250104' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes
c817d4d4421f Merge tag 'imx-fixes-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
be9c0a553356 Merge tag 'qcom-arm64-fixes-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
6d09f4fb518a arm64: dts: rockchip: add hevc power domain clock to rk3328
d1aa06cb62af dt-bindings: net: pse-pd: Fix unusual character in documentation
5ffa3ec7f447 arm64: dts: rockchip: Fix the SD card detection on NanoPi R6C/R6S
f4dbf6bea17a Merge tag 'v6.13-rc6-dts-raw'
136084c9071b Merge tag 'drm-misc-fixes-2025-01-02' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes
5f6a873e4c1f dt-bindings: display: mediatek: dp: Reference common DAI properties
6ff7bb898acb Merge tag 'v6.13-rc5-dts-raw'
f8bafac28c32 Merge tag 'sound-6.13-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
fc831d50be9f arm64: dts: qcom: sa8775p: fix the secure device bootup issue
029bcca18358 Merge tag 'v6.13-rc4-dts-raw'
f20911601a36 Merge tag 'devicetree-fixes-for-6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
8f7fab85f2a7 Merge tag 'soc-fixes-6.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
32d1c97c87fb Merge tag 'arm-soc/for-6.13/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
691b34dd7d9f dt-bindings: display: adi,adv7533: Drop single lane support
62da87b44171 Revert "arm64: dts: qcom: x1e80100: enable OTG on USB-C controllers"
11d19fa272bb Revert "arm64: dts: qcom: x1e80100-crd: enable otg on usb ports"
afdfc5f25296 arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5
33793000f4a4 arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a
5d5a71565a1c Revert "arm64: dts: qcom: x1e78100-t14s: enable otg on usb-c ports"
5f53f8bb69d2 Merge tag 'soc-fixes-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
b4d2d007bfdf Merge tag 'iio-fixes-for-6.13a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-linus
8ffbadf01db0 ASoC: dt-bindings: realtek,rt5645: Fix CPVDD voltage comment
008abf9e254a Merge tag 'v6.13-rc3-dts-raw'
a8fc9cf94eb5 Merge tag 'arc-6.13-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
2c35fa0d488f Merge tag 'usb-6.13-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
3e232d1e666c ARC: dts: Replace deprecated snps,nr-gpios property for snps,dw-apb-gpio-port devices
f745a9511362 Merge tag 'juno-fix-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixes
fbf5077068b9 regulator: dt-bindings: qcom,qca6390-pmu: document wcn6750-pmu
37ab64667e47 ARM: dts: imxrt1050: Fix clocks for mmc
dab0a5e156fb arm64: dts: imx95: correct the address length of netcmix_blk_ctrl
7eae94b44a89 Merge tag 'v6.13-rc2-dts-raw'
e78a7e2b0cd7 arm64: dts: imx8-ss-audio: add fallback compatible string fsl,imx6ull-esai for esai
45813ccd2a7b dt-bindings: iio: st-sensors: Re-add IIS2MDC magnetometer
1946afa68c64 Merge tag 'pmdomain-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
f1f0da779072 Merge tag 'linux-watchdog-6.13-rc1' of git://www.linux-watchdog.org/linux-watchdog
d763929c7513 arm64: dts: fvp: Update PCIe bus-range property
54996f58c80e dt-bindings: phy: imx8mq-usb: correct reference to usb-switch.yaml
b1aa978c13bf dt-bindings: mtd: fixed-partitions: Fix "compression" typo
bdb818f3713b arm64: dts: rockchip: rename rfkill label for Radxa ROCK 5B
63c1a08a6ade arm64: dts: rockchip: add reset-names for combphy on rk3568
ba53ae02e092 dt-bindings: power: mediatek: Add another nested power-domain layer
07d0c70010a5 Merge tag 'v6.13-rc1-dts-raw'
5637b45be13b arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions
9b262efab34c Merge tag 'i2c-for-6.13-rc1-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
ed44ac60a90e Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
edfdcfeb9045 Merge tag 'rtc-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
a814b904106d Merge tag 'tty-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
bbb47e849ae5 Merge tag 'char-misc-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
e63bdbcacef6 Merge tag 'staging-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
f19ac76126e4 Merge tag 'usb-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
556f16e8ae4c Merge tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
5e598b221885 Merge tag 'regulator-fix-v6.13-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
1206af144c4a Merge tag 'for-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
4b78bb4b845e Merge tag 'pm-6.13-rc1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
2b75cf774b29 Merge tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
ea19b796a46c Merge tag 'dmaengine-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
1133f1ec2065 Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
746c372b8ad6 Merge tag 'loongarch-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
4fed1a0b1885 Merge branch 'pm-opp'
fc3ef2d2a08a Merge tag 'kvm-riscv-6.13-2' of https://github.com/kvm-riscv/linux into HEAD
211c1fea1d18 Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux into HEAD
5bbcb87b4e8a dt-bindings: Unify "fsl,liodn" type definitions
11712cccac6a arm64: dts: mediatek: mt8173-elm-hana: Mark touchscreens and trackpads as fail
3412036f44ec Merge tag 'rproc-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
f6916ccc6810 Merge tag 'pci-v6.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
c8ac80d24539 LoongArch: dts: Add I2S support to Loongson-2K2000
78c8af2e4435 LoongArch: dts: Add I2S support to Loongson-2K1000
dd845634778c Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
c371d27c22df Merge tag 'mailbox-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
318d6ab86b21 Merge tag 'pinctrl-v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
593d0bf860b6 Merge tag 'i2c-for-6.13-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
e958eeea5d92 Merge branch 'pci/controller/qcom'
801c1432c854 Merge branch 'pci/controller/microchip'
eae7c4992556 Merge tag 'input-for-v6.13-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
fe51d1a81fe8 dt-bindings: mailbox: Add thead,th1520-mailbox bindings
d117c6077557 dt-bindings: mailbox: qcom-ipcc: Add SM8750
a5d0d60dc7b1 dt-bindings: mailbox: qcom,apcs-kpss-global: correct expected clocks for fallbacks
8abe9b373f38 dt-bindings: mailbox: qcom-ipcc: Add SAR2130P compatible
81b4a2d4a0c3 dt-bindings: mailbox: mpfs: fix reg properties
a45ebe5f9f40 dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk freq optimized
2ee96fbc8c27 dt-bindings: i2c: nomadik: support 400kHz < clock-frequency <= 3.4MHz
a0589920dc8b dt-bindings: i2c: nomadik: add mobileye,eyeq6h-i2c bindings
35d18ffaacbc dt-bindings: i2c: mv64xxx: Add Allwinner A523 compatible string
ca13487bccee MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a
dada4910fa78 Merge tag 'iommu-updates-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
a97f5234955e Merge tag 'thermal-6.13-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
89534c5c0ee3 Merge tag 'pm-6.13-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
eb0295acbf42 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
c299ef125ca8 Merge tag 'backlight-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
65a2f98075d6 Merge tag 'leds-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
b6fddbbdea9e Merge tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
590065c0905d Merge tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel
dc4900bf152f Merge tag 'sound-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
5d1a70ddfc54 Merge tag 'i2c-for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
c6ee89ab9656 Merge tag 'net-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
4535ffa44df9 dt-bindings: riscv: Add Svade and Svadu Entries
c8aedfade1c8 Merge tag 'soc-drivers-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
61b798afa773 Merge tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
37c659acf984 mips: dts: realtek: Add SPI NAND controller
94d5730e0e14 Merge tag 'media/v6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
e6d79eee5678 Merge tag 'hid-for-linus-2024111801' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
f787d015b4d0 Merge tag 'devicetree-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
bf1e79882185 Merge tag 'mmc-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
a2fa4706a249 Merge tag 'pmdomain-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
bff422d6c9a5 Merge tag 'gpio-updates-for-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
f198cc9328e2 Merge tag 'pwm/for-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
b5f1623d4cf5 Merge tag 'spi-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
0fb4cce57122 Merge tag 'regulator-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
f78409f8ed71 Merge tag 'timers-core-2024-11-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
f9da6fbe19f3 Merge tag 'irq-core-2024-11-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
d899fe1de24b Merge tag 'thermal-v6.13-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
2fc3f7277835 Merge tag 'opp-updates-6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
7e7b0e62a08d Merge tag 'cpufreq-arm-updates-6.13' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
092aa09090cc Merge tag 'edac_updates_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
5122a15a7641 Merge tag 'hwmon-for-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
3707c212dfd4 Merge tag 'v6.13-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
406bc7dd4a19 dt-bindings: regulator: qcom-labibb-regulator: document the pmi8950 labibb regulator
8c237be9ce96 arm64: dts: apm: Remove unused and undocumented "bus_num" property
013cc605fbdd arm: dts: spear13xx: Remove unused and undocumented "pl022,slave-tx-disable" property
92cd6f965727 arm64: dts: amd: Remove unused and undocumented "amd,zlib-support" property
054fb11029ed Merge tag 'sunxi-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
0813b7768a18 Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-next
732a2ef869ae Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next
9c8d2f73021e Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next
e5eb1f3324f9 Merge branches 'clk-cleanup', 'clk-mediatek', 'clk-kunit', 'clk-xilinx' and 'clk-fixed-gate' into clk-next
bfaae6ff9e59 Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
68283c980cd9 Merge tag 'mips_6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
79bfc7441791 Merge tag 'for-6.13/block-20241118' of git://git.kernel.dk/linux
0c01c94ca0e4 Merge tag 'ata-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
3a3ade96051d dt-bindings: net: renesas,ether: Drop undocumented "micrel,led-mode"
26283f99abfc Merge branch 'for-6.13/goodix' into for-linus
94a60aceafae Merge tag 'asoc-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
494ff953c027 Merge tag 'i2c-host-6.13-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
c53be2ce2415 arm64: dts: qcom: sc8180x: Add a SoC-specific compatible to cpufreq-hw
2b8e420a3270 dt-bindings: cpufreq: cpufreq-qcom-hw: Add SC8180X compatible
6596841d5093 dt-bindings: i2c: Add Realtek RTL I2C Controller
bca673ba1132 dt-bindings: i2c: imx: add SoC specific compatible strings for S32G
4526cf8d2335 dt-bindings: i2c: microchip: corei2c: Add PIC64GX as compatible with driver
5aeeb0598129 dt-bindings: i2c: qcom-cci: Document SDM670 compatible
54f022df57b2 dt-bindings: usb: maxim,max33359: add usage of sink bc12 time property
1ed83030fdb3 dt-bindings: connector: Add time property for Sink BC12 detection completion
85167dc2ae25 dt-bindings: remoteproc: qcom,sm8350-pas: add SAR2130P aDSP compatible
83bca830540d dt-bindings: remoteproc: qcom,sm8550-pas: Add SM8750 ADSP
2bdefd8183a1 dt-bindings: net: dsa: microchip,ksz: Drop undocumented "id"
6eb17b2bd78c Merge tag 'for-net-next-2024-11-14' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
2a14ef2ac5e0 Merge branch 'dt/linus' into dt/next
bae5aba3f9a3 MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks
bc1acfc7ba28 MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
20d38d5ed30c Merge branches 'arm/smmu', 'mediatek', 's390', 'ti/omap', 'riscv' and 'core' into next
a0794b374609 dt-bindings: net: sff,sfp: Fix "interrupts" property typo
15f59fa95127 dt-bindings: net: mdio-mux-gpio: Drop undocumented "marvell,reg-init"
abaa833875a2 dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
d4692890e218 dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
8b8b3b527dd8 dt-bindings: clock: axi-clkgen: include AXI clk
0fb8688d489e Merge tag 'v6.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-bindings
8082b4609710 dt-bindings: clock: Add Marvell PXA1908 clock bindings
ec9532ca76f2 dt-bindings: clock: airoha: Update reg mapping for EN7581 SoC.
faac8e7307da dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers
1ddd28078d2c dt-bindings: net: bluetooth: nxp: Add support for power save feature using GPIO
6e00e8e10462 dt-bindings: clock: actions,owl-cmu: convert to YAML
8632a52cf6bb dt-bindings: clock: ti: Convert mux.txt to json-schema
3a3d3efe9f2f ASoc: simple-mux: Allow to specify an idle-state
f1a21c9027aa ASoC: Merge up fixes
2a6f86b68aef ASoC: dt-bindings: simple-mux: add idle-state property
e57711411998 Merge tag 'at24-updates-for-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
c817c4dd5391 dt-bindings: net: dsa: microchip: Add LAN9646 switch support
13bd51fa1dc3 Merge tag 'wireless-next-2024-11-13' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
177c7f83ccb1 Merge tag 'at91-soc-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
3d87efe60dff Merge tag 'at91-dt-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
877c4e7469b0 dt-bindings: hwmon: isl68137: add bindings to support voltage dividers
1067dd80f2cf Merge tag 'v6.13-armsoc/drivers1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
57d263a89884 Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
166d602e19ff dt-bindings: thermal: tsens: Add MSM8937
e85bd8dc346a dt-bindings: thermal: qcom-tsens: Add SAR2130P compatible
6ec582f4202e dt-bindings: serial: Add a new compatible string for ums9632
75178b614606 regulator: dt-bindings: qcom,rpmh: Correct PM8550VE supplies
a5865ee38927 dt-bindings: pinctrl: qcom: Add sm8750 pinctrl
21b92a318c68 dt-bindings: timer: actions,owl-timer: convert to YAML
cf31a6391668 dt-bindings: input: Goodix GT7986U SPI HID Touchscreen
3e51a972eb07 Merge tag 'samsung-drivers-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
a7c4f30bb64b Merge tag 'asahi-soc-dt-6.13' of https://github.com/AsahiLinux/linux into soc/dt
a4fd8e1dfc43 Merge tag 'v6.13-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
2c162aaf86bf Merge tag 'v6.13-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
bd05bfd61ea1 Merge tag 'sunxi-dt-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
b27a64825ed4 Merge tag 'riscv-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
ba090176b165 Merge tag 'mvebu-dt64-6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
6bf22927b301 Merge tag 'mvebu-dt-6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
0f2aa55f6305 dt-bindings: hwmon: pwm-fan: Document start from stopped state properties
426cb331c9cc dt-bindings: hwmon: ti,tmp108: Add nxp,p3t1085 compatible string
ae309085b834 dt-bindings: hwmon: pmbus: add ti tps25990 support
5da2c2026bd2 Merge tag 'stm32-dt-for-v6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
9c3899079f19 Merge tag 'ti-k3-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
0b3cd09d6ce5 Merge tag 'amlogic-arm64-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
f26dab644e22 Merge tag 'amlogic-arm-dt-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
deb57f61c6df Merge tag 'riscv-sophgo-dt-for-v6.13' of https://github.com/sophgo/linux into soc/dt
4726cfc72104 arm64: dts: lg131x: Update spi clock properties
d89970dd389d arm64: dts: seattle: Update spi clock properties
930d668738e9 Merge tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
ce2d746e1530 Merge tag 'omap-for-v6.13/dt-signed-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
f105a6053107 Merge tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
387af474eee3 Merge tag 'mtk-dts64-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
53a949e36049 Merge tag 'imx-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
16f098c332bd Merge tag 'imx-dt-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
51aaab41dffd Merge tag 'imx-bindings-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
17e5fb03d215 Merge tag 'qcom-arm32-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
31626a0e0ee3 Merge tag 'socfpga_dts_updates_for_v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
152ae851dbfa Merge tag 'zynqmp-dt-for-6.13' of https://github.com/Xilinx/linux-xlnx into soc/dt
f90a49f1e27b Merge tag 'v6.13-armsoc/dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
ae55eb28a726 Merge tag 'samsung-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
3d49ae1f0a1b Merge tag 'tegra-for-6.13-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
07ff07464e33 Merge tag 'tegra-for-6.13-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
7f89fd77486c Merge tag 'ux500-dts-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into soc/dt
05ebe6553b4d Merge tag 'renesas-dts-for-v6.13-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
16235aeda228 Merge tag 'thead-dt-for-v6.13-p2' of https://github.com/pdp7/linux into soc/dt
6fa0b8a99183 Merge tag 'thead-dt-for-v6.13' of https://github.com/pdp7/linux into soc/dt
7e058b903582 dt-bindings: power: qcom,rpmpd: document the SM8750 RPMh Power Domains
f6a47c3457a0 dt-bindings: mfd: bd71828: Use charger resistor in mOhm instead of MOhm
4b18f1610238 Merge tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
dda26b78365e mips: dts: realtek: Add I2C controllers
b71367867087 mips: dts: realtek: Add syscon-reboot node
79779e7c715d dt-bindings: mfd: sprd,sc2731: Convert to YAML
5dae93564df4 dt-bindings: rtc: Add Amlogic A4 and A5 RTC
26e180301e14 dt-bindings: mfd: Add Realtek RTL9300 switch peripherals
1891c1b614b2 dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8917
b1ba8faed042 dt-bindings: leds: pwm: Add default-brightness property
f399c33dfe79 dt-bindings: usb: add A523 compatible string for EHCI and OCHI
947c6f46a132 dt-bindings: usb: sunxi-musb: add Allwinner A523 compatible string
d441b40639a5 dt-bindings: ata: ahci-platform: add missing iommus property
723c65f36e60 dt-bindings: net: dsa: microchip: add mdio-parent-bus property for internal MDIO
58487abd9efe dt-bindings: net: dsa: microchip: add internal MDIO bus description
8d58a2dd6d84 dt-bindings: power: reset: Convert mode-.* properties to array
1789292f1a7c dt-bindings: power: supply: sc27xx-fg: document deprecated bat-detect-gpio
5538bdf2a501 dt-bindings: rtc: sun6i: Add Allwinner A523 support
20e517ff0e61 Merge patch series "Zacas/Zabha support and qspinlocks"
123d509ffce3 dt-bindings: riscv: Add Ziccrse ISA extension description
9442e2221b50 dt-bindings: riscv: Add Zabha ISA extension description
19eeccaea220 arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25
f80689fcef4b arm64: dts: rockchip: add Radxa ROCK 5C
cf73817a27fe dt-bindings: arm: rockchip: add Radxa ROCK 5C
6f9651cdd68b arm64: dts: rockchip: orangepi-5-plus: Enable GPU
0969ba564561 arm64: dts: rockchip: enable USB3 on NanoPC-T6
d0831b4f29fa arm64: dts: rockchip: adapt regulator nodenames to preferred form
5b243675290c arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi GenBook
23fd319073ff arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi 4B
3900aca0874b arm64: dts: rockchip: Enable HDMI0 for rk3588 Cool Pi CM5 EVB
2c753fe0da98 arm64: dts: rockchip: Enable HDMI on NanoPi R6C/R6S
8e4a55566af5 arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
7b1c800bcde2 arm64: dts: rockchip: Enable HDMI on Hardkernel ODROID-M2
c436bbae9ee0 arm64: dts: rockchip: Remove non-removable flag from sdmmc on rk3576-sige5
1980d45b0897 ASoC: dt-bindings: stm32: add missing port property
2893b7f5fb7a Merge tag 'icc-6.13-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
b32a9156b890 Merge tag 'v6.12-rc7' into __tmp-hansg-linux-tags_media_atomisp_6_13_1
c7134866aa26 Merge tag 'drm-misc-next-2024-11-08' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
9c04f56979b1 dt-bindings: Add SY24655 to ina2xx devicetree bindings
5ff094ad6592 dt-bindings: hwmon: ltc2978: add support for ltc7841
d9ef63ef8a11 dt-bindings: hwmon: Add NCT7363Y documentation
c0471d92c15c dt-bindings: hwmon: pmbus: Add bindings for Vicor pli1209bc
d5eaf6b6924f dt-bindings: hwmon: pmbus: Add bindings for MPS MP297x
cdad7d08ac3b dt-bindings: hwmon: add renesas,isl28022
cfd9365d2a13 dt-bindings: hwmon: add support for ti,amc6821
ddc5f672209b dt-bindings: rtc: mpfs-rtc: remove Lewis from maintainers
2865159e6810 dt-bindings: spmi: qcom,x1e80100-spmi-pmic-arb: Add SAR2130P compatible
c50dfc3a2aab dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8188
a190753f88d0 arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
4991141770ff arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer
e4b43ce62e72 dt-bindings: rng: add binding for BCM74110 RNG
941365ad45c2 ARM: dts: rockchip: adapt regulator nodenames to preferred form
bf61fdbdcb67 arm64: dts: rockchip: Enable HDMI0 on FriendlyElec CM3588 NAS
b20c5c1134f6 arm64: dts: rockchip: add Banana Pi P2 Pro board
e25bd251aa0e dt-bindings: arm: rockchip: add Banana Pi P2 Pro board
be5707904383 arm64: dts: rockchip: Add new SoC dtsi for the RK3566T variant
5490c2e7cf29 arm64: dts: rockchip: Prepare RK356x SoC dtsi files for per-variant OPPs
446fb0e5e919 arm64: dts: rockchip: Update CPU OPP voltages in RK356x SoC dtsi
a0399eec38f1 arm64: dts: rockchip: Add OPP voltage ranges to RK3399 OP1 SoC dtsi
edc6a2d078cf arm64: dts: rockchip: Enable HDMI0 on Indiedroid Nova
b212feea5740 arm64: dts: rockchip: Enable GPU on Indiedroid Nova
55b9ba0d6a3f arm64: dts: rockchip: correct analog audio name on Indiedroid Nova
067743d4f0ba dt-bindings: iio: adc: ad7380: add adaq4370-4 and adaq4380-4 compatible parts
86b95e793090 Merge commit '9365f0de4303f82ed4c2db1c39d3de824b249d80' into HEAD
f330887620af ASoC: stm32: i2s: add stm32mp25 support
3739109e0b30 dt-bindings: interrupt-controller: qcom,pdc: Add SAR2130P compatible
62ad47978cfe dt-bindings: Enable dtc "interrupt_provider" warnings
8aec8212bc90 ASoC: dt-bindings: add stm32mp25 support for i2s
ddcb952e0d83 ASoC: dt-bindings: add stm32mp25 support for sai
6533ea7e371c media: dt-bindings: Add qcom,msm8953-camss
0400a923076e media: dt-bindings: adv7180: Document 'adi,force-bt656-4'
cad71a536128 dt-bindings: pinctrl: sx150xq: allow gpio line naming
4fc4402b096a dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible
957318c990d9 dt-bindings: pinctrl: correct typo of description for cv1800
964a6e882b70 dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8937 compatible
6f8ca0d8db72 dt-bindings: pinctrl: qcom,pmic-gpio: add PM8937
f1565113396b Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
08d9d0f1c1f1 Add a driver for the Iron Device SMA1307 Amp
f2f280762a9e arm64: dts: sun50i-a64-pinephone: Add mount-matrix for PinePhone magnetometers
6a0f30875a00 arm64: dts: sun50i-a64-pinephone: Add AF8133J to PinePhone
19a5f6136083 dt-bindings: PCI: microchip,pcie-host: Add reg for Root Port 2
55fb5e5b420f dt-bindings: watchdog: Document ExynosAutoV920 watchdog bindings
054c654fe1f3 dt-bindings: watchdog: fsl-imx-wdt: Add missing 'big-endian' property
8ea12deded37 dt-bindings: watchdog: Document Qualcomm QCS8300
730c3664636b media: dt-bindings: Add OmniVision OV08X40
f9a3c027aa9d media: dt-bindings: Remove assigned-clock-* from various schema
7566186de0e0 riscv: dts: thead: Add TH1520 ethernet nodes
386669413e02 dt-bindings: interrupt-controller: Add T-HEAD C900 ACLINT SSWI device
1646cca4d199 ASoC: dt-bindings: maxim,max98390: Reference common DAI properties
ee6c807e70e1 spi: dt-bindings: apple,spi: Add binding for Apple SPI controllers
876cffaa982c ASoC: dt-bindings: irondevice,sma1307: Add initial DT
160064141ff7 Merge tag 'exynos-drm-next-for-v6.13-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
fc688470a160 dt-bindings: net: Add T-HEAD dwmac support
9b1f83707883 dt-bindings: net: snps,dwmac: add support for Arria10
460309ffbb0c Merge branch '20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com' into clk-for-6.13
23cfc4f08cb1 dt-bindings: clock: qcom: Add GCC clocks for QCS8300
f3d1192d6712 dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
42d048cdf864 Merge branch '20241028060506.246606-3-quic_srichara@quicinc.com' into clk-for-6.13
fafe71156483 dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
7e1403abe239 Merge branch '20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org' into clk-for-6.13
2defff84b795 dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
3894d09b6e84 dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
a72e5c09c7f4 dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
28f260417c06 dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
60cc5850fdfc dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
df87984c1613 dt-bindings: display: samsung,exynos7-decon: add exynos7870 compatible
d50643ee756b Merge tag 'drm-msm-next-2024-11-04' of https://gitlab.freedesktop.org/drm/msm into drm-next
b3e4ab4f064e dt-bindings: firmware: qcom,scm: Document sm8750 SCM
463a6ef40f74 dt-bindings: PCI: snps,dw-pcie: Drop "#interrupt-cells" from example
03102039e316 Merge tag 'mediatek-drm-next-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
34a8c575f1c8 ASoC: codecs: Add aw88081 amplifier driver
8f4e264ce11e ASoC: dt-bindings: everest,es8326: Document interrupt property
4e44f374d949 ASoC: dt-bindings: mediatek,mt8188-mt6359: Add mediatek,adsp property
6f4ed65f7dd8 arm64: dts: marvell: Drop undocumented SATA phy names
7b21455daa8f ASoC: dt-bindings: fsl-esai: allow fsl,imx8qm-esai fallback to fsl,imx6ull-esai
8c018a0ee4a8 ASoC: dt-bindings: qcom,sm8250: Add SM8750 sound card
8a48011ba43b ASoC: dt-bindings: sprd,sc9860-mcdt: convert to YAML
7b4ce90e74f0 ASoC: dt-bindings: sprd,pcm-platform: convert to YAML
5823f4fe0659 ASoC: dt-bindings: fsl_spdif: Document imx6sl/sx compatible fallback
7e14eb16d5b3 dt-bindings: usb: qcom,dwc3: Add SAR2130P compatible
51bf70618e24 Merge branch 'for-linus' into for-next
22f3676ff712 ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board
47d31036aa61 dt-bindings: arm: add sam9x75 curiosity board
0501f23b39df ARM: dts: at91: sam9x7: add device tree for SoC
d5a9f68a0aea dt-bindings: display: bridge: Add ITE IT6263 LVDS to HDMI converter
70e9f6df13a8 dt-bindings: display: Document dual-link LVDS display common properties
6934292e075c dt-bindings: display: lvds-data-mapping: Add 30-bit RGB pixel data mappings
6f27127c4a26 dt-bindings: watchdog: airoha: document watchdog for Airoha EN7581
daa8216ec644 Merge v6.12-rc6 into usb-next
056bfa125b25 Merge 6.12-rc6 into char-misc-next
4161d4c159eb dt-bindings: input: rotary-encoder: Fix "rotary-encoder,rollover" type
a687918c0646 dt-bindings: nvmem: sprd,sc2731-efuse: convert to YAML
1aa204d6b806 dt-bindings: nvmem: sprd,ums312-efuse: convert to YAML
d1d8d849187e dt-bindings: nvmem: convert zii,rave-sp-eeprom.txt to yaml format
17763c48b366 dt-bindings: fuse: Move renesas,rcar-{efuse,otp} to nvmem
9654bb88a716 Merge branch 'icc-sar2130p' into icc-next
dd017956b3ce Merge branch 'icc-qcs615' into icc-next
a17c617ee41c Merge branch 'icc-qcs8300' into icc-next
8370d645f4b6 Merge tag 'mtk-soc-for-v6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into arm/drivers
53631c4ff314 Merge tag 'drm-msm-next-2024-10-28' of https://gitlab.freedesktop.org/drm/msm into drm-next
c904ffa3b82b ARM: dts: omap4-kc1: fix twl6030 power node
2155689ca359 ARM: dts: am335x-bone-common: Increase MDIO reset deassert delay to 50ms
8dc422e35be3 ARM: dts: turris-omnia: Add global LED brightness change interrupt
607ccd1474a1 ARM: dts: marvell: kirkwood: Fix at24 EEPROM node name
346a3de67692 Merge tag 'qcom-drivers-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers
ba19144661e0 arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon
598a4d98663f Merge tag 'memory-controller-drv-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
17e8e3195ac5 dt-bindings: watchdog: Document Qualcomm QCS615 watchdog
11e178dc255e arm64: dts: mediatek: mt8183-kukui: Drop bogus fixed regulators
f77f82632596 arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add supplies for fixed regulators
24fc1ae800ba arm64: dts: mediatek: mt8183-kukui-jacuzzi: Fix DP bridge supply names
f5b0e5328756 arm64: dts: mediatek: mt6358: fix dtbs_check error
d5140dfa5ec4 arm64: dts: mediatek: mt8186-corsola: Fix IT6505 reset line polarity
d9e000034473 dt-bindings: net: add bindings for NETC blocks control
9fe0d2d4fd4b dt-bindings: net: add i.MX95 ENETC support
826299f01c00 dt-bindings: net: add compatible string for i.MX95 EMDIO
d1dd8567ae0f arm64: dts: freescale: imx8mp-verdin: Fix SD regulator startup delay
d490130f1b5b arm64: dts: freescale: imx8mm-verdin: Fix SD regulator startup delay
9e74cfa8aed7 arm64: dts: imx8mp-verdin: add single-master property to all i2c nodes
e311a676d575 arm64: dts: imx8mm-verdin: add single-master property to all i2c nodes
7ca54a28453d arm64: dts: imx95: Add missing vendor string to SCMI property
1e0645252385 arm64: dts: imx8mp-navqp: Add HDMI support
f69334422236 arm64: dts: imx8qm-ss-hsio: fix PCI and SATA clock indices
52db967c6836 arm64: dts: imx8qm-ss-hsio: fix interrupt-map indent under pci* nodes
4ad8c25409b5 arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0
9c1b6d13e36e arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and output-high in GPIO
9b2e30519b00 arm64: dts: layerscape: remove en25s64 and only keep jedec,spi-nor compatible string
112a2f10e385 arm64: dts: imx8mp-kontron-dl: change touchscreen power-supply to AVDD28-supply
0f08165e91f7 arm64: dts: imx8mp: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board
64e784a46469 arm64: dts: imx8: move samsung,burst-clock-frequency to imx8mn and imx8mm mba8mx board file
83fb50675bc3 arm64: dts: mba8mx: remove undocumented 'data-lanes' at panel
0e24192fd5df arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support
37833e2088f6 arm64: dts: imx8ulp-evk: Add spdif sound card support
750ba00a205a arm64: dts: imx8ulp-evk: Add bt-sco sound card support
7d99d457b93d arm64: dts: imx8ulp: Add audio device nodes
f4b3c64c0244 arm64: dts: imx8qm-mek: enable dsp node for rproc usage
1caf91ab383e arm64: dts: imx8qm: add node for VPU dsp
fbc00480351a arm64: dts: imx8qm: drop dsp node from audio_subsys bus
28f0a4fda11f arm64: dts: imx8qxp-mek: add dsp rproc-related mem regions
5d166eadac0c arm64: dts: imx8-ss-audio: configure dsp node for rproc usage
e5e252f95438 Merge tag 'v6.12-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
4c2e02e65cdd ARM: dts: imx: Add devicetree for Kobo Clara 2E
6b94da0ee5dd dt-bindings: arm: fsl: add compatible strings for Kobo Clara 2E
202c40aec2b8 Backmerge v6.12-rc6 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
b103f56c1313 dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
1cb298e50005 dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
d1a15a60e3dd dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P
b5252d8ac17a dt-bindings: serial: samsung: Add samsung,exynos8895-uart compatible
150da36dbb3e dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2044 uarts
8d33fdaef0c9 dt-bindings: serial: snps,dw-apb-uart: merge duplicate compatible entry.
0221e5a00939 dt-bindings: usb: Describe TUSB1046 crosspoint switch
9ced24730a60 dt-bindings: usb: add TUSB73x0 PCIe
9f0df430d226 dt-bindings: net: snps,dwmac: Fix "snps,kbbe" type
d37a18c3359d dt-bindings: iio: magnetometer: document the Allegro MicroSystems ALS31300 3-D Linear Hall Effect Sensor
89d25ea2ca64 dt-bindings: vendor-prefixes: Add Allegro MicroSystems, Inc
67d497917b1c dt-bindings: iio: light: veml6075: document vishay,rset-ohms
42fa3119d0f6 dt-bindings: iio: dac: ad5791: Add required voltage supplies
17ed50b8e5b2 dt-bindings: iio: dac: ad5791: Add optional reset, clr and ldac gpios
b8c3bcba7006 dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
3f1c84e16a83 dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml
8be0ac5e2035 dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller
b6b07e2734ce arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
77fef08ac39f arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
4279f7bfeca0 arm64: dts: renesas: r9a08g045: Add RTC node
c662c8fd62d0 arm64: dts: renesas: r9a08g045: Add VBATTB node
3b4ff03ddadd Merge tag 'renesas-r9a08g045-dt-binding-defs-tag3' into renesas-dts-for-v6.13
b574ea7102f4 arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ
b1b4b25b826b ARM: dts: renesas: r7s72100: Add DMA support to MMCIF
d9254ef42935 ARM: dts: renesas: r7s72100: Add DMAC node
24f9da7ff499 arm64: dts: renesas: hihope: Drop #sound-dai-cells
a1c74be440b4 dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
ddbfd89adc2b arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry
ea0e401633cb arm64: dts: ti: k3-am62p: add opp frequencies
ff729dee84ac arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry
bb3fd30ebdc2 arm64: dts: ti: k3-am62a: add opp frequencies
4e946fcedb0a arm64: dts: ti: k3-am62-verdin: Add Ivy carrier board
3c9f7ab0f160 arm64: dts: ti: k3-am62-verdin: add label to som adc node
331663639dd4 dt-bindings: arm: ti: Add verdin am62 ivy board
a5ed55d5f102 dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible
3c02cd885435 arm64: allwinner: a100: Add MMC related nodes
5d066483a0d1 arm64: dts: allwinner: a100: add usb related nodes
036fcc436587 dt-bindings: usb: sunxi-musb: Add A100 compatible string
146dcab6bf5d dt-bindings: usb: Add A100 compatible string
9c1f15141146 dt-bindings: phy: sun50i-a64: add a100 compatible
75547bc28cb8 arm64: dts: allwinner: a100: add watchdog node
d54b845fdacb arm64: dts: allwinner: A100: Add PMU mode
aca70dbb9197 riscv: dts: sophgo: Add emmc support for Huashan Pi
42878e08ab97 riscv: dts: sophgo: Add sdio configuration for Huashan Pi
eb07cad87c26 riscv: dts: sophgo: fix pinctrl base-address
8e37388c023b ARM: dts: imx6sll: Improve gpc description
b8bd0f9f429f dt-bindings: power: fsl,imx-gpc: Document fsl,imx6sll-gpc
f4ecbd3601e6 ARM: dts: imx6sl: Pass tempmon #thermal-sensor-cells
ba6c85227642 ARM: dts: imx6sx: Fix tempmon description
331a16df15a3 ARM: dts: imx6sll: Remove regulator-3p0 unit address
47c8e9173f81 dt-bindings: soc: imx: fsl,imx-anatop: Add additional regulators
3ae26b145a89 dt-bindings: soc: imx: fsl,imx-anatop: Fix the i.MX7 irq number
255ba77d9c2d ARM: dts: imx6sll: Fix the last SPDIF clock name
c42453e6426e dt-bindings: mfd: aspeed: Support for AST2700
2a73067c2a22 dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
5397edc4d601 dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant
9caf7607e387 dt-bindings: iio: dac: ad3552r: add iio backend support
763816eac739 dt-bindings: iio: imu: bmi270: Add Bosch BMI260
713fa6540db4 dt-bindings: iio: light: veml6030: add veml3235
dba57ae0cfce ASoC: dt-bindings: Add schema for "awinic,aw88081"
a19f983c0d5c arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add cma heap for libcamera softisp support
28471dd8f4a6 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add cma heap for libcamera softisp support
b9629dab901b arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop redundant clock-lanes from camera@1a
1ddecd567632 arm64: dts: qcom: sc8280xp-x13s: Drop redundant clock-lanes from camera@10
be774e8d2ab8 arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso
3f2133c08066 ARM: dts: imx7ulp: Remove incorrect mmc fallback compatible
7506bc6cb797 ARM: dts: imx6sl: Remove incorrect mmc fallback compatible
28933a53f55c ARM: dts: imx6sx: Remove incorrect mmc fallback compatible
1f840a106c30 ARM: dts: imx6sl/sll: Add the "fsl,imx6dl-gpt" fallback
a894fbc7d9c2 dt-bindings: arm: fsl: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board
fba51fea7ab6 dt-bindings: arm: fsl: Add Gateworks GW82XX-2x dev kit
6e1ac4df7d84 dt-bindings: dsp: fsl,dsp: fix power domain count
3fb0f7f167d1 ARM: dts: imx6ul: Drop duplicate space in iomux node groups
db27e15bb568 ARM: dts: imx6sx: Align pin config nodes with bindings
abb4de37ca85 ARM: dts: imx6sl: imx6sll: Align pin config nodes with bindings
36f077eedcaf ARM: dts: imx6qp: Align pin config nodes with bindings
39f669d0e202 ARM: dts: imx6qdl: Align pin config nodes with bindings
98bf72bdd507 ARM: dts: imx6q: Align pin config nodes with bindings
cbdbce56bc99 ARM: dts: imx6dl: Align pin config nodes with bindings
1b47588d2862 ARM: dts: imx53: Align pin config nodes with bindings
d6f94f6b81c9 ARM: dts: imx51: Align pin config nodes with bindings
96f9d558ff37 ARM: dts: imx50: Align pin config nodes with bindings
028df26bebec ARM: dts: imx35: Align pin config nodes with bindings
3beb7b7a5c8e arm64: dts: imx8mm-venice-gw73xx: remove compatible in overlay file
52d3e69f3742 arm64: dts: imx93: Add LPSPI alias
8299fb97f122 arm64: dts: imx8ulp: Add LPSPI alias
b7d284ff717f arm64: dts: imx8dxl: Add LPSPI alias
8beff2148426 arm64: dts: imx8qm: Add LPSPI alias
512aedaf436b arm64: dts: imx8qxp: Add LPSPI alias
6ef56051d213 ARM: dts: imx6qdl: convert fsl,tx-d-cal to correct value
ec366f90d9bb arm64: dts: imx8qxp: change usbphy1 compatible
cea897ccd54b arm64: dts: imx8qm: change usbphy1 compatible
874df11138be arm64: dts: imx8dxl-ss-conn: change usbphy1 compatible
02bb93887167 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
561ec2dba20c dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP
5f24de097e7e dt-bindings: mfd: x-powers,axp152: Document AXP323
fdd7b26f4e12 dt-bindings: leds: pca955x: Convert text bindings to YAML
f25661476440 Merge tag 'ath-next-20241030' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
62e231406590 riscv: dts: starfive: add DeepComputing FML13V01 board device tree
32165b14e52d dt-bindings: riscv: starfive: add deepcomputing,fml13v01
d7219d674223 dt-bindings: vendor: add deepcomputing
6ff04cefd0f8 riscv: dts: starfive: jh7110-common: move usb0 config to board dts
dca4975af2f1 riscv: dts: starfive: jh7110-common: revised device node
08c161cb09dd dt-bindings: spi: sprd,sc9860-spi: convert to YAML
0071bdbd8c4a dt-bindings: display: panel: Add Samsung S6E88A0-AMS427AP24
ca71b2ee5303 dt-bindings: display: panel: Move flip properties to panel-common
885d588105ef dt-bindings: net: qcom,ethqos: add description for qcs8300
30c9a2f24d08 dt-bindings: net: qcom,ethqos: add description for qcs615
716fa1e7ccdf dt-bindings: net: renesas,ether: Add iommus property
3f4eb4ad0e43 dt-bindings: net: add compatible strings for lan969x targets
383b9d96b4a7 MIPS: mobileye: eyeq6h-epm6: Use eyeq6h in the board device tree
2c23682394f8 mips: bmips: bcm6358/6368: define required brcm,bmips-cbr-reg
fca10e05179a Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-next
e360d40c1957 ASoC: renesas, rsnd: Update file path
fcc8d656b01e dt-bindings: mfd: Add support for Airoha EN7581 GPIO System Controller
7f06843a8e70 dt-bindings: pwm: airoha: Add EN7581 pwm
cf0edabd92c5 dt-bindings: pinctrl: airoha: Add EN7581 pinctrl
e6aaee853312 dt-bindings: arm: airoha: Add the chip-scu node for EN7581 SoC
f0cd86a71bc4 Merge tag 'wireless-next-2024-10-25' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
797a67e6b014 ARM: dts: ti/omap: omap4-epson-embt2ws: add charger
7efc9f8883cb ARM: dts: omap36xx: declare 1GHz OPP as turbo again
fb2d1cd36043 ARM: ti/omap: omap3-gta04a5: add Bluetooth
ede8f302a975 ARM: dts: ti/omap: dra7: fix redundant clock divider definition
368aa5565758 ARM: dts: ti/omap: use standard node name for twl4030 charger
fff64bcb9e7d ARM: dts: omap: omap4-epson-embt2ws: add GPIO expander
95bd176683f3 ARM: dts: omap: omap4-epson-embt2ws: add unknown gpio outputs
c54ce42be317 ARM: dts: omap: omap4-epson-embt2ws: wire up regulators
f9a228320349 ARM: dts: omap: omap4-epson-embt2ws: define GPIO regulators
7c132391322b dt-bindings: cache: qcom,llcc: Fix X1E80100 reg entries
e87d66603200 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Convert mezzanine riser to dtbo
0e47b353b366 arm64: dts: qcom: sm8450-hdk: model the PMU of the on-board wcn6855
0da5e2831b5f arm64: dts: qcom: sc8280xp-x13s: model the PMU of the on-board wcn6855
b144f43b00c6 arm64: dts: qcom: sc8280xp-crd: enable bluetooth
71dd0754900a arm64: dts: qcom: sc8280xp-crd: model the PMU of the on-board wcn6855
db6231faa8ef arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boards
6db2df13d51b dt-bindings: arm: qcom: Document qcs9100-ride and qcs9100-ride Rev3
939575bddd9e dt-bindings: arm: qcom,ids: add SoC ID for QCS9100
37f62a041104 dt-bindings: soc: qcom,aoss-qmp: Document the QCS8300 AOSS channel
2b6367dc7663 dt-bindings: soc: qcom: add qcom,qcs8300-imem compatible
921d4a5b59ca dt-bindings: firmware: qcom,scm: document SCM on QCS8300 SoCs
b056fb0da587 dt-bindings: arm: qcom: add the SoC ID for SA8255P
353c843385dd dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
eb757c1154d7 dt-bindings: firmware: qcom,scm: document support for SA8255p
023f9687db26 arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers
26e54f2b420b arm64: dts: qcom: x1e80100-crd: describe HID supplies
e13fc809cbc2 dt-bindings: arm-smmu: document QCS615 APPS SMMU
d883086fe6d0 arm64: dts: st: add DMA support on SPI instances of stm32mp25
293e556c3b71 arm64: dts: st: add DMA support on I2C instances of stm32mp25
a6d1ed648360 arm64: dts: st: add DMA support on U(S)ART instances of stm32mp25
b6492a99f4d4 arm64: dts: st: add RNG node on stm32mp251
789463f5f6f9 arm64: dts: ti: k3-am642-phyboard-electra-rdk: Enable trickle charger
da365b4af0fd arm64: dts: st: enable RTC on stm32mp257f-ev1 board
58372f2d5992 arm64: dts: st: add RTC on stm32mp25x
7967e3f18c68 ARM: dts: stm32: add support of WLAN/BT on stm32mp135f-dk
31603dbb73ed ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2
765429189582 ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp135f-dk
dff35cb83ba2 ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on stm32mp157c-dk2
0c7155f0410d ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp13
b45457addbd1 ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15
3c483aafdf06 ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT
139d492884d8 arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variant
cdfae05f1158 arm64: dts: qcom: msm8998-clamshell: enable resin/VolDown
64e0ef2c06b2 arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp button
9f95673168b0 arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPI
a5bac521fc24 arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreen
a8515049c066 ARM: dts: stm32: Add IWDG2 EXTI interrupt mapping and mark as wakeup source
eddd3e969925 ASoC: dt-bindings: document the adau1373 Codec
470374aa96c5 dt-bindings: arm: pmu: Add Samsung Mongoose core compatible
6834ae6fe43e Merge tag 'samsung-pinctrl-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
65f56eb13285 dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU
2a9e11d084c6 dt-bindings: cpufreq: cpufreq-qcom-hw: Add SAR2130P compatible
b194ce2eb3b8 dt-bindings: cpufreq: add virtual cpufreq device
8bc748b3aced dt-bindings: connector: Add properties to define time values
605f85ff9e6f dt-bindings: iio: adc: adi,ad7606: document AD760{7,8,9} parts
6a89ae47b092 dt-bindings: iio: light: opt3001: add compatible for opt3002
70299596e737 dt-bindings: nfc: nxp,nci: Document PN553 compatible
fdd8e743e28d dt-bindings: watchdog: convert zii,rave-sp-wdt.txt to yaml format
01f9cc33c847 dt-bindings: input: convert zii,rave-sp-pwrbutton.txt to yaml
b854e49c0d99 arm64: dts: ti: k3-am64-phycore-som: Add M4F remoteproc nodes
39fc4e8d0c96 arm64: dts: ti: k3-am62-phycore-som: Add M4F remoteproc nodes
98100a4d2f27 arm64: dts: ti: minor whitespace cleanup
b7a07b589550 arm64: dts: ti: k3-am62x-phyboard-lyra: Fix indentation in audio-card
ecf01fc92c51 arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fix bus-width property in MMC nodes
b8c71de468cb arm64: dts: ti: k3-am64-phycore-som: Fix bus-width property in MMC nodes
2d697a33eea7 arm64: dts: ti: k3-am642-evm: Add overlay for PCIe0 EP mode
b2eb2eb13dff arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode
012f0b98adb5 arm64: dts: ti: k3-am62-main: Update otap/itap values
0f5c0fbac643 arm64: dts: ti: k3-am625-beagleplay: Enable MikroBUS PWM
4a83eccaf4bb arm64: dts: ti: k3-am62-verdin: Fix SD regulator startup delay
2b93c69971f5 arm64: dts: ti: k3-am62-verdin: Fix SoM ADC compatible
7b41e5063d24 arm64: dts: ti: k3-am625-verdin: add TPM device
d5934e5672b3 arm64: dts: ti: k3-j721s2: Fix clock IDs for MCSPI instances
5259ea65769a arm64: dts: ti: k3-j721e: Fix clock IDs for MCSPI instances
1aa6fec1bf7f arm64: dts: ti: k3-j7200: Fix clock ids for MCSPI instances
05dadccc1d6e arm64: dts: ti: k3-j7200: Fix register map for main domain pmx
b5e4fcb6a6a4 arm64: dts: ti: k3-j7200-evm*: Add bootph-* properties
23d8a29be7cf arm64: dts: ti: k3-j721e-sk*: Add bootph-* properties
8939387ec242 arm64: dts: ti: k3-j721e-evm*: Add bootph-* properties
1ebacb4afd7d arm64: dts: ti: k3-am68-sk*: Add bootph-* properties
59290b7acdb1 arm64: dts: ti: k3-j721s2-evm*: Add bootph-* properties
96b67eddd9d8 arm64: dts: ti: k3-j784s4-j742s2-evm-common: Remove parent nodes bootph-*
6fc66a1cbbf9 arm64: dts: ti: k3-j7200: Add bootph-* properties
4e700078c990 arm64: dts: ti: k3-j721e: Add bootph-* properties
24856781f185 arm64: dts: ti: k3-j721s2: Add bootph-* properties
5ea5f859d657 arm64: dts: ti: k3-j784s4: Add bootph-* properties
7fe1e46095c4 arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Remove parent nodes bootph-*
1853b9579d48 arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Move bootph from mcu_timer1 to mcu_timer0
114be30a95ab dt-bindings: firmware: arm,scmi: Introduce more transport properties
4a611cd4cf42 dt-bindings: sram: Document reg-io-width property
c548ac9c74e2 dt-bindings: pinctrl: convert pinctrl-mcp23s08.txt to yaml format
cf6826771639 dt-bindings: crypto: qcom-qce: document the SA8775P crypto engine
2b8c1030e8c0 dt-bindings: rng: add support for Airoha EN7581 TRNG
58a715d54f20 dt-bindings: rng: add st,stm32mp25-rng support
6670c8049523 dt-bindings: rng: Add Marvell Armada RNG support
15cd3ba66a63 dt-bindings: soc: rockchip: add rk3588 mipi dcphy syscon
43d7d295f50a dt-bindings: pinctrl: samsung: Add compatible for exynos9810-wakeup-eint
25dc3ef6afee dt-bindings: pinctrl: samsung: Add compatible for Exynos9810 SoC
0b4611bbe9bb dt-bindings: arm: samsung: Document Exynos9810 and starlte board binding
3478405a22cc dt-bindings: soc: samsung: exynos-pmu: Add exynos9810 compatible
5391365435bc dt-bindings: arm: cpus: Add Samsung Mongoose M3
5f722ff65658 dt-bindings: hwinfo: samsung,exynos-chipid: Add Samsung exynos9810 compatible
bb0089d8c302 dt-bindings: display/msm/gmu: Add Adreno 663 GMU
39e708dc0fb1 arm64: dts: exynos8895: Add spi_0/1 nodes
0cf148b180b1 arm64: dts: exynos8895: Add Multi Core Timer (MCT) node
f799b809d6c7 arm64: dts: exynos8895: Add clock management unit nodes
b4fa09099517 dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible
6325725ea9a3 Merge branch 'for-v6.13/clk-dt-bindings' into next/dt64
8da2e616237d Merge branch 'for-v6.13/clk-dt-bindings' into next/clk
eeba38da05de dt-bindings: clock: samsung: Add Exynos8895 SoC
87e26426dfdb ARM: dts: sunxi: add support for RerVision A33-Vstar board
55be2d52b761 dt-bindings: arm: sunxi: document RerVision A33-Vstar board
b53ca4b51fbb arm64: dts: allwinner: Add disable-wp for boards with micro SD card
9f4b1c04a628 ARM: dts: cubieboard4: Fix DCDC5 regulator constraints
556bf94aa7b1 arm64: dts: allwinner: h313/h616/h618/h700: Enable audio codec for all supported boards
4da8ded9f0cc arm64: dts: allwinner: h616: Add audio codec node
f419b2caa850 arm64: dts: apple: Add A11 devices
bcf1afc654cc arm64: dts: apple: Add A10X devices
84201093d52b arm64: dts: apple: Add A10 devices
513b4af7b994 arm64: dts: apple: Add A9X devices
1e48996186f2 arm64: dts: apple: Add A9 devices
718683c792c8 arm64: dts: apple: Add A8X devices
2ba5d138f134 arm64: dts: apple: Add A8 devices
0d01c7eaa9e2 arm64: dts: apple: Add A7 devices
f2291bedf412 dt-bindings: arm: apple: Add A11 devices
6777f8463609 dt-bindings: arm: apple: Add A10X devices
b4ff47625083 dt-bindings: arm: apple: Add A10 devices
ce790688aa46 dt-bindings: arm: apple: Add A9X devices
0472420f025e dt-bindings: arm: apple: Add A9 devices
340a25ae66bc dt-bindings: arm: apple: Add A8X devices
25411031e69f dt-bindings: arm: apple: Add A8 devices
bc22115c3571 dt-bindings: arm: apple: Add A7 devices
6018a7f4ceca dt-bindings: pinctrl: apple,pinctrl: Add A7-A11 compatibles
176a45e1572d dt-bindings: watchdog: apple,wdt: Add A7-A11 compatibles
79f0d9d12ef3 dt-bindings: arm: cpus: Add Apple A7-A11 CPU cores
bfaae9b422dd dt-bindings: mmc: Add sdhci compatible for QCS615
34d505c80e75 dt-bindings: mmc: sdhci-msm: Add SAR2130P compatible
d6f153d7cb45 dt-bindings: mmc: mtk-sd: Add mt7988 SoC
22f0ba9af4bb dt-bindings: mmc: mtk-sd: Add support for MT8196
4c1518fa641b dt-bindings: pwm: adi,axi-pwmgen: Increase #pwm-cells to 3
a1e6619cb6c6 dt-bindings: pwm: amlogic: Document C3 PWM
4e4e741cb376 arm64: dts: mt8183: Damu: add i2c2's i2c-scl-internal-delay-ns
030f50a89855 arm64: dts: mt8183: cozmo: add i2c2's i2c-scl-internal-delay-ns
94427cb3877f arm64: dts: mt8183: burnet: add i2c2's i2c-scl-internal-delay-ns
eef73802f2c2 arm64: dts: mt8183: fennel: add i2c2's i2c-scl-internal-delay-ns
abff5effb653 dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
cde5a517b243 dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: Add SM8750
b8ddbab4b1d5 arm64: dts: renesas: r9a09g057: Add OPP table
60d1484c7f80 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
ac3aa417c4d3 arm64: dts: rockchip: Add rk3588-orangepi-5b device tree
d041fe91c4a5 dt-bindings: arm: rockchip: Add Orange Pi 5b enum to Orange Pi 5 entry
911221b5def9 arm64: dts: rockchip: refactor common Orange Pi 5 board
621631b891ca arm64: dts: rockchip: Remove 'enable-active-low' from two boards
4e8ec18efa34 arm64: dts: rockchip: add HDMI support to rk3588-jaguar
77c83d44d09e arm64: dts: rockchip: add HDMI support to rk3588-tiger-haikou
adcae16b7116 arm64: dts: rockchip: add HDMI pinctrl to rk3588-tiger SoM
3e97951ad0a6 dt-bindings: riscv: Add pointer masking ISA extensions
b41aa6a575a1 ASoC: add CS42L84 codec driver
7192e70b9e3a arm64: tegra: smaug: Declare cros-ec extcon
8934d4046bdc arm64: tegra: Add SDMMC sdr104-offsets for Tegra X1
ea318ab24a38 arm64: dts: nvidia: tegra210-smaug: Add TMP451 temperature sensor node
898f0df845bd arm64: dts: nvidia: tegra210-smaug: Add touchscreen node
befe34729281 arm64: tegra: p2180: Add mandatory compatible for WiFi node
de0d275642cc arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes
144450a673fc ASoC: dt-bindings: Add CS42L84 codec
24c8f63fb336 arm64: dts: qcom: x1e80100-dell-xps13-9345: fix nvme regulator boot glitch
5a2877e8f17f arm64: dts: qcom: x1e80100-dell-xps13-9345: route edp-panel enable gpio
5fe874b7e3ee ARM: dts: qcom: ipq4019: use nvmem-layout
665e55a6885b dt-bindings: iommu: arm,smmu: Add Qualcomm SAR2130P compatible
f7103f8dbe23 ASoC: dt-bindings: allwinner: add H616 sun4i audio codec binding
85cdd8af34ad dt-bindings: perf: fsl-imx-ddr: Add i.MX91 compatible
f50caff43d6a arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
2775a2d6f7b4 arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
1df9ef3a764c arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S
092d7aa6b26a arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi R3S
451daf1e7781 arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
5500fa4c0d21 arm64: dts: rockchip: Enable HDMI0 on rock-5a
47f18a03a79a arm64: dts: rockchip: Enable HDMI0 on rk3588-nanopc-t6
309958c5385c arm64: dts: rockchip: pwm-leds for Orange Pi 5
7341cdb87808 arm64: dts: rockchip: reorder audio/hdmi nodes in Orange Pi 5
fed07cae4bda dt-bindings: clock: Add i.MX91 clock support
64f251acccf2 dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
c3a0967a0ade dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
e5866abf2fc0 dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
6013f4f7ebe6 arm64: dts: qcom: Use 'ufshc' as the node name for UFS controller nodes
7e734080860e dt-bindings: memory: fsl: Add compatible string nxp,imx9-memory-controller
1aa0676d2d4b dt-bindings: pinctrl: fsl,imx6ul-pinctrl: Convert i.MX35/5x/6 to YAML
1ee7a76a6c50 dt-bindings: soc: qcom,aoss-qmp: Add SAR2130P compatible
940defd6ddc2 dt-bindings: firmware: qcom,scm: Add SAR2130P compatible
af94817fdc9b dt-bindings: arm: qcom,ids: add SoC ID for SAR2130P and SAR1130P
4bbc500f1da4 arm64: dts: qcom: qcm6490-idp: Add UFS nodes
3434afeaf4be dt-bindings: soc: qcom: aoss-qmp: Add SM8750
cb1aae17d00a dt-bindings: arm: qcom,ids: add SoC ID for QCS615
f46702301869 arm64: dts: qcom: change labels to lower-case
9cc41c2a3917 arm64: dts: qcom: sdm: change labels to lower-case
7f90ace59631 arm64: dts: qcom: sm: change labels to lower-case
424546162d92 arm64: dts: qcom: sm8650: change labels to lower-case
5187737d5a40 arm64: dts: qcom: sm8550: change labels to lower-case
fd28693b7ec7 arm64: dts: qcom: sm8450: change labels to lower-case
a83c84ed92db arm64: dts: qcom: sm8350: change labels to lower-case
e9bdee2539b8 arm64: dts: qcom: sm8250: change labels to lower-case
f98c362c10a4 arm64: dts: qcom: sm8150: change labels to lower-case
bd4eb7f2c86e arm64: dts: qcom: sm6350: change labels to lower-case
136ffc3dabc1 arm64: dts: qcom: sm6115: change labels to lower-case
78ec42322ffe arm64: dts: qcom: sc: change labels to lower-case
7bae058d8dfe ARM: dts: qcom: change labels to lower-case
d0bf57f2868c arm64: dts: qcom: sc8280xp: change labels to lower-case
a4a1c355ae9d arm64: dts: qcom: sc7180: change labels to lower-case
0d8dff827b33 arm64: dts: qcom: msm8992-libra: drop unused regulators labels
12d665984756 arm64: dts: qcom: msm: change labels to lower-case
c3f0be5bbb93 arm64: dts: qcom: ipq: change labels to lower-case
3f59ee4054f6 arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node
009d588e0380 arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes
e9d262a12a51 ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node
d510764cf6fe ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node
a5ff6758bf1c arm64: dts: qcom: sa8775p: Add TCSR halt register space
b1d366cdfe38 arm64: dts: qcom: sa8775p-ride: add WiFi/BT nodes
45ac1e08b402 arm64: dts: qcom: sa8775p: add QCrypto nodes
066c8b7de678 Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into arm64-for-6.13
19bf5adbc0ac Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into clk-for-6.13
448c23dea476 dt-bindings: clock: qcom: Add SA8775P display clock controllers
62a4544b801a dt-bindings: clock: qcom: Add SA8775P camera clock controller
655ad47c87f6 dt-bindings: clock: qcom: Add SA8775P video clock controller
3164172f31e5 regulator: init_data handling update
b4501c58ccd3 arm64: dts: qcom: sm7325: Add device-tree for Nothing Phone 1
6690dd9829c2 dt-bindings: arm: qcom: Add SM7325 Nothing Phone 1
a0e6a2b73511 dt-bindings: vendor-prefixes: Add Nothing Technology Limited
166a45c90a81 arm64: dts: qcom: Add SM7325 device tree
c0f8f7275e0e dt-bindings: arm: cpus: Add qcom kryo670 compatible
5a5f297992a8 arm64: dts: qcom: sa8775p: Add GPI configuration
48e01bb5863b regulator: dt-bindings: qcom,qca6390-pmu: add more properties for wcn6855
fc22539a553f regulator: dt-bindings: lltc,ltc3676: convert to YAML
9fd1b7244de8 dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL
2d6147baff0c dt-bindings: mmc: Document support for partition table in mmc-card
6966ae169e9c arm64: dts: rockchip: analog audio on Orange Pi 5
54d1879aeb79 arm64: dts: rockchip: Add dtsi file for RK3399S SoC variant
d31105e3a752 arm64: dts: rockchip: Convert dts files used as parents to dtsi files
a198185b9b55 arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
cf9235a8b9cf arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
cefc739ed7fd dt-bindings: arm: rockchip: Add FriendlyARM NanoPi R3S
22c62b410a76 arm64: dts: rockchip: Enable HDMI0 on Orange Pi 5
309d3c431657 arm64: dts: rockchip: add and enable gpu node for Radxa ROCK 5A
08d6b7cea0b0 arm64: dts: rockchip: Enable HDMI0 on orangepi-5-plus
6c98a7bb55d5 arm64: dts: rockchip: Enable HDMI0 on rk3588-evb1
7c442cba59d1 arm64: dts: rockchip: Enable HDMI0 on rock-5b
a839348380c2 arm64: dts: rockchip: Add HDMI0 node to rk3588
5bfa747aa6cc arm64: dts: rockchip: Add Radxa e20c board
6f220d3a1243 arm64: dts: rockchip: Add base DT for rk3528 SoC
02c7df878deb dt-bindings: arm: rockchip: Add Radxa E20C board
844b572cc629 arm64: dts: rockchip: Add rk3576-armsom-sige5 board
e472bbb96d8d arm64: dts: rockchip: Add rk3576 SoC base DT
39f0871081fe dt-bindings: arm: rockchip: Add ArmSoM Sige 5
83489bf1ecfb arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk356x
39eaee8ff5dd arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk3399
6da1af61e5d0 arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk3368
6638fa4733b1 arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from rk3328
320af665b061 arm64: dts: rockchip: Drop rockchip prefix of s-p-c PMIC prop from px30
94c457e83260 ASoC: dt-bindings: qcom: Add SM8750 LPASS macro codecs
3e3c77d7ec1a dt-bindings: pinctrl : qcom: document SAR2130P TLMM
4fa57881d207 dt-bindings: pinctrl: describe qcs8300-tlmm
db77b8421e31 ASoC: dt-bindings: everest,es8328: Document audio graph port
db78cbd4db87 dt-bindings: power: Add binding for MediaTek MT6735 power controller
12a5b0df8288 dt-bindings: power: rpmpd: Add SAR2130P compatible
155d58a9a5ea dt-bindings: interconnect: qcom-bwmon: Document QCS8300 bwmon compatibles
2d1656d763ba dt-bindings: interconnect: qcom: document SAR2130P NoC
fe75fe7f8010 dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path
143cdfb176c5 dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS615 SoC
c7dbf07a745f dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS8300 SoC
cc849602f015 arm64: dts: imx8qxp-mek: add cm4 and related nodes
5c260f3d0e7d arm64: dts: imx8qxp-mek: add usbotg1 and related node
a3454d3d7fa5 arm64: dts: imx8qxp-mek: add flexcan1 and flexcan2
02a69f98c668 arm64: dts: imx8qxp-mek: enable jpeg encode and decode
17e2c887c738 arm64: dts: imx8qxp-mek: add esai, cs42888 and related node
adda0b1a447a arm64: dts: imx8qxp-mek: add bluetooth audio codec
bb041d03e14f dt-bindings: at24: add ST M24256E Additional Write lockable page support
c52e0b44f52d ARM: dts: imx6sll: fix anatop thermal dtbs_check warnings
0ad8c197e84e arm64: dts: imx8m*-venice-gw75xx: add Accelerometer device
f3e374f020bd arm64: dts: imx8qm-mek: Add PCIe and SATA
ae0cdc268451 arm64: dts: imx8qxp-mek: Add PCIe support
0dfe113f6196 arm64: dts: imx8dxl-evk: Add PCIe support
1f04693e298f arm64: dts: imx8-ss-hsio: Add PCIe and SATA support
0b1f674ef893 arm64: dts: colibri-imx8x: Fix typo "rewritting"
ed688466bd31 arm64: dts: imx93-9x9-qsb: Add PDM microphone sound card support
5581f5e11eae arm64: dts: imx93-9x9-qsb: add bt-sco sound card support
dbdd22ddfac2 arm64: dts: imx93-9x9-qsb: Enable sound-wm8962 sound card
d3e21971c3b5 ARM: dts: imx6dl: Add support for i.MX6DL DHCOM SoM on PDK2 carrier board
b11b5832eb54 dt-bindings: arm: fsl: Document i.MX6DL DHCOM SoM on PDK2 carrier board
3036f98efd20 riscv: sophgo: dts: add power key for pioneer box
382306fd81b9 ARM: dts: imx6qdl-dhcom-pdk2: Fill in missing panel power-supply
df4f89b32581 ARM: dts: imx6qdl-dhcom-pdk2: Drop incorrect size-cells in GPIO keys
9b1b00bff3b1 ARM: dts: imx6qdl-dhcom-som: Drop bogus regulator-suspend-mem-microvolt
177785b48e6b arm64: dts: imx95-19x19-evk: add lpi2c[5,6] and sub-nodes
6912c8892abb arm64: dts: imx95-19x19-evk: add nxp,ctrl-ids property
ff37f6cca13c arm64: dts: imx95: enable A55 cpuidle
6fba8c16af61 arm64: dts: imx95: add anamix temperature thermal zone and cooling node
51124be16359 arm64: dts: imx95: update a55 thermal trip points
4d2b2f1d0695 arm64: dts: imx95: add bbm/misc/syspower scmi nodes
fbfc377ba7a8 arm64: dts: imx95: set max-rx-timeout-ms
0c5a7fb42610 ARM: dts: imx7-colibri: Update audio card name
06df2ef8a492 ARM: dts: imx6qdl-colibri: Update audio card name
06a6941c0f78 ARM: dts: imx6qdl-apalis: Update audio card name
2b4ed3fd4960 arm64: dts: imx8mm-kontron: Add DL (Display-Line) overlay with LVDS support
09d68d473bf6 arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM
c7bd4069275a riscv: dts: sophgo: Add SARADC description for Sophgo CV1800B
f197a8728a5f riscv: dts: sophgo: Add LicheeRV Nano board device tree
b4f7d900d99a riscv: dts: sophgo: Add initial SG2002 SoC device tree
05309c2c85c7 Realtek SPI-NAND controller
734f739458e7 dt-bindings: phy: sparx5: document lan969x
92a719586c26 dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant
85d7821330e4 dt-bindings: iio: adc: add ad7779 doc
219811555bd9 dt-bindings: iio: adc: ad7606: Add iio backend bindings
746f361d888c dt-bindings: iio: adc: ad7606: Remove spi-cpha from required
7bb5b0ef1349 dt-bindings: iio: pressure: bmp085: Add interrupts for BMP3xx and BMP5xx devices
0900965dffb4 dt-bindings: iio: imu: smi240: add Bosch smi240
50057515bdfa dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300
e438761375e2 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible
84892869e473 dt-bindings: dma: sifive pdma: Add PIC64GX to compatibles
eb53a9f1aad0 dt-bindings: dma: stm32-dma3: prevent additional transfers
db5d78da359b dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode
01a6a247a537 dt-bindings: dma: qcom,gpi: Add SAR2130P compatible
d3c8498b6a47 dt-bindings: soc: rockchip: add rk3576 usb2phy syscon
3c7b4436a3ef dt-bindings: soc: rockchip: add rk3576 vo1-grf syscon
716b379a0e4e arm64: dts: mediatek: mt8186-corsola: Fix GPU supply coupling max-spread
a1bdc8d588cf arm64: dts: mediatek: mt8195-cherry: Use correct audio codec DAI
7b256ed28e8b arm64: dts: mediatek: mt8188: Fix USB3 PHY port default status
e2809c3e4393 arm64: dts: mediatek: mt8173-elm-hana: Add vdd-supply to second source trackpad
a93b20e4e56c arm64: dts: mediatek: mt8186-corsola-voltorb: Merge speaker codec nodes
c5a57299769e dt-bindings: soc: mediatek: Add DVFSRC bindings for MT8183 and MT8195
a18fd2bcdfce arm64: dts: mediatek: mt8390-genio-700-evk: Enable ethernet
d9d3b66f2926 arm64: dts: mediatek: mt8188: Add ethernet node
6c459245f516 arm64: tegra: Create SKU8 AGX Orin board file
0e227df92387 dt-bindings: arm: Tegra234 Industrial Module
6e567b53df79 dt-bindings: display: bridge: sil,sii9022: Add bus-width
31a6dad2157f dt-bindings: display: bridge: tc358768: switch to bus-width
e52b8f328e65 dt-bindings: display: mediatek: Add OF graph support for board path
a5b8bc18db9d spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi
fcb56ba369e5 dt-bindings: spi: Add realtek,rtl9301-snand
3b3e464afa21 ARM: dts: Reconfigure the MC2 eMMC interface
a9ef1eb7ced8 ARM: dts: ux500: Add touchkeys to Codinas
ea8b05f87b2e dt-bindings: display/msm: Document the DPU for SA8775P
dd02bc215d76 dt-bindings: display/msm: Document MDSS on SA8775P
37d89b0da653 dt-bindings: display/msm: merge SM8550 DPU into SC7280
7901f24ee5fd dt-bindings: display/msm: merge SM8450 DPU into SC7280
ecfbf7ca3ff2 dt-bindings: display/msm: merge SM8350 DPU into SC7280
c23d5cbb9118 dt-bindings: display/msm: merge SM8250 DPU into SM8150
9f2c304f24e6 dt-bindings: display/msm: merge SC8280XP DPU into SC7280
7b235a5fe2b6 dt-bindings: display: msm: dp-controller: document SA8775P compatible
ec37fc180ec1 arm64: dts: layerscape: remove cooling-max-state and cooling-min-state
b2a0c2f4cdaf ARM: dts: imx6qdl-dhcom: Fix model typo for i.MX6 DHSOM
11747d9128af arm64: dts: imx8mp: add cpuidle state "cpu-pd-wait"
61c72c95b163 ARM: dts: imx6qdl-tx6: Fix 'fixed-clock' description
561a8b0f511b ARM: dts: imx6qdl-tx6: Remove 'turn-on-delay-ms'
a3da9407fea4 arm64: dts: imx8mp-evk: add PCIe Endpoint function overlay file
3ff668119d88 dt-bindings: input: mediatek,pmic-keys: Add compatible for MT6359 keys
e835158c65f4 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
6cc32685e36f Merge 6.12-rc4 into usb-next
745c9a7e2695 Merge 6.12-rc4 into tty-next
b73d66e9e6f9 Merge 6.12-rc4 into char-misc-next
97079da3b2c4 arm64: dts: ti: k3-am64: Add ti,pa-stats property
ddeec60183dd arm64: dts: ti: k3-am64-main: Add ti,pruss-pa-st node
7ab873810d8e arm64: dts: ti: k3-am654-icssg2: Add ti,pa-stats property
cac55bdc6b45 arm64: dts: ti: k3-am65-main: Add ti,pruss-pa-st node
aea8579d9280 arm64: dts: ti: k3-am62a7-phyboard-lyra-rdk: Update ethernet internal delay
a62ec33e597a arm64: dts: ti: k3-am62x-phyboard-lyra: Drop unnecessary McASP AFIFOs
b31d5fc38d27 arm64: dts: ti: k3-am64x-sk: Enable eQEP
572891e2ea8b arm64: dts: ti: k3-am64-main: Add eQEP nodes
a278dcec62b7 arm64: dts: ti: k3-am62p-main: Add eQEP nodes
5d37c1118395 arm64: dts: ti: k3-am62a-main: Add eQEP nodes
5e8af74c8ba7 arm64: dts: ti: k3-am62-main: Add eQEP nodes
17e308cc0b97 arm64: dts: ti: k3-am642-evm: Add M4F remoteproc node
8e4ca5fe2c46 arm64: dts: ti: k3-am642-sk: Add M4F remoteproc node
8fc6f5415c54 arm64: dts: ti: k3-am64: Add M4F remoteproc node
50abc117a20d arm64: dts: ti: k3-am625-sk: Add M4F remoteproc node
48e8505beee9 arm64: dts: ti: k3-am62: Add M4F remoteproc node
0309d6086f00 Revert "arm64: dts: ti: am62-phyboard-lyra: Add overlay to increase cpu frequency to 1.4 GHz"
f434f5970ce1 arm64: dts: ti: am62-phycore-som: Increase cpu frequency to 1.4 GHz
3063860fde37 Merge tag 'renesas-pinctrl-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
ceb22b29c581 dt-bindings: pinctrl: spacemit: add support for K1 SoC
22ccb431ff16 dt-bindings: display: panel-simple: Document support for Microchip AC69T88A
2ecb2de40a66 dt-bindings: clock: ti: Convert divider.txt to json-schema
6de19d8f0ff4 dt-bindings: clock: ti: Convert interface.txt to json-schema
eb274205dc9f dt-bindings: imx-rng: Allow passing only "fsl,imx31-rnga"
6215e0dd208e dt-bindings: display: Add Sharp Memory LCD bindings
4497ec169a33 dt-bindings: gpio-mmio: Add ngpios property
0fa8dc3b05bb arm64: dts: fsl-lx2160a: add rev2 support
9405a41d0c9e arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM PicoITX
a18f1526ea4f dt-bindings: arm: fsl: Document DH electronics i.MX8M Plus DHCOM PicoITX
a40b650b9c6c arm64: dts: imx8mp-phyboard-pollux-rdk: update gpio-line-names
efe0961bcc0d arm64: dts: imx8mp: Add DH i.MX8MP DHCOM SoM on DRC02 carrier board
4067f5c56da6 dt-bindings: arm: fsl: Document DH i.MX8MP DHCOM SoM on DRC02 carrier board
dca2a70961bd dt-bindings: reset: npcm: add clock properties
7cbf7b89f442 dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC
4f112cd1aebd dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings
5fffc63d2ac3 dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes
72170e5b5797 Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings"
3995b2076704 dt-bindings: wireless: wilc1000: Document WILC3000 compatible string
4f86698e3e4f dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561
954430d0eac8 dt-bindings: phy: add NXP PTN3222 eUSB2 to USB2 redriver
bf20defea7b3 dt-bindings: phy: mxs-usb-phy: add imx8qxp compatible
f836468e82c9 dt-bindings: phy: rk3228-hdmi-phy: convert to yaml
d4931423cede spi: dt-bindings: brcm,bcm2835-aux-spi: Convert to dtschema
9e084dc5e189 dt-bindings: phy: mediatek: tphy: add a property for power-domains
b2a6f3584847 dt-bindings: phy: Add eDP PHY compatible for sa8775p
40b48a871c03 dt-bindings: phy: rockchip-usbdp: add rk3576
9cad4b12d670 dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX Controller
d1b1c09ad1dc dt-bindings: phy: rockchip,inno-usb2phy: add rk3576
4decea3b16e6 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8
cd2ee82322fa dt-bindings: phy: Add QMP UFS PHY comptible for QCS615
b3be38224e6a dt-bindings: phy: describe the Qualcomm SGMII PHY
5b6622add587 ASoC: Merge up fixes
9e8eedb5aca9 arm64: dts: imx: Add imx8mp-iota2-lumpy board
001e26a4496f dt-bindings: arm: Add i.MX8MP IOTA2 Lumpy board
9cdd6ca350d1 arm64: dts: freescale: imx8mp-verdin: Add Ivy carrier board
bcf5eb264359 arm64: dts: freescale: imx8mp-verdin: add labels to som nodes
7a813c060658 dt-bindings: arm: freescale: Add verdin imx8mp ivy board
9a4d53bcb000 dt-bindings: arm: freescale: Add verdin imx8mm ivy board
babe9c9bc350 arm64: dts: freescale: imx8mm-verdin: Add Ivy carrier board
7fe5efbbfc73 arm64: dts: freescale: imx8mm-verdin: add label to som adc node
439c1b519a0a arm64: dts: imx8mp-phyboard-pollux-rdk: add gpio-fan
d3a155830740 ARM: dts: amlogic: meson8/8b: remove invalid pinctrl reg
70dfe5f6b6d7 arm64: dts: exynos: Add initial support for Samsung Galaxy Note20 5G (c1s)
1fb33fff8bdf arm64: dts: exynos: Add initial support for the Exynos 990 SoC
54c9c140f62f dt-bindings: arm: samsung: samsung-boards: Add bindings for Exynos 990 boards
9380c4ca2ed5 dt-bindings: arm: cpus: Add Samsung Mongoose M5
875a598c29c8 dt-bindings: hwinfo: exynos-chipid: Add compatible for Exynos 990 chipid
3b8da126b7d6 dt-bindings: pinctrl: samsung: Add exynos990-wakeup-eint compatible
d05da361a158 dt-bindings: pinctrl: samsung: Add exynos990-pinctrl compatible
e6ad38f15ef1 dt-bindings: usb: add rk3576 compatible to rockchip,dwc3
172cff4b0fe5 dt-bindings: power/supply: qcom,pmi8998-charger: Drop incorrect "#interrupt-cells" from example
f608622a4c61 arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region
7605dbdc0eb3 dt-bindings: reset: syscon-reboot: Add reg property
c8f503143d90 dt-bindings: power: supply: Add TI TWL603X charger
2e03d81a95fe arm64: dts: qcom: x1e80100: rename vph-pwr regulator nodes
3b3a1e7fc62e arm64: dts: mediatek: mt8188: Add eDP and DP TX nodes
e4257c23f0e0 arm64: dts: mediatek: mt8188: Add DP-INTF nodes
9a5bd28490fd arm64: dts: mediatek: mt8188: Add display nodes for vdosys1
ea1c3e87fddb arm64: dts: mediatek: mt8188: Add display nodes for vdosys0
1042ce37df70 arm64: dts: mediatek: mt8188: Add JPEG decoder and encoder nodes
422075bb8edd arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes
1c67a339a469 arm64: dts: mediatek: mt8188: Add MIPI DSI nodes
13d97b6e2d15 arm64: dts: mediatek: mt8188: Add PCIe nodes
bb8ed945f116 arm64: dts: mediatek: mt8188: Assign GCE aliases
28e7afea2b36 arm64: dts: mediatek: mt8390-genio-700-evk: add keys and USB HUB
3afc934beaf9 arm64: dts: mediatek: mt8390-genio-700-evk: update regulator names
98405216faa7 arm64: dts: mediatek: mt8390-genio-700-evk: enable pcie
e1e0053cf4dd arm64: dts: mt8183: kukui: Fix the address of eeprom at i2c4
8a4fb1889563 arm64: dts: mt8183: krane: Fix the address of eeprom at i2c4
1d315aee39e4 arm64: dts: mediatek: mt7988: add efuse block
f2fbf857fb76 arm64: dts: mediatek: mt7988: add UART controllers
b210c250e291 arm64: dts: mt8183: Add encoder node
49b0cdb0196e arm64: dts: mediatek: mt8395-genio-1200-evk: Enable GPU
0d6269b04bd8 arm64: dts: mediatek: mt8188: Add socinfo nodes
0bd19540e3c1 arm64: dts: mediatek: mt8188: Add audio support
40f680fa96e6 ARM: dts: nxp: imx6ull: add dma support for uart8
026fba088d6c ARM: dts: nxp: imx6ul: add dma support for all uarts
22403370729e dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add support for QCS615
1b46afcf7db2 dt-bindings: phy: qcom,qusb2: Add bindings for QCS615
0e32ff673a5a ARM: dts: imx6q-lxr: Add board support
08e95b0325e7 dt-bindings: arm: fsl: Document the Comvetia LXR board
26ce50e7d8b2 dt-bindings: vendor-prefixes: Add an entry for ComVetia AG
00c30e415792 dt-bindings: display: panel: Add Samsung AMS581VF01
927f00825fba dt-bindings: mfd: mediatek: mt6397: Add ADC, CODEC and Regulators for MT6359
c4a0a08b93f2 dt-bindings: mfd: mediatek: mt6397: Add start-year property to RTC
bd1251bec9e4 dt-bindings: mfd: Convert zii,rave-sp.txt to yaml format
c658eb03f5ec dt-bindings: mfd: twl: Add charger node also for TWL603x
9c6b9e05ec76 dt-bindings: mfd: syscon: Document the non simple-mfd syscon on PolarFire SoC
90d7e910eb9f dt-bindings: mfd: Add support for the samsung,s2dos05
87d6133346a0 dt-bindings: mfd: qcom,tcsr: Add compatible for qcs615
f7d8e2a8fa7f dt-bindings: mfd: qcom,tcsr: Add compatible for QCS8300
34d22c52efc5 dt-bindings: mfd: qcom,tcsr: Document support for SA8255p
31e89d05e127 dt-bindings: mfd: mediatek: mt6397: Convert to DT schema format
9548ef611f9a arm64: dts: colibri-imx8x: Add ad7879_ts label to touchscreen controller
4801934a1531 dt-bindings: media: Add bindings for raspberrypi,rp1-cfe
0a4f497ae4ee dt-bindings: media: renesas,isp: Add binding for V4M
91d41465acda dt-bindings: media: renesas,isp: Add Gen4 family fallback
c2e69b242813 dt-bindings: i2c: maxim,max96712: Add compatible for MAX96724
1c90953be33b dt-bindings: media: renesas,csi2: Add binding for V4M
68bd2cb51490 arm64: dts: imx8mm-venice-*: add RTC aliases
5e5a7e406f64 arm64: dts: imx93-9x9-qsb: add I3C overlay file
0c66bf12b173 dt-bindings: pinctrl: samsung: Add missing constraint for Exynos8895 interrupts
13b53cabe1fa dt-bindings: pinctrl: samsung: Fix interrupt constraint for variants with fallbacks
171713151ac8 arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration
3234e35dd74b arm64: dts: freescale: minor whitespace cleanup
29ef9ee273ac arm64: dts: Add support for Kontron i.MX8MP SMARC module and eval carrier
966e25fa019d arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board
669e05743d3b dt-bindings: arm: fsl: Add Kontron i.MX8MP OSM-S based boards
8e60288ef257 arm64: dts: imx93-11x11-evk: Enable sound-wm8962 sound card
f7899e2eb04d arm64: dts: imx93-11x11-evk: add flexcan support
0c059ea2b317 arm64: dts: imx93-11x11-evk: add io-expander adi,adp5585-01
27a12bb96f4a arm64: dts: imx93-11x11-evk: remove redundant "sleep" pinctrl in lpi2c2 node
ce488aac6011 dt-bindings: clocks: add binding for gated-fixed-clocks
a52fb79b0ede arm64: dts: renesas: r9a09g057: Add ICU node
c70b39c7804c dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller
6b2ee6f97f03 dt-bindings: iio: light: veml6030: add veml7700
809b7c6f70ab riscv: dts: thead: remove enabled property for spi0
6b7745f477d0 riscv: dts: thead: Add missing GPIO clock-names
90e90f2cfc80 riscv: dtb: thead: Add BeagleV Ahead LEDs
844db5464ff5 riscv: dts: thead: Add TH1520 pinctrl settings for UART0
36270053083a riscv: dts: thead: Add Lichee Pi 4M GPIO line names
73fb6b2c50d6 riscv: dts: thead: Adjust TH1520 GPIO labels
339c9346dc4a riscv: dts: thead: Add TH1520 GPIO ranges
fc28f97249d5 riscv: dts: thead: Add TH1520 pin control nodes
d15a1d47fc59 dt-bindings: vendor-prefixes: add spacemit
16c7c623dee2 dt-bindings: backlight: Convert zii,rave-sp-backlight.txt to yaml
d42ad23dcba4 dt-bindings: leds: Add 'active-high' property
52c7513233d2 dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property
786b481a9829 arm64: dts: imx8mm-emtop-baseboard: Add Peripherals Support
b71ca16e750e arm64: dts: imx8-apalis: Add usb4 host support
2394fd72d428 arm64: dts: imx8-apalis: Add nau8822 audio-codec to apalis eval v1.2
e3c292d1f737 arm64: dts: imx8-apalis: Add audio support
c96165670fbd arm64: dts: imx8-apalis: Set thermal thresholds
1db463a2e954 arm64: dts: imx8qm: Remove adma pwm
c035becefc62 arm64: dts: qcom: sa8775p: extend the register range for UFS ICE
7ff7071f9f43 arm64: dts: qcom: sm8550: extend the register range for UFS ICE
889c773c3f84 arm64: dts: qcom: sm8650: extend the register range for UFS ICE
555a22db63da arm64: dts: qcom: sa8775p: Populate additional UART DT nodes
b21f6a0e8035 arm64: dts: qcom: x1e80100-t14s: add another trackpad support
c6d16d152204 arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345
bcddc55313a4 dt-bindings: arm: qcom: Add Dell XPS 13 9345
75acf9f43361 arm64: dts: qcom: x1e78100-t14s: enable otg on usb-c ports
4ce3cb7331f1 arm64: dts: qcom: x1e80100-crd: enable otg on usb ports
3d1e606e47ea arm64: dts: qcom: x1e80100: enable OTG on USB-C controllers
b9303b525b4b arm64: dts: qcom: x1e80100-vivobook-s15: Drop orientation-switch from USB SS[0-1] QMP PHYs
c51166f8ad48 arm64: dts: qcom: x1e80100-slim7x: Drop orientation-switch from USB SS[0-1] QMP PHYs
37e90c03b449 arm64: dts: qcom: Drop undocumented domain "idle-state-name"
aeb29cc23669 arm64: dts: qcom: sc7280: Add 0x81 Adreno speed bin
3c5b615079b4 arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe
f9ab469e781d dt-bindings: dma: rz-dmac: Document RZ/A1H SoC
423821e8b5cf dt-bindings: rtc: mpfs-rtc: Properly name file
8c9723a68cf6 dt-bindings: mmc: sdhci-msm: Document the X1E80100 SDHCI Controller
1d51903da4ef dt-bindings: mmc: sdhci-msm: add IPQ5424 compatible
20e9a1c8d97c dt-bindings: mmc: cdns,sdhci: ref sdhci-common.yaml
70c9390cfaa7 dt-bindings: mmc: cdns: document Microchip PIC64GX MMC/SDHCI controller
ca5d807bbbdf ARM: dts: rockchip: Add Relfor Saib board
38159d2940cf dt-bindings: arm: rockchip: Add Relfor Saib board
c7f8baab2a0c dt-bindings: vendor-prefixes: Add Relfor labs
46ba63fe482f ARM: dts: rockchip: Add watchdog node for RV1126
1e35f91de25d dt-bindings: watchdog: rockchip: Add rockchip,rv1126-wdt string
5c092b1d7063 arm64: dts: renesas: rzg3s-smarc: Use interrupts-extended for gpio-keys
b1ff59620ae1 arm64: dts: renesas: beacon-renesom: Use interrupts-extended for touchscreen
3434d2b8e224 arm64: dts: renesas: Use interrupts-extended for WLAN
224f6a584251 arm64: dts: renesas: Use interrupts-extended for video decoders
4cde4936ee89 arm64: dts: renesas: Use interrupts-extended for USB muxes
21837e846ca6 arm64: dts: renesas: Use interrupts-extended for PMICs
08ab7120e63b arm64: dts: renesas: Use interrupts-extended for I/O expanders
80b32a671718 arm64: dts: renesas: Use interrupts-extended for HDMI bridges
8c17f11e2b8a arm64: dts: renesas: Use interrupts-extended for Ethernet PHYs
561722cb17bb arm64: dts: renesas: Use interrupts-extended for DisplayPort bridges
aa4687349f31 ARM: dts: renesas: kzm9g: Use interrupts-extended for sensors
65b548334a98 ARM: dts: renesas: kzm9g: Use interrupts-extended for I/O expander
276f27402851 ARM: dts: renesas: r8a7742-iwg21m: Use interrupts-extended for RTC
a4e199acde95 ARM: dts: renesas: iwg22d-sodimm: Use interrupts-extended for port expander
87a105b8df5c ARM: dts: renesas: Use interrupts-extended for video decoders
3a7481a6911d ARM: dts: renesas: Use interrupts-extended for touchpanels
007b9bf3c590 ARM: dts: renesas: Use interrupts-extended for PMICs
ec9235ef00d3 ARM: dts: renesas: Use interrupts-extended for HDMI bridges
34f3321ec6df ARM: dts: renesas: Use interrupts-extended for Ethernet PHYs
2ad74334f74f ARM: dts: renesas: Use interrupts-extended for Ethernet MACs
25c3332c9796 dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700
93d9a41cf53a Merge tag 'v6.12-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
6800013270c4 Merge 6.12-rc3 into usb-next
ae776265ffc9 dt-bindings: clock: add support for lan969x
e1975abaca46 ARM: dts: microchip: Rename LED sub nodes name
8f0592fd90d9 ARM: dts: microchip: Rename the pmic node
19694a10b460 ARM: dts: microchip: Rename the eeprom nodename
803e741b26b4 ARM: dts: microchip: sama7g5ek: Add power monitor support
369739ce16a1 ARM: dts: microchip: sama7g54_curiosity: Add power monitor support
9db788660aa1 ARM: dts: microchip: sama5d2_icp: Add power monitor support
c904ffbc3092 ARM: dts: microchip: sam9x60ek: Add power monitor support
b7f7646bf617 ARM: dts: microchip: Unify rng node names
7bcf27db3e0e ARM: dts: microchip: Add trng labels for all at91 SoCs
d349c4f85ddc ARM: dts: microchip: sam9x60: Add missing property atmel,usart-mode
1572a7cd3baf dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x7 compatible
82fd17cf9cca arm64: dts: ti: Add support for J742S2 EVM board
3fbb4e71ee4a arm64: dts: ti: Introduce J742S2 SoC family
9200229331e7 dt-bindings: arm: ti: Add bindings for J742S2 SoCs and Boards
5ad7086348b1 arm64: dts: ti: Refactor J784s4-evm to a common file
61116717b2c8 arm64: dts: ti: Refactor J784s4 SoC files to a common file
081c45d86c97 dt-bindings: media: ti,j721e-csi2rx-shim: Update maintainer email
e97c92a1288d dt-bindings: iio: adc: add AD762x/AD796x ADCs
bb8c9c2a684f Merge tag 'v6.12-rc2' into test2
d4a1153e08d3 dt-bindings: net: emaclite: Add clock support
2d4c608b14c2 dt-bindings: rtc: mpfs-rtc: Add PIC64GX compatibility
82fb791a0b4f dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add QCS8300 compatible
a006ae08f18c dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QCS8300
2a47837a6a43 dt-bindings: usb: qcom,dwc3: Add QCS8300 to USB DWC3 bindings
e8276f3d76ac dt-bindings: leds: bcm63138: Add shift register bits
1c98277621a1 dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RK3528
4591ac9bf944 dt-bindings: serial: snps-dw-apb-uart: Add Rockchip RK3576
0c0550d3439e dt-bindings: serial: rs485: Fix rs485-rts-delay property
bc03157c4989 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1552fc04c8e3 Merge tag 'drm-misc-next-2024-10-09' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
7641349eb174 arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes
d9318718df7e Merge branch 'for-v6.13/clk-dt-bindings' into next/dt64
045dbca8dfe9 Merge branch 'for-v6.13/clk-dt-bindings' into next/clk
c6057e9c7a9e dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
49395d036a58 dt-bindings: leds: Document "rc-feedback" trigger
68abe5c0bbec dt-bindings: clock: xilinx: describe whether dynamic reconfig is enabled
4ce301971c64 ASoC: dt-bindings: Add Loongson I2S controller
871ccd03f57e ASoC: dt-bindings: Add NXP uda1342 Codec
e2c119138d31 ASoC: dt-bindings: Add Everest ES8323 Codec
e7152c3acca2 arm64: dts: renesas: r8a779h0: Add OTP_MEM node
65a521f35063 arm64: dts: renesas: r8a779g0: Add OTP_MEM node
04cdb59fe3ff arm64: dts: renesas: r8a779f0: Add E-FUSE node
4195489a94de arm64: dts: renesas: r8a779a0: Add E-FUSE node
1113149692ef arm64: dts: renesas: beacon: Add SD/OE pin properties
58ef1410262d arm64: dts: renesas: hihope: Add SD/OE pin properties
5e1e0dfe606a arm64: dts: renesas: salvator-x: Add SD/OE pin properties
2f6df7189b2d arm64: dts: renesas: ulcb: Add SD/OE pin properties
9fca3436586b arm64: dts: renesas: salvator-xs: Add SD/OE pin properties
5412125ac591 ARM: dts: renesas: genmai: Enable MMCIF
c3e40a9b9efb ARM: dts: renesas: genmai: Enable SDHI0
dccdee817ccc arm64: dts: renesas: rz{g2l,g2lc}-smarc-som: Update partition table for spi-nor flash
78a979f6cfd9 arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash
348e61ec8d0d dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties
edcb99a82f7e Merge wireless-next into staging-next
a71be37b5de8 arm64: dts: amlogic: Add Amlogic C3 PWM
200722693564 dt-bindings: display: panel: Add Samsung AMS639RQ08
043a4e837c78 dt-bindings: panel: add Samsung s6e3ha8
282c7dde11e3 dt-bindings: display: panel-lvds: Add compatible for Jenson BL-JT60050-01A
99d670ed3553 dt-bindings: vendor-prefixes: Add Jenson Display
259161dcea8e Merge net-next/main to resolve conflicts
e693d5afac4a Merge tag 'drm-misc-next-2024-09-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
2955a2febba6 dt-bindings: net: marvell,aquantia: add property to override MDI_CFG
c3f883a9e9bf Merge tag 'drm-misc-next-2024-09-20' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
b0a2a71ee7b7 dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
a5b48af0bb34 arm64: rockchip: add clocks property to cru node rk3328
95f747b4f658 arm64: dts: rockchip: fix compatible string rk3328 cru node
8378a03b73ae dt-bindings: writing-schema: Add details on YAML text blocks
2a556c7c3f8a regulator: dt-bindings: vctrl-regulator: convert to YAML
09d320f523bf dt-bindings: net: fec: add pps channel property
9d2430d75454 ARM: dts: imx7ulp: add "nxp,sim" property for usbphy1
b6098914fba3 arm64: dts: s32g2: Disable support for SD/eMMC UHS mode
e25af93c7f88 arm64: dts: s32g: Add S32G2/S32G3 uSDHC pinmux
1fe5abb81f67 ARM: dts: imx28-apx4devkit: Fix the rtc compatible
ca76f55fc4ff dt-bindings: net: ethernet-phy: Add timing-role role property for ethernet PHYs
420663585109 ARM: dts: imx6qdl-mba6: Add reserved memory area for CMA memory
7f8a95299bd0 arm64: dts: imx8mm: Add dbi2 and atu reg for i.MX8MM PCIe EP
44e6d98d4cc6 arm64: dts: imx8mp: Add dbi2 and atu reg for i.MX8MP PCIe EP
a2021b75e127 arm64: dts: imx8mq: Add dbi2 and atu reg for i.MX8MQ PCIe EP
dc211561776b dt-bindings: net: realtek: Use proper node names
cd6d97f59761 arm64: dts: qcom: qcs6490-rb3gen2: Enable PWR/VOL keys
ebbe6a9c33fe arm64: dts: qcom: qcs6490-rb3gen2: Specify i2c1 clock frequency
5a588983eab1 ASoC: dt-bindings: rockchip,rk3036-codec: convert to yaml
2b7c81f060b6 ASoC: Merge up v6.12
d820555c1f28 spi: Merge up v6.12
f650903e3b7f ARM: dts: renesas: rcar-gen2: Switch HS-USB to renesas,enable-gpios
39bee53dfd9e ARM: dts: renesas: r7s72100: 'bus-width' is a board property
eb9f07d9e4f4 arm64: dts: renesas: beacon-renesom: Switch to mic-det-gpios
9e4ebc4803d2 ARM: dts: renesas: Use proper node names for keys
bb139ec6c060 ARM: dts: renesas: r8a7778: Rename 'bsc' to 'lbsc'
b8e0085e6650 ARM: dts: renesas: Add proper node names to (L)BSC devices
f71cb63ecb03 dt-bindings: phy: cadence-sierra: Allow PHY types QSGMII and SGMII
a1a280e3c562 dt-bindings: phy: Add STM32MP25 COMBOPHY bindings
1cce969a3069 arm64: dts: qcom: sda660-ifc6560: enable mDSP and WiFi devices
385f3a706daf arm64: dts: qcom: sdm630: add WiFI device node
ba24d1324aa0 arm64: dts: qcom: sdm630: enable A2NOC and LPASS SMMU
b4f0cdb93361 arm64: dts: qcom: sda660-ifc6560: fix l10a voltage ranges
08516c3836c6 arm64: dts: qcom: sda660-ifc6560: enable GPU
ef67aa0a21f7 arm64: dts: qcom: sdm630: enable GPU SMMU and GPUCC
981d78b61dce dt-bindings: iio: light: veml6030: add veml6035
e0d7b63c359e dt-bindings: iio: light: veml6030: add vdd-supply property
659a221815d7 dt-bindings: iio: dac: ad3552r: fix maximum spi speed
89bd84e00d20 dt-bindings: iio: imu: migrate InvenSense email to TDK group domain
9f2f8b13c6ec dt-bindings: iio: adc: Add the GE HealthCare PMC ADC
332a4726d46d dt-bindings: vendor-prefixes: Add an entry for GE HealthCare
7d0dcec5cf2b arm64: dts: qcom: qcm6490-fairphone-fp5: Add thermistor for UFS/RAM
9faee8d13bbb arm64: dts: qcom: sm6350: Fix GPU frequencies missing on some speedbins
59021fcbaea7 arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5G
f941eb9e840d arm64: dts: qcom: sc8280xp: Add uart18
58766bb02b1a dt-bindings: arm: qcom: Document Microsoft Surface Pro 9 5G
d2a8bd12a58a arm64: dts: qcom: minor whitespace cleanup
650341209ce1 arm64: dts: qcom: drop underscore in node names
87dafc2af9bf ARM: dts: qcom: minor whitespace cleanup
68ba7e3093c4 ARM: dts: qcom: drop underscore in node names
f0e620731d60 arm64: dts: qcom: x1e80100-romulus: Set up USB Multiport controller
15693801706e arm64: dts: qcom: x1e80100-romulus: Add lid switch
3ac1117ff640 dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings
10088f897c56 dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings
583c833f335a dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings
90455163e2d5 dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings
7931a601e1a3 dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings
4bd022291a79 arm64: dts: qcom: sc7280: Fix PMU nodes for Cortex A55 and A78
d2f949857a37 arm64: dts: qcom: x1e80100: Add debug uart to Lenovo Yoga Slim 7x
d6b8df3106b0 arm64: dts: qcom: x1e80100: describe tcsr download mode register
731c1cb1f4d5 arm64: dts: qcom: qcs6460-rb3gen2: enable venus node
e9720dc3afbb arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu
06424041d32a arm64: dts: qcom: sm8450: Affirm IDR0.CCTW on apps_smmu
47ccab6fcc0b arm64: dts: qcom: sm8350: Affirm IDR0.CCTW on apps_smmu
e45dd32195c3 arm64: dts: qcom: sm8150: Affirm IDR0.CCTW on apps_smmu
8f3c1d70a169 arm64: dts: qcom: sm6350: Affirm IDR0.CCTW on apps_smmu
df39a8050659 arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu
270061a6fab8 arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on apps_smmu
29387ce4c082 arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
7a314949e604 arm64: dts: qcom: sc8180x: Affirm IDR0.CCTW on apps_smmu
435e35553ca3 arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu
8a7b76025358 arm64: dts: qcom: qdu1000: Affirm IDR0.CCTW on apps_smmu
ec6f718f9ab9 arm64: dts: qcom: qcs6490-rb3gen2: Add SD Card node
31437b048a52 arm64: dts: qcom: sm8650-qrd: remove status property from dispcc device tree node
57ad38d9eb28 arm64: dts: qcom: sm8650-mtp: remove status property from dispcc device tree node
8132697f573a arm64: dts: qcom: sm8650-hdk: remove status property from dispcc device tree node
84ca17adb974 arm64: dts: qcom: sm8650: don't disable dispcc by default
79a12df8a93d arm64: dts: qcom: sm8450-hdk: remove status property from dispcc device tree node
08f0740fbe38 arm64: dts: qcom: sm8450: don't disable dispcc by default
6a5d2b07a1c2 arm64: dts: qcom: sm8450-sony-xperia-nagara: disable dispcc on derived boards
f90b98759450 arm64: dts: qcom: sm8450-qrd: explicitly disable dispcc on the board
000a8024c143 arm64: dts: qcom: sm8350-hdk: remove a blank overwrite of dispcc node status
8fa4a6d46ef3 arm64: dts: qcom: msm8998: add HDMI nodes
6a7fdd43be12 arm64: dts: rockchip: Switch to hp-det-gpios
110fc4fc8fbf arm64: dts: rockchip: Switch to simple-audio-card,hp-det-gpios
ce578767c731 dt-bindings: iio: light: vishay,veml6075: add vishay,veml6070
29868b055c92 dt-bindings: iio: imu: mpu6050: Add iam20680ht/hp bindings to mpu6050
359080581950 ASoC: Clean up {hp,mic}-det-gpio handling
0df63b22c8f6 ARM: dts: ti: dra7: Remove double include of clock bindings
0283571a7331 ARM: dts: ti: omap3434-sdp: drop linux,mtd-name from onenand node
00b214888af5 ARM: dts: ti: omap: am335x-baltos: drop "gpmc,device-nand" from NAND node
f8150d134ba2 ARM: dts: ti: drop linux,mtd-name from NAND nodes
de6fed174a79 ARM: dts: ti/omap: Fix at24 EEPROM node names
18d97d6cc1c4 dt-bindings: usb: dwc3-imx8mp: add compatible string for imx95
2a4990169e34 dt-bindings: phy: imx8mq-usb: add compatible "fsl,imx95-usb-phy"
fb1256fa92bc dt-bindings: usb: renesas,usbhs: Deprecate renesas,enable-gpio
787d98ae3b39 dt-bindings: usb: add PIC64GX compatibility to mpfs-musb driver
f381d0e73e2b dt-bindings: usb: cypress,cypd4226: Drop Tegra specific GPIO defines
300bb4269d7b dt-bindings: usb: genesys,gl850g: allow downstream device subnodes
c989019ae660 riscv: dts: sophgo: cv1812h: add pinctrl support
b991927c7c78 riscv: dts: sophgo: cv1800b: add pinctrl support
5ea06508d59d scsi: ufs: ufs: qcom: dt-bindings: Document the QCS8300 UFS Controller
ecac4d7c7cc8 dt-bindings: fpga: altr,fpga-passive-serial: Convert to yaml
2403f95db3f8 ASoC: dt-bindings: Deprecate {hp,mic}-det-gpio
87fe2b600252 arm64: dts: qcom: msm8998: add HDMI GPIOs
c7e517c97fb1 dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
585c45d07807 dt-bindings: gpio: st,nomadik-gpio: Add missing "#interrupt-cells" to example
e53b6c7b8261 dt-bindings: interrupt-controller: Add support for sam9x7 aic
8da717b8063d dt-bindings: power: qcom,rpmpd: document qcs615 RPMh power domains
4c93f97cdc68 dt-bindings: power: qcom,rpmpd: document qcs8300 RPMh power domains
3812a499aa89 arm64: dts: mediatek: mt8188: Add SPMI support for PMIC control
45b1e1440500 arm64: dts: mediatek: mt8188: Add PWM nodes for display backlight
adecb482d783 arm64: dts: mediatek: mt8188: Add SMI/LARB/IOMMU support
5c2395ccf030 arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq
15509164371c arm64: dts: mt8183: Add port node to dpi node
8b07a795fc1c arm64: dts: mt8192-asurada-spherion: Add Synaptics trackpad support
69967111e2b7 arm64: dts: mediatek: mt8186: add FHCTL node
5469dabf6e10 arm64: dts: mediatek: mt8183-pumpkin: add HDMI support
5b01d93025d9 arm64: dts: mediatek: mt8183-kukui: Disable DPI display interface
3bf7adce8f91 arm64: dts: mt8195: Fix dtbs_check error for infracfg_ao node
3eb5b79226ac arm64: dts: mt8195: Fix dtbs_check error for mutex node
79d5a4c7c8b5 arm64: dts: mediatek: mt8395-genio-1200-evk: Fix dtbs_check error for phy
f7e4d69ece47 arm64: dts: mediatek: mt8188: Move SPI NOR *-cells properties
5311cb9de085 arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0
41b85940d81e arm64: dts: mediatek: mt8188: Update vppsys node names to syscon
372ce47e0e06 arm64: dts: mediatek: mt8188: Add missing dma-ranges to soc node
288630890bef arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU
f6802405f4e0 arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain
d4805550924b arm64: dts: rockchip: Enable all 3 USBs on Turing RK1
c9b0d499654d arm64: dts: rockchip: Add Powkiddy RGB20SX
c5b382a594f3 dt-bindings: arm: rockchip: Add Powkiddy RGB20SX
39e90c62b050 arm64: dts: rockchip: Add power button for puma-haikou
b531c25e8e6a dt-bindings: hwinfo: samsung,exynos-chipid: add exynos8895 compatible
fe24d3cdfab3 arm64: dts: exynos: Add initial support for Samsung Galaxy S8
09bf72ba53d2 arm64: dts: exynos: Add initial support for exynos8895 SoC
24af01abacf8 dt-bindings: soc: samsung: exynos-pmu: Add exynos8895 compatible
4ef6f9244f74 dt-bindings: arm: samsung: Document dreamlte board binding
7218905e111f dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible
41f5d2a15643 dt-bindings: pinctrl: samsung: Add compatible for Exynos8895 SoC
4f59ba89a4a4 dt-bindings: arm: cpus: Add Samsung Mongoose M2
4a89b93976ca arm64: zynqmp: Add thermal zones
11a1b40f2a46 arm64: zynqmp: Expose AMS to userspace as HWMON
9c79137dfa71 arm64: zynqmp: Enable AMS for all boards
4297cfaff763 ARM: dts: socfpga: Fix at24 EEPROM node names
1a8e565ffe0b dt-bindings: Fix array property constraints
c1848318abfe dt-bindings: interrupt-controller: fsl,mu-msi: Drop "interrupt-controller" property
1ec511ef069d dt-bindings: interrupt-controller: ti,sci-inta: Add missing "#interrupt-cells" to example
74424e7f23bb dt-bindings: trivial-devices: add onnn,adt7462
63357e975889 dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer
9f689f9f85b1 ASoC: Add NTP8918 and NTP8835 codecs support
d083bbb62bec dt-bindings: pinctrl: amlogic,meson-pinctrl: lower gpio-line-names minItems for meson8b
edd8d8764671 dt-bindings: pinctrl: Add support for canaan,k230 SoC
6a4f33926064 ARM: dts: renesas: rskrza1: Enable watchdog timer
2a6957e1269c arm64: dts: renesas: rcar-gen4: Switch PCIe to reset-gpios
2ba8c4a5d5d8 ARM: dts: renesas: rza2mevb: Use interrupts-extended for gpio-keys
f7a030d3b38b ARM: dts: renesas: rskrza1: Use interrupts-extended for gpio-keys
aaecea0f8bd4 ARM: dts: renesas: marzen: Use interrupts-extended for gpio-keys
2f03ec558600 ARM: dts: renesas: Remove 'reg-io-width' properties from MMCIF nodes
fff0ddf2bce0 ARM: dts: renesas: Genmai: Update audio codec device node
d8679d2be154 ARM: dts: renesas: genmai: Define keyboard switch
fbb0e65b243d ARM: dts: renesas: genmai: Sort nodes
ea18b054bf65 ARM: dts: renesas: genmai: Enable OS timer modules
68f8258dbf51 ARM: dts: renesas: genmai: Enable watchdog
c733788f6999 ARM: dts: renesas: genmai: Fix partition size for QSPI NOR Flash
36d49e7ae7cc arm64: dts: renesas: r8a779h0: gray-hawk-single: Enable PCIe Host
0d0c88a036b8 arm64: dts: renesas: r8a779h0: Add PCIe Host and Endpoint nodes
d909bff40dfc dt-bindings: pinctrl: qcom: add IPQ5424 pinctrl
28dc5229ae20 Merge branch 'ib-thead-th1520' into devel
33380f1c1ff3 dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings
259cd8c48685 dt-bindings: ocelot: document lan969x-pinctrl
8a571eac3232 dt-bindings: pinctrl: Add SA8255p TLMM
af7be1413d12 dt-bindings: pinctrl: Add support for Xilinx Versal platform
c78de6d3a962 dt-bindings: opp: operating-points-v2-ti-cpu: Describe opp-supported-hw
ec5754987a33 dt-bindings: cpufreq: qcom-hw: document support for SA8255p
ba56c1c064ae arm64: dts: qcom: qcm6490-rb3gen2: enable WiFi
ef14321de506 arm64: dts: qcom: qcm6490-idp: enable WiFi
600a06a3b099 arm64: dts: qcom: sc7280: don't enable GPU on unsupported devices
54debad84f18 arm64: dts: qcom: qcs6390-rb3gen2: use modem.mbn for modem DSP
1031c2c08dea ASoC: dt-bindings: mt6359: Update generic node name and dmic-mode
892d16539671 arm64: dts: rockchip: add LED_FUNCTION_STATUS for RGB LEDs on Radxa E25
c832f8ac3bdc arm64: dts: rockchip: Add AP6275P wireless support to Khadas Edge 2
43840031417b arm64: dts: rockchip: Enable GPU on Turing RK1
3e0e636a275b arm64: dts: rockchip: Enable automatic fan control on Turing RK1
36cf08da66a0 arm64: dts: rockchip: Fix Turing RK1 PCIe3 hang
0764ad8c0518 dt-bindings: clock: samsung: remove define with number of clocks for FSD
3754b2afab7e dt-bindings: memory-controllers: fsl,ifc: split child node differences
8713425fa162 arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
da10f3b08e0f arm64: dts: rockchip: Add RK3588S EVB1 board
33d6b7f1ff4c dt-bindings: arm: rockchip: Add RK3588S EVB1 board
e19e92e9272b arm64: dts: rockchip: Add ArmSoM W3 board
25b187da6e7e arm64: dts: rockchip: Add ArmSoM LM7 SoM
9dad170bea61 dt-bindings: arm: rockchip: Add ArmSoM LM7 SoM
c80b7eba6833 dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
e5b590f7e262 arm64: dts: rockchip: enable automatic fan control on Orange Pi 5+
5f528a6fedb9 Merge drm/drm-next into drm-misc-next
da705300feb6 arm64: dts: rockchip: add attiny_rst_gate to Ringneck
ee185d62e14c arm64: dts: rockchip: add tsd,mule-i2c-mux on px30-ringneck
12d6e10731a4 arm64: dts: rockchip: add tsd,mule-i2c-mux on rk3588-tiger
2dc1a4182c54 arm64: dts: rockchip: add tsd,mule-i2c-mux on rk3399-puma
f3e1990f27da arm64: dts: rockchip: add tsd,mule-i2c-mux on rk3588-jaguar
d61cebb06ff5 dt-bindings: iio: adc: add docs for AD7606C-{16,18} parts
51789d5e7711 dt-bindings: iio: adc: document diff-channels corner case for some ADCs
5e6cfa1a03fb dt-bindings: iio: adc: amlogic,meson-saradc: also allow meson8-saradc to have amlogic,hhi-sysctrl property
970192b0e4c8 dt-bindings: iio: dac: add docs for ad8460
f952c57b067c dt-bindings: iio: light: veml6030: rename to add manufacturer
0cc281b14ca3 dt-bindings: iio: imu: add bmi270 bindings
2b6408921687 dt-bindings: iio: temperature: tmp006: document interrupt
458e2c6fa81b dt-bindings: adc: ad7173: add support for ad4113
da37218f1f2c ARM: dts: amlogic: meson8b-ec100: add missing gpio-line-names entry
68910695abce ARM: dts: amlogic: meson8b-ec100: add missing clocks property in sound card
5dc11b8ed550 ARM: dts: amlogic: meson8-minix-neo-x8: fix invalid pnictrl-names
e9810e32f796 ARM: dts: amlogic: add missing phy-mode in ethmac node
9245aa5c751f ARM: dts: amlogic: meson8: use correct pinctrl bank node name
98b22e41c153 ARM: dts: amlogic: fix /memory node name
4b92b8bf2966 ARM: dts: amlogic: meson8b-odroidc1: fix invalid reset-gpio
6566ba1b4784 ARM: dts: amlogic: meson6: remove support for ATV1200 board
9af30064241f ARM: dts: amlogic: meson8: fix ao_arc_sram node name
0a7a4881969f ARM: dts: amlogic: meson8: fix soc thermal-zone node name
65b134aa3213 ARM: dts: amlogic: meson6: fix clk81 node name
7044f82e12d9 arm64: dts: meson-g12-common: fix uart-ao-a typo
d3b5013b44d4 arm64: dts: meson: a1: bind power domain to temperature sensor
21e260e3efc5 arm64: dts: meson: a1: add definitions for meson PWM
0af71311758b dt-bindings: input: document Novatek NVT touchscreen controller
e3b7e5dc666b dt-bindings: spi: zynqmp-qspi: Include two 'reg' properties only for the Zynq UltraScale QSPI
18838fc29859 ASoC: dt-bindings: realtek,rt5640: Convert to dtschema
45a46ecc03be ASoC: dt-bindings: fsl-esai: Add power-domains for fsl,imx8qm-esai
7cc0672d511b ASoC: dt-bindings: Add NeoFidelity NTP8835
fe920ac500b5 ASoC: dt-bindings: Add NeoFidelity NTP8918
d1100655b714 dt-bindings: vendor-prefixes: Add NeoFidelity, Inc
1dc6b237e2cb dt-bindings: net: ath11k: document the inputs of the ath11k on WCN6855
30556a11ec4f dt-bindings: lcdif: Document the dmas/dma-names properties
d8fb8bc2cda5 dt-bindings: net: wireless: brcm4329-fmac: add clock description for AP6275P
e479085c013c dt-bindings: net: wireless: brcm4329-fmac: add pci14e4,449d
7ad9cb0fdd60 Merge drm/drm-next into drm-misc-next
f3263e455928 dt-bindings: gpu: Add rockchip,rk3576-mali compatible
ab5d13f0b89f dt-bindings: display: bridge: add TI TDP158
a696036bd331 dt-bindings: display: imx/ldb: drop ddc-i2c-bus property
0bf2495489f6 dt-bindings: display: fsl-imx-drm: drop edid property support

git-subtree-dir: dts/upstream
git-subtree-split: 8531b4b4988c2c9bddc90ea74f2d3e2dca9d5056

include/dt-bindings/arm/qcom,ids.h

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 8332f8d..e850dc3 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -255,8 +255,10 @@
 #define QCOM_ID_IPQ9510			521
 #define QCOM_ID_QRB4210			523
 #define QCOM_ID_QRB2210			524
+#define QCOM_ID_SAR2130P		525
 #define QCOM_ID_SM8475			530
 #define QCOM_ID_SM8475P			531
+#define QCOM_ID_SA8255P			532
 #define QCOM_ID_SA8775P			534
 #define QCOM_ID_QRU1000			539
 #define QCOM_ID_SM8475_2		540
@@ -264,6 +266,7 @@
 #define QCOM_ID_X1E80100		555
 #define QCOM_ID_SM8650			557
 #define QCOM_ID_SM4450			568
+#define QCOM_ID_SAR1130P		579
 #define QCOM_ID_QDU1010			587
 #define QCOM_ID_QRU1032			588
 #define QCOM_ID_QRU1052			589
@@ -276,8 +279,12 @@
 #define QCOM_ID_QCM8550			604
 #define QCOM_ID_IPQ5300			624
 #define QCOM_ID_IPQ5321			650
+#define QCOM_ID_IPQ5424			651
+#define QCOM_ID_IPQ5404			671
+#define QCOM_ID_QCS9100			667
 #define QCOM_ID_QCS8300			674
 #define QCOM_ID_QCS8275			675
+#define QCOM_ID_QCS615			680
 
 /*
  * The board type and revision information, used by Qualcomm bootloaders and

include/dt-bindings/clock/aspeed,ast2700-scu.h

diff --git a/include/dt-bindings/clock/aspeed,ast2700-scu.h b/include/dt-bindings/clock/aspeed,ast2700-scu.h
new file mode 100644
index 0000000..63021af
--- /dev/null
+++ b/include/dt-bindings/clock/aspeed,ast2700-scu.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 clock controller.
+ *
+ * Copyright (c) 2024 Aspeed Technology Inc.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_AST2700_H
+#define __DT_BINDINGS_CLOCK_AST2700_H
+
+/* SOC0 clk */
+#define SCU0_CLKIN		0
+#define SCU0_CLK_24M		1
+#define SCU0_CLK_192M		2
+#define SCU0_CLK_UART		3
+#define SCU0_CLK_UART_DIV13	3
+#define SCU0_CLK_PSP		4
+#define SCU0_CLK_HPLL		5
+#define SCU0_CLK_HPLL_DIV2	6
+#define SCU0_CLK_HPLL_DIV4	7
+#define SCU0_CLK_HPLL_DIV_AHB	8
+#define SCU0_CLK_DPLL		9
+#define SCU0_CLK_MPLL		10
+#define SCU0_CLK_MPLL_DIV2	11
+#define SCU0_CLK_MPLL_DIV4	12
+#define SCU0_CLK_MPLL_DIV8	13
+#define SCU0_CLK_MPLL_DIV_AHB	14
+#define SCU0_CLK_D0		15
+#define SCU0_CLK_D1		16
+#define SCU0_CLK_CRT0		17
+#define SCU0_CLK_CRT1		18
+#define SCU0_CLK_MPHY		19
+#define SCU0_CLK_AXI0		20
+#define SCU0_CLK_AXI1		21
+#define SCU0_CLK_AHB		22
+#define SCU0_CLK_APB		23
+#define SCU0_CLK_UART4		24
+#define SCU0_CLK_EMMCMUX	25
+#define SCU0_CLK_EMMC		26
+#define SCU0_CLK_U2PHY_CLK12M	27
+#define SCU0_CLK_U2PHY_REFCLK	28
+
+/* SOC0 clk-gate */
+#define SCU0_CLK_GATE_MCLK	29
+#define SCU0_CLK_GATE_ECLK	30
+#define SCU0_CLK_GATE_2DCLK	31
+#define SCU0_CLK_GATE_VCLK	32
+#define SCU0_CLK_GATE_BCLK	33
+#define SCU0_CLK_GATE_VGA0CLK	34
+#define SCU0_CLK_GATE_REFCLK	35
+#define SCU0_CLK_GATE_PORTBUSB2CLK	36
+#define SCU0_CLK_GATE_UHCICLK	37
+#define SCU0_CLK_GATE_VGA1CLK	38
+#define SCU0_CLK_GATE_DDRPHYCLK	39
+#define SCU0_CLK_GATE_E2M0CLK	40
+#define SCU0_CLK_GATE_HACCLK	41
+#define SCU0_CLK_GATE_PORTAUSB2CLK	42
+#define SCU0_CLK_GATE_UART4CLK	43
+#define SCU0_CLK_GATE_SLICLK	44
+#define SCU0_CLK_GATE_DACCLK	45
+#define SCU0_CLK_GATE_DP	46
+#define SCU0_CLK_GATE_E2M1CLK	47
+#define SCU0_CLK_GATE_CRT0CLK	48
+#define SCU0_CLK_GATE_CRT1CLK	49
+#define SCU0_CLK_GATE_ECDSACLK	50
+#define SCU0_CLK_GATE_RSACLK	51
+#define SCU0_CLK_GATE_RVAS0CLK	52
+#define SCU0_CLK_GATE_UFSCLK	53
+#define SCU0_CLK_GATE_EMMCCLK	54
+#define SCU0_CLK_GATE_RVAS1CLK	55
+
+/* SOC1 clk */
+#define SCU1_CLKIN		0
+#define SCU1_CLK_HPLL		1
+#define SCU1_CLK_APLL		2
+#define SCU1_CLK_APLL_DIV2	3
+#define SCU1_CLK_APLL_DIV4	4
+#define SCU1_CLK_DPLL		5
+#define SCU1_CLK_UXCLK		6
+#define SCU1_CLK_HUXCLK		7
+#define SCU1_CLK_UARTX		8
+#define SCU1_CLK_HUARTX		9
+#define SCU1_CLK_AHB		10
+#define SCU1_CLK_APB		11
+#define SCU1_CLK_UART0		12
+#define SCU1_CLK_UART1		13
+#define SCU1_CLK_UART2		14
+#define SCU1_CLK_UART3		15
+#define SCU1_CLK_UART5		16
+#define SCU1_CLK_UART6		17
+#define SCU1_CLK_UART7		18
+#define SCU1_CLK_UART8		19
+#define SCU1_CLK_UART9		20
+#define SCU1_CLK_UART10		21
+#define SCU1_CLK_UART11		22
+#define SCU1_CLK_UART12		23
+#define SCU1_CLK_UART13		24
+#define SCU1_CLK_UART14		25
+#define SCU1_CLK_APLL_DIVN	26
+#define SCU1_CLK_SDMUX		27
+#define SCU1_CLK_SDCLK		28
+#define SCU1_CLK_RMII		29
+#define SCU1_CLK_RGMII		30
+#define SCU1_CLK_MACHCLK	31
+#define SCU1_CLK_MAC0RCLK	32
+#define SCU1_CLK_MAC1RCLK	33
+#define SCU1_CLK_CAN		34
+
+/* SOC1 clk gate */
+#define SCU1_CLK_GATE_LCLK0		35
+#define SCU1_CLK_GATE_LCLK1		36
+#define SCU1_CLK_GATE_ESPI0CLK		37
+#define SCU1_CLK_GATE_ESPI1CLK		38
+#define SCU1_CLK_GATE_SDCLK		39
+#define SCU1_CLK_GATE_IPEREFCLK		40
+#define SCU1_CLK_GATE_REFCLK		41
+#define SCU1_CLK_GATE_LPCHCLK		42
+#define SCU1_CLK_GATE_MAC0CLK		43
+#define SCU1_CLK_GATE_MAC1CLK		44
+#define SCU1_CLK_GATE_MAC2CLK		45
+#define SCU1_CLK_GATE_UART0CLK		46
+#define SCU1_CLK_GATE_UART1CLK		47
+#define SCU1_CLK_GATE_UART2CLK		48
+#define SCU1_CLK_GATE_UART3CLK		49
+#define SCU1_CLK_GATE_I2CCLK		50
+#define SCU1_CLK_GATE_I3C0CLK		51
+#define SCU1_CLK_GATE_I3C1CLK		52
+#define SCU1_CLK_GATE_I3C2CLK		53
+#define SCU1_CLK_GATE_I3C3CLK		54
+#define SCU1_CLK_GATE_I3C4CLK		55
+#define SCU1_CLK_GATE_I3C5CLK		56
+#define SCU1_CLK_GATE_I3C6CLK		57
+#define SCU1_CLK_GATE_I3C7CLK		58
+#define SCU1_CLK_GATE_I3C8CLK		59
+#define SCU1_CLK_GATE_I3C9CLK		60
+#define SCU1_CLK_GATE_I3C10CLK		61
+#define SCU1_CLK_GATE_I3C11CLK		62
+#define SCU1_CLK_GATE_I3C12CLK		63
+#define SCU1_CLK_GATE_I3C13CLK		64
+#define SCU1_CLK_GATE_I3C14CLK		65
+#define SCU1_CLK_GATE_I3C15CLK		66
+#define SCU1_CLK_GATE_UART5CLK		67
+#define SCU1_CLK_GATE_UART6CLK		68
+#define SCU1_CLK_GATE_UART7CLK		69
+#define SCU1_CLK_GATE_UART8CLK		70
+#define SCU1_CLK_GATE_UART9CLK		71
+#define SCU1_CLK_GATE_UART10CLK		72
+#define SCU1_CLK_GATE_UART11CLK		73
+#define SCU1_CLK_GATE_UART12CLK		74
+#define SCU1_CLK_GATE_FSICLK		75
+#define SCU1_CLK_GATE_LTPIPHYCLK	76
+#define SCU1_CLK_GATE_LTPICLK		77
+#define SCU1_CLK_GATE_VGALCLK		78
+#define SCU1_CLK_GATE_UHCICLK		79
+#define SCU1_CLK_GATE_CANCLK		80
+#define SCU1_CLK_GATE_PCICLK		81
+#define SCU1_CLK_GATE_SLICLK		82
+#define SCU1_CLK_GATE_E2MCLK		83
+#define SCU1_CLK_GATE_PORTCUSB2CLK	84
+#define SCU1_CLK_GATE_PORTDUSB2CLK	85
+#define SCU1_CLK_GATE_LTPI1TXCLK	86
+
+#endif

include/dt-bindings/clock/fsd-clk.h

diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h
index c8a2af1..3f7b64d 100644
--- a/include/dt-bindings/clock/fsd-clk.h
+++ b/include/dt-bindings/clock/fsd-clk.h
@@ -28,7 +28,6 @@
 #define DOUT_CMU_IMEM_ACLK			13
 #define DOUT_CMU_IMEM_DMACLK			14
 #define GAT_CMU_FSYS0_SHARED0DIV4		15
-#define CMU_NR_CLK				16
 
 /* PERIC */
 #define PERIC_SCLK_UART0			1
@@ -76,7 +75,6 @@
 #define PERIC_EQOS_PHYRXCLK_MUX			43
 #define PERIC_EQOS_PHYRXCLK			44
 #define PERIC_DOUT_RGMII_CLK			45
-#define PERIC_NR_CLK				46
 
 /* FSYS0 */
 #define UFS0_MPHY_REFCLK_IXTAL24		1
@@ -101,7 +99,6 @@
 #define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I	20
 #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I	21
 #define FSYS0_DOUT_FSYS0_PERIBUS_GRP		22
-#define FSYS0_NR_CLK				23
 
 /* FSYS1 */
 #define PCIE_LINK0_IPCLKPORT_DBI_ACLK		1
@@ -112,7 +109,6 @@
 #define PCIE_LINK1_IPCLKPORT_AUX_ACLK		6
 #define PCIE_LINK1_IPCLKPORT_MSTR_ACLK		7
 #define PCIE_LINK1_IPCLKPORT_SLV_ACLK		8
-#define FSYS1_NR_CLK				9
 
 /* IMEM */
 #define IMEM_DMA0_IPCLKPORT_ACLK		1
@@ -126,11 +122,9 @@
 #define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS		9
 #define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS		10
 #define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS		11
-#define IMEM_NR_CLK				12
 
 /* MFC */
 #define MFC_MFC_IPCLKPORT_ACLK			1
-#define MFC_NR_CLK				2
 
 /* CAM_CSI */
 #define CAM_CSI0_0_IPCLKPORT_I_ACLK		1
@@ -145,6 +139,5 @@
 #define CAM_CSI2_1_IPCLKPORT_I_ACLK		10
 #define CAM_CSI2_2_IPCLKPORT_I_ACLK		11
 #define CAM_CSI2_3_IPCLKPORT_I_ACLK		12
-#define CAM_CSI_NR_CLK				13
 
 #endif /*_DT_BINDINGS_CLOCK_FSD_H */

include/dt-bindings/clock/imx93-clock.h

diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h
index 787c9e7..6c68506 100644
--- a/include/dt-bindings/clock/imx93-clock.h
+++ b/include/dt-bindings/clock/imx93-clock.h
@@ -204,6 +204,10 @@
 #define IMX93_CLK_A55_SEL		199
 #define IMX93_CLK_A55_CORE		200
 #define IMX93_CLK_PDM_IPG		201
-#define IMX93_CLK_END			202
+#define IMX91_CLK_ENET1_QOS_TSN     202
+#define IMX91_CLK_ENET_TIMER        203
+#define IMX91_CLK_ENET2_REGULAR     204
+#define IMX91_CLK_ENET2_REGULAR_GATE		205
+#define IMX91_CLK_ENET1_QOS_TSN_GATE		206
 
 #endif

include/dt-bindings/clock/marvell,pxa1908.h

diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
new file mode 100644
index 0000000..fb15b0d
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa1908.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
+#define __DTS_MARVELL_PXA1908_CLOCK_H
+
+/* plls */
+#define PXA1908_CLK_CLK32		1
+#define PXA1908_CLK_VCTCXO		2
+#define PXA1908_CLK_PLL1_624		3
+#define PXA1908_CLK_PLL1_416		4
+#define PXA1908_CLK_PLL1_499		5
+#define PXA1908_CLK_PLL1_832		6
+#define PXA1908_CLK_PLL1_1248		7
+#define PXA1908_CLK_PLL1_D2		8
+#define PXA1908_CLK_PLL1_D4		9
+#define PXA1908_CLK_PLL1_D8		10
+#define PXA1908_CLK_PLL1_D16		11
+#define PXA1908_CLK_PLL1_D6		12
+#define PXA1908_CLK_PLL1_D12		13
+#define PXA1908_CLK_PLL1_D24		14
+#define PXA1908_CLK_PLL1_D48		15
+#define PXA1908_CLK_PLL1_D96		16
+#define PXA1908_CLK_PLL1_D13		17
+#define PXA1908_CLK_PLL1_32		18
+#define PXA1908_CLK_PLL1_208		19
+#define PXA1908_CLK_PLL1_117		20
+#define PXA1908_CLK_PLL1_416_GATE	21
+#define PXA1908_CLK_PLL1_624_GATE	22
+#define PXA1908_CLK_PLL1_832_GATE	23
+#define PXA1908_CLK_PLL1_1248_GATE	24
+#define PXA1908_CLK_PLL1_D2_GATE	25
+#define PXA1908_CLK_PLL1_499_EN		26
+#define PXA1908_CLK_PLL2VCO		27
+#define PXA1908_CLK_PLL2		28
+#define PXA1908_CLK_PLL2P		29
+#define PXA1908_CLK_PLL2VCODIV3		30
+#define PXA1908_CLK_PLL3VCO		31
+#define PXA1908_CLK_PLL3		32
+#define PXA1908_CLK_PLL3P		33
+#define PXA1908_CLK_PLL3VCODIV3		34
+#define PXA1908_CLK_PLL4VCO		35
+#define PXA1908_CLK_PLL4		36
+#define PXA1908_CLK_PLL4P		37
+#define PXA1908_CLK_PLL4VCODIV3		38
+
+/* apb (apbc) peripherals */
+#define PXA1908_CLK_UART0		1
+#define PXA1908_CLK_UART1		2
+#define PXA1908_CLK_GPIO		3
+#define PXA1908_CLK_PWM0		4
+#define PXA1908_CLK_PWM1		5
+#define PXA1908_CLK_PWM2		6
+#define PXA1908_CLK_PWM3		7
+#define PXA1908_CLK_SSP0		8
+#define PXA1908_CLK_SSP1		9
+#define PXA1908_CLK_IPC_RST		10
+#define PXA1908_CLK_RTC			11
+#define PXA1908_CLK_TWSI0		12
+#define PXA1908_CLK_KPC			13
+#define PXA1908_CLK_SWJTAG		14
+#define PXA1908_CLK_SSP2		15
+#define PXA1908_CLK_TWSI1		16
+#define PXA1908_CLK_THERMAL		17
+#define PXA1908_CLK_TWSI3		18
+
+/* apb (apbcp) peripherals */
+#define PXA1908_CLK_UART2		1
+#define PXA1908_CLK_TWSI2		2
+#define PXA1908_CLK_AICER		3
+
+/* axi (apmu) peripherals */
+#define PXA1908_CLK_CCIC1		1
+#define PXA1908_CLK_ISP			2
+#define PXA1908_CLK_DSI1		3
+#define PXA1908_CLK_DISP1		4
+#define PXA1908_CLK_CCIC0		5
+#define PXA1908_CLK_SDH0		6
+#define PXA1908_CLK_SDH1		7
+#define PXA1908_CLK_USB			8
+#define PXA1908_CLK_NF			9
+#define PXA1908_CLK_CORE_DEBUG		10
+#define PXA1908_CLK_VPU			11
+#define PXA1908_CLK_GC			12
+#define PXA1908_CLK_SDH2		13
+#define PXA1908_CLK_GC2D		14
+#define PXA1908_CLK_TRACE		15
+#define PXA1908_CLK_DVC_DFC_DEBUG	16
+
+#endif

include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
new file mode 100644
index 0000000..b470520
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
+#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIVPLL		2
+#define CLK_APMIXED_MMPLL		3
+#define CLK_APMIXED_MSDCPLL		4
+#define CLK_APMIXED_VENCPLL		5
+#define CLK_APMIXED_TVDPLL		6
+#define CLK_APMIXED_APLL1		7
+#define CLK_APMIXED_APLL2		8
+
+#endif

include/dt-bindings/clock/mediatek,mt6735-imgsys.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h
new file mode 100644
index 0000000..f250c26
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H
+#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H
+
+#define CLK_IMG_SMI_LARB2		0
+#define CLK_IMG_CAM_SMI			1
+#define CLK_IMG_CAM_CAM			2
+#define CLK_IMG_SEN_TG			3
+#define CLK_IMG_SEN_CAM			4
+#define CLK_IMG_CAM_SV			5
+#define CLK_IMG_SUFOD			6
+#define CLK_IMG_FD			7
+
+#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */

include/dt-bindings/clock/mediatek,mt6735-infracfg.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
new file mode 100644
index 0000000..d8dd51e
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
+#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
+
+#define CLK_INFRA_DBG			0
+#define CLK_INFRA_GCE			1
+#define CLK_INFRA_TRBG			2
+#define CLK_INFRA_CPUM			3
+#define CLK_INFRA_DEVAPC		4
+#define CLK_INFRA_AUDIO			5
+#define CLK_INFRA_GCPU			6
+#define CLK_INFRA_L2C_SRAM		7
+#define CLK_INFRA_M4U			8
+#define CLK_INFRA_CLDMA			9
+#define CLK_INFRA_CONNMCU_BUS		10
+#define CLK_INFRA_KP			11
+#define CLK_INFRA_APXGPT		12
+#define CLK_INFRA_SEJ			13
+#define CLK_INFRA_CCIF0_AP		14
+#define CLK_INFRA_CCIF1_AP		15
+#define CLK_INFRA_PMIC_SPI		16
+#define CLK_INFRA_PMIC_WRAP		17
+
+#endif

include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
new file mode 100644
index 0000000..d2d99a4
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H
+#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H
+
+#define CLK_MFG_BG3D			0
+
+#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */

include/dt-bindings/clock/mediatek,mt6735-pericfg.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h
new file mode 100644
index 0000000..16bc21b
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H
+#define _DT_BINDINGS_CLK_MT6735_PERICFG_H
+
+#define CLK_PERI_DISP_PWM		0
+#define CLK_PERI_THERM			1
+#define CLK_PERI_PWM1			2
+#define CLK_PERI_PWM2			3
+#define CLK_PERI_PWM3			4
+#define CLK_PERI_PWM4			5
+#define CLK_PERI_PWM5			6
+#define CLK_PERI_PWM6			7
+#define CLK_PERI_PWM7			8
+#define CLK_PERI_PWM			9
+#define CLK_PERI_USB0			10
+#define CLK_PERI_IRDA			11
+#define CLK_PERI_APDMA			12
+#define CLK_PERI_MSDC30_0		13
+#define CLK_PERI_MSDC30_1		14
+#define CLK_PERI_MSDC30_2		15
+#define CLK_PERI_MSDC30_3		16
+#define CLK_PERI_UART0			17
+#define CLK_PERI_UART1			18
+#define CLK_PERI_UART2			19
+#define CLK_PERI_UART3			20
+#define CLK_PERI_UART4			21
+#define CLK_PERI_BTIF			22
+#define CLK_PERI_I2C0			23
+#define CLK_PERI_I2C1			24
+#define CLK_PERI_I2C2			25
+#define CLK_PERI_I2C3			26
+#define CLK_PERI_AUXADC			27
+#define CLK_PERI_SPI0			28
+#define CLK_PERI_IRTX			29
+
+#endif

include/dt-bindings/clock/mediatek,mt6735-topckgen.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h
new file mode 100644
index 0000000..d4b1e11
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
+#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
+
+#define CLK_TOP_AD_SYS_26M_CK		0
+#define CLK_TOP_CLKPH_MCK_O		1
+#define CLK_TOP_DMPLL			2
+#define CLK_TOP_DPI_CK			3
+#define CLK_TOP_WHPLL_AUDIO_CK		4
+
+#define CLK_TOP_SYSPLL_D2		5
+#define CLK_TOP_SYSPLL_D3		6
+#define CLK_TOP_SYSPLL_D5		7
+#define CLK_TOP_SYSPLL1_D2		8
+#define CLK_TOP_SYSPLL1_D4		9
+#define CLK_TOP_SYSPLL1_D8		10
+#define CLK_TOP_SYSPLL1_D16		11
+#define CLK_TOP_SYSPLL2_D2		12
+#define CLK_TOP_SYSPLL2_D4		13
+#define CLK_TOP_SYSPLL3_D2		14
+#define CLK_TOP_SYSPLL3_D4		15
+#define CLK_TOP_SYSPLL4_D2		16
+#define CLK_TOP_SYSPLL4_D4		17
+#define CLK_TOP_UNIVPLL_D2		18
+#define CLK_TOP_UNIVPLL_D3		19
+#define CLK_TOP_UNIVPLL_D5		20
+#define CLK_TOP_UNIVPLL_D26		21
+#define CLK_TOP_UNIVPLL1_D2		22
+#define CLK_TOP_UNIVPLL1_D4		23
+#define CLK_TOP_UNIVPLL1_D8		24
+#define CLK_TOP_UNIVPLL2_D2		25
+#define CLK_TOP_UNIVPLL2_D4		26
+#define CLK_TOP_UNIVPLL2_D8		27
+#define CLK_TOP_UNIVPLL3_D2		28
+#define CLK_TOP_UNIVPLL3_D4		29
+#define CLK_TOP_MSDCPLL_D2		30
+#define CLK_TOP_MSDCPLL_D4		31
+#define CLK_TOP_MSDCPLL_D8		32
+#define CLK_TOP_MSDCPLL_D16		33
+#define CLK_TOP_VENCPLL_D3		34
+#define CLK_TOP_TVDPLL_D2		35
+#define CLK_TOP_TVDPLL_D4		36
+#define CLK_TOP_DMPLL_D2		37
+#define CLK_TOP_DMPLL_D4		38
+#define CLK_TOP_DMPLL_D8		39
+#define CLK_TOP_AD_SYS_26M_D2		40
+
+#define CLK_TOP_AXI_SEL			41
+#define CLK_TOP_MEM_SEL			42
+#define CLK_TOP_DDRPHY_SEL		43
+#define CLK_TOP_MM_SEL			44
+#define CLK_TOP_PWM_SEL			45
+#define CLK_TOP_VDEC_SEL		46
+#define CLK_TOP_MFG_SEL			47
+#define CLK_TOP_CAMTG_SEL		48
+#define CLK_TOP_UART_SEL		49
+#define CLK_TOP_SPI_SEL			50
+#define CLK_TOP_USB20_SEL		51
+#define CLK_TOP_MSDC50_0_SEL		52
+#define CLK_TOP_MSDC30_0_SEL		53
+#define CLK_TOP_MSDC30_1_SEL		54
+#define CLK_TOP_MSDC30_2_SEL		55
+#define CLK_TOP_MSDC30_3_SEL		56
+#define CLK_TOP_AUDIO_SEL		57
+#define CLK_TOP_AUDINTBUS_SEL		58
+#define CLK_TOP_PMICSPI_SEL		59
+#define CLK_TOP_SCP_SEL			60
+#define CLK_TOP_ATB_SEL			61
+#define CLK_TOP_DPI0_SEL		62
+#define CLK_TOP_SCAM_SEL		63
+#define CLK_TOP_MFG13M_SEL		64
+#define CLK_TOP_AUD1_SEL		65
+#define CLK_TOP_AUD2_SEL		66
+#define CLK_TOP_IRDA_SEL		67
+#define CLK_TOP_IRTX_SEL		68
+#define CLK_TOP_DISPPWM_SEL		69
+
+#endif

include/dt-bindings/clock/mediatek,mt6735-vdecsys.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
new file mode 100644
index 0000000..f94cec1
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H
+#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H
+
+#define CLK_VDEC_VDEC			0
+#define CLK_VDEC_SMI_LARB1		1
+
+#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */

include/dt-bindings/clock/mediatek,mt6735-vencsys.h

diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h
new file mode 100644
index 0000000..e5a9cb4
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H
+#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H
+
+#define CLK_VENC_SMI_LARB3			0
+#define CLK_VENC_VENC			1
+#define CLK_VENC_JPGENC			2
+#define CLK_VENC_JPGDEC			3
+
+#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */

include/dt-bindings/clock/mobileye,eyeq5-clk.h

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index 26d8930..f353c29 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -6,17 +6,60 @@
 #ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
 #define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
 
-#define EQ5C_PLL_CPU	0
-#define EQ5C_PLL_VMP	1
-#define EQ5C_PLL_PMA	2
-#define EQ5C_PLL_VDI	3
-#define EQ5C_PLL_DDR0	4
-#define EQ5C_PLL_PCI	5
-#define EQ5C_PLL_PER	6
-#define EQ5C_PLL_PMAC	7
-#define EQ5C_PLL_MPC	8
-#define EQ5C_PLL_DDR1	9
+#define EQ5C_PLL_CPU		0
+#define EQ5C_PLL_VMP		1
+#define EQ5C_PLL_PMA		2
+#define EQ5C_PLL_VDI		3
+#define EQ5C_PLL_DDR0		4
+#define EQ5C_PLL_PCI		5
+#define EQ5C_PLL_PER		6
+#define EQ5C_PLL_PMAC		7
+#define EQ5C_PLL_MPC		8
+#define EQ5C_PLL_DDR1		9
+
+#define EQ5C_DIV_OSPI		10
+
+/* EQ5C_PLL_CPU children */
+#define EQ5C_CPU_CORE0		11
+#define EQ5C_CPU_CORE1		12
+#define EQ5C_CPU_CORE2		13
+#define EQ5C_CPU_CORE3		14
+
+/* EQ5C_PLL_PER children */
+#define EQ5C_PER_OCC		15
+#define EQ5C_PER_UART		16
+#define EQ5C_PER_SPI		17
+#define EQ5C_PER_I2C		18
+#define EQ5C_PER_GPIO		19
+#define EQ5C_PER_EMMC		20
+#define EQ5C_PER_OCC_PCI	21
+
+#define EQ6LC_PLL_DDR		0
+#define EQ6LC_PLL_CPU		1
+#define EQ6LC_PLL_PER		2
+#define EQ6LC_PLL_VDI		3
+
+#define EQ6HC_CENTRAL_PLL_CPU	0
+#define EQ6HC_CENTRAL_CPU_OCC	1
+
+#define EQ6HC_WEST_PLL_PER	0
+#define EQ6HC_WEST_PER_OCC	1
+#define EQ6HC_WEST_PER_UART	2
+
+#define EQ6HC_SOUTH_PLL_VDI		0
+#define EQ6HC_SOUTH_PLL_PCIE		1
+#define EQ6HC_SOUTH_PLL_PER		2
+#define EQ6HC_SOUTH_PLL_ISP		3
+
+#define EQ6HC_SOUTH_DIV_EMMC		4
+#define EQ6HC_SOUTH_DIV_OSPI_REF	5
+#define EQ6HC_SOUTH_DIV_OSPI_SYS	6
+#define EQ6HC_SOUTH_DIV_TSU		7
 
-#define EQ5C_DIV_OSPI	10
+#define EQ6HC_ACC_PLL_XNN		0
+#define EQ6HC_ACC_PLL_VMP		1
+#define EQ6HC_ACC_PLL_PMA		2
+#define EQ6HC_ACC_PLL_MPC		3
+#define EQ6HC_ACC_PLL_NOC		4
 
 #endif

include/dt-bindings/clock/qcom,gcc-sm8450.h

diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h
index 9679410..7320e63 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8450.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h
@@ -194,6 +194,9 @@
 #define GCC_VIDEO_AXI0_CLK					182
 #define GCC_VIDEO_AXI1_CLK					183
 #define GCC_VIDEO_XO_CLK					184
+/* Additional SM8475-specific clocks */
+#define SM8475_GCC_GPLL2					185
+#define SM8475_GCC_GPLL3					186
 
 /* GCC resets */
 #define GCC_CAMERA_BCR						0

include/dt-bindings/clock/qcom,ipq5332-gcc.h

diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0..da9b507 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -96,15 +96,7 @@
 #define GCC_PCNOC_BFDCD_CLK_SRC				87
 #define GCC_PCNOC_LPASS_CLK				88
 #define GCC_PRNG_AHB_CLK				89
-#define GCC_Q6_AHB_CLK					90
-#define GCC_Q6_AHB_S_CLK				91
-#define GCC_Q6_AXIM_CLK					92
 #define GCC_Q6_AXIM_CLK_SRC				93
-#define GCC_Q6_AXIS_CLK					94
-#define GCC_Q6_TSCTR_1TO2_CLK				95
-#define GCC_Q6SS_ATBM_CLK				96
-#define GCC_Q6SS_PCLKDBG_CLK				97
-#define GCC_Q6SS_TRIG_CLK				98
 #define GCC_QDSS_AT_CLK					99
 #define GCC_QDSS_AT_CLK_SRC				100
 #define GCC_QDSS_CFG_AHB_CLK				101
@@ -134,7 +126,6 @@
 #define GCC_SNOC_PCIE3_2LANE_S_CLK			125
 #define GCC_SNOC_USB_CLK				126
 #define GCC_SYS_NOC_AT_CLK				127
-#define GCC_SYS_NOC_WCSS_AHB_CLK			128
 #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC			129
 #define GCC_UNIPHY0_AHB_CLK				130
 #define GCC_UNIPHY0_SYS_CLK				131
@@ -155,17 +146,6 @@
 #define GCC_USB0_PIPE_CLK				146
 #define GCC_USB0_SLEEP_CLK				147
 #define GCC_WCSS_AHB_CLK_SRC				148
-#define GCC_WCSS_AXIM_CLK				149
-#define GCC_WCSS_AXIS_CLK				150
-#define GCC_WCSS_DBG_IFC_APB_BDG_CLK			151
-#define GCC_WCSS_DBG_IFC_APB_CLK			152
-#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK			153
-#define GCC_WCSS_DBG_IFC_ATB_CLK			154
-#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK			155
-#define GCC_WCSS_DBG_IFC_NTS_CLK			156
-#define GCC_WCSS_ECAHB_CLK				157
-#define GCC_WCSS_MST_ASYNC_BDG_CLK			158
-#define GCC_WCSS_SLV_ASYNC_BDG_CLK			159
 #define GCC_XO_CLK					160
 #define GCC_XO_CLK_SRC					161
 #define GCC_XO_DIV4_CLK					162

include/dt-bindings/clock/qcom,ipq5424-gcc.h

diff --git a/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/include/dt-bindings/clock/qcom,ipq5424-gcc.h
new file mode 100644
index 0000000..755ce7a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5424-gcc.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
+
+#define GPLL0					0
+#define GPLL4					1
+#define GPLL2					2
+#define GPLL2_OUT_MAIN                          3
+#define GCC_SLEEP_CLK_SRC			4
+#define GCC_APSS_DBG_CLK                        5
+#define GCC_USB0_EUD_AT_CLK			6
+#define GCC_PCIE0_AXI_M_CLK_SRC			7
+#define GCC_PCIE0_AXI_M_CLK			8
+#define GCC_PCIE1_AXI_M_CLK_SRC			9
+#define GCC_PCIE1_AXI_M_CLK			10
+#define GCC_PCIE2_AXI_M_CLK_SRC			11
+#define GCC_PCIE2_AXI_M_CLK			12
+#define GCC_PCIE3_AXI_M_CLK_SRC			13
+#define GCC_PCIE3_AXI_M_CLK			14
+#define GCC_PCIE0_AXI_S_CLK_SRC			15
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK		16
+#define GCC_PCIE0_AXI_S_CLK			17
+#define GCC_PCIE1_AXI_S_CLK_SRC			18
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK		19
+#define GCC_PCIE1_AXI_S_CLK			20
+#define GCC_PCIE2_AXI_S_CLK_SRC			21
+#define GCC_PCIE2_AXI_S_BRIDGE_CLK		22
+#define GCC_PCIE2_AXI_S_CLK			23
+#define GCC_PCIE3_AXI_S_CLK_SRC			24
+#define GCC_PCIE3_AXI_S_BRIDGE_CLK		25
+#define GCC_PCIE3_AXI_S_CLK			26
+#define GCC_PCIE0_PIPE_CLK_SRC			27
+#define GCC_PCIE0_PIPE_CLK			28
+#define GCC_PCIE1_PIPE_CLK_SRC			29
+#define GCC_PCIE1_PIPE_CLK			30
+#define GCC_PCIE2_PIPE_CLK_SRC			31
+#define GCC_PCIE2_PIPE_CLK			32
+#define GCC_PCIE3_PIPE_CLK_SRC			33
+#define GCC_PCIE3_PIPE_CLK			34
+#define GCC_PCIE_AUX_CLK_SRC			35
+#define GCC_PCIE0_AUX_CLK			36
+#define GCC_PCIE1_AUX_CLK			37
+#define GCC_PCIE2_AUX_CLK			38
+#define GCC_PCIE3_AUX_CLK			39
+#define GCC_PCIE0_AHB_CLK			40
+#define GCC_PCIE1_AHB_CLK			41
+#define GCC_PCIE2_AHB_CLK			42
+#define GCC_PCIE3_AHB_CLK			43
+#define GCC_USB0_AUX_CLK_SRC			44
+#define GCC_USB0_AUX_CLK			45
+#define GCC_USB0_MASTER_CLK			46
+#define GCC_USB0_MOCK_UTMI_CLK_SRC		47
+#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC		48
+#define GCC_USB0_MOCK_UTMI_CLK			49
+#define GCC_USB0_PIPE_CLK_SRC			50
+#define GCC_USB0_PIPE_CLK			51
+#define GCC_USB0_PHY_CFG_AHB_CLK		52
+#define GCC_USB0_SLEEP_CLK			53
+#define GCC_SDCC1_APPS_CLK_SRC			54
+#define GCC_SDCC1_APPS_CLK			55
+#define GCC_SDCC1_ICE_CORE_CLK_SRC		56
+#define GCC_SDCC1_ICE_CORE_CLK			57
+#define GCC_SDCC1_AHB_CLK			58
+#define GCC_PCNOC_BFDCD_CLK_SRC			59
+#define GCC_NSSCFG_CLK				60
+#define GCC_NSSNOC_NSSCC_CLK			61
+#define GCC_NSSCC_CLK				62
+#define GCC_NSSNOC_PCNOC_1_CLK			63
+#define GCC_QPIC_AHB_CLK			64
+#define GCC_QPIC_CLK				65
+#define GCC_MDIO_AHB_CLK			66
+#define GCC_PRNG_AHB_CLK			67
+#define GCC_UNIPHY0_AHB_CLK			68
+#define GCC_UNIPHY1_AHB_CLK			69
+#define GCC_UNIPHY2_AHB_CLK			70
+#define GCC_CMN_12GPLL_AHB_CLK			71
+#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC		72
+#define GCC_NSSNOC_SNOC_CLK			73
+#define GCC_NSSNOC_SNOC_1_CLK			74
+#define GCC_WCSS_AHB_CLK_SRC			75
+#define GCC_QDSS_AT_CLK_SRC			76
+#define GCC_NSSNOC_ATB_CLK			77
+#define GCC_QDSS_AT_CLK				78
+#define GCC_QDSS_TSCTR_CLK_SRC			79
+#define GCC_NSS_TS_CLK				80
+#define GCC_QPIC_IO_MACRO_CLK_SRC		81
+#define GCC_QPIC_IO_MACRO_CLK			82
+#define GCC_LPASS_AXIM_CLK_SRC			83
+#define GCC_LPASS_CORE_AXIM_CLK			84
+#define GCC_LPASS_SWAY_CLK_SRC			85
+#define GCC_LPASS_SWAY_CLK			86
+#define GCC_CNOC_LPASS_CFG_CLK                  87
+#define GCC_SNOC_LPASS_CLK                      88
+#define GCC_ADSS_PWM_CLK_SRC			89
+#define GCC_ADSS_PWM_CLK			90
+#define GCC_XO_CLK_SRC				91
+#define GCC_NSSNOC_XO_DCD_CLK			92
+#define GCC_NSSNOC_QOSGEN_REF_CLK		93
+#define GCC_NSSNOC_TIMEOUT_REF_CLK		94
+#define GCC_UNIPHY0_SYS_CLK			95
+#define GCC_UNIPHY1_SYS_CLK			96
+#define GCC_UNIPHY2_SYS_CLK			97
+#define GCC_CMN_12GPLL_SYS_CLK			98
+#define GCC_UNIPHY_SYS_CLK_SRC			99
+#define GCC_NSS_TS_CLK_SRC			100
+#define GCC_ANOC_PCIE0_1LANE_M_CLK		101
+#define GCC_ANOC_PCIE1_1LANE_M_CLK		102
+#define GCC_ANOC_PCIE2_2LANE_M_CLK		103
+#define GCC_ANOC_PCIE3_2LANE_M_CLK		104
+#define GCC_CNOC_PCIE0_1LANE_S_CLK		105
+#define GCC_CNOC_PCIE1_1LANE_S_CLK		106
+#define GCC_CNOC_PCIE2_2LANE_S_CLK		107
+#define GCC_CNOC_PCIE3_2LANE_S_CLK		108
+#define GCC_CNOC_USB_CLK			109
+#define GCC_CNOC_WCSS_AHB_CLK			110
+#define GCC_QUPV3_AHB_MST_CLK			111
+#define GCC_QUPV3_AHB_SLV_CLK			112
+#define GCC_QUPV3_I2C0_CLK			113
+#define GCC_QUPV3_I2C1_CLK			114
+#define GCC_QUPV3_SPI0_CLK			115
+#define GCC_QUPV3_SPI1_CLK			116
+#define GCC_QUPV3_UART0_CLK			117
+#define GCC_QUPV3_UART1_CLK			118
+#define GCC_QPIC_CLK_SRC			119
+#define GCC_QUPV3_I2C0_CLK_SRC			120
+#define GCC_QUPV3_I2C1_CLK_SRC			121
+#define GCC_QUPV3_I2C0_DIV_CLK_SRC              122
+#define GCC_QUPV3_I2C1_DIV_CLK_SRC              123
+#define GCC_QUPV3_SPI0_CLK_SRC			124
+#define GCC_QUPV3_SPI1_CLK_SRC			125
+#define GCC_QUPV3_UART0_CLK_SRC			126
+#define GCC_QUPV3_UART1_CLK_SRC			127
+#define GCC_USB1_MASTER_CLK			128
+#define GCC_USB1_MOCK_UTMI_CLK_SRC		129
+#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC		130
+#define GCC_USB1_MOCK_UTMI_CLK			131
+#define GCC_USB1_SLEEP_CLK			132
+#define GCC_USB1_PHY_CFG_AHB_CLK		133
+#define GCC_USB0_MASTER_CLK_SRC			134
+#define GCC_QDSS_DAP_CLK			135
+#define GCC_PCIE0_RCHNG_CLK_SRC			136
+#define GCC_PCIE0_RCHNG_CLK			137
+#define GCC_PCIE1_RCHNG_CLK_SRC			138
+#define GCC_PCIE1_RCHNG_CLK			139
+#define GCC_PCIE2_RCHNG_CLK_SRC			140
+#define GCC_PCIE2_RCHNG_CLK			141
+#define GCC_PCIE3_RCHNG_CLK_SRC			142
+#define GCC_PCIE3_RCHNG_CLK			143
+#define GCC_IM_SLEEP_CLK			144
+
+#endif

include/dt-bindings/clock/qcom,ipq9574-gcc.h

diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 52123c5..f238aa4 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -132,16 +132,8 @@
 #define GCC_NSSNOC_SNOC_1_CLK				123
 #define GCC_QDSS_ETR_USB_CLK				124
 #define WCSS_AHB_CLK_SRC				125
-#define GCC_Q6_AHB_CLK					126
-#define GCC_Q6_AHB_S_CLK				127
-#define GCC_WCSS_ECAHB_CLK				128
-#define GCC_WCSS_ACMT_CLK				129
-#define GCC_SYS_NOC_WCSS_AHB_CLK			130
 #define WCSS_AXI_M_CLK_SRC				131
-#define GCC_ANOC_WCSS_AXI_M_CLK				132
 #define QDSS_AT_CLK_SRC					133
-#define GCC_Q6SS_ATBM_CLK				134
-#define GCC_WCSS_DBG_IFC_ATB_CLK			135
 #define GCC_NSSNOC_ATB_CLK				136
 #define GCC_QDSS_AT_CLK					137
 #define GCC_SYS_NOC_AT_CLK				138
@@ -154,27 +146,18 @@
 #define QDSS_TRACECLKIN_CLK_SRC				145
 #define GCC_QDSS_TRACECLKIN_CLK				146
 #define QDSS_TSCTR_CLK_SRC				147
-#define GCC_Q6_TSCTR_1TO2_CLK				148
-#define GCC_WCSS_DBG_IFC_NTS_CLK			149
 #define GCC_QDSS_TSCTR_DIV2_CLK				150
 #define GCC_QDSS_TS_CLK					151
 #define GCC_QDSS_TSCTR_DIV4_CLK				152
 #define GCC_NSS_TS_CLK					153
 #define GCC_QDSS_TSCTR_DIV8_CLK				154
 #define GCC_QDSS_TSCTR_DIV16_CLK			155
-#define GCC_Q6SS_PCLKDBG_CLK				156
-#define GCC_Q6SS_TRIG_CLK				157
-#define GCC_WCSS_DBG_IFC_APB_CLK			158
-#define GCC_WCSS_DBG_IFC_DAPBUS_CLK			159
 #define GCC_QDSS_DAP_CLK				160
 #define GCC_QDSS_APB2JTAG_CLK				161
 #define GCC_QDSS_TSCTR_DIV3_CLK				162
 #define QPIC_IO_MACRO_CLK_SRC				163
 #define GCC_QPIC_IO_MACRO_CLK                           164
 #define Q6_AXI_CLK_SRC					165
-#define GCC_Q6_AXIM_CLK					166
-#define GCC_WCSS_Q6_TBU_CLK				167
-#define GCC_MEM_NOC_Q6_AXI_CLK				168
 #define Q6_AXIM2_CLK_SRC				169
 #define NSSNOC_MEMNOC_BFDCD_CLK_SRC			170
 #define GCC_NSSNOC_MEMNOC_CLK				171
@@ -199,7 +182,6 @@
 #define GCC_UNIPHY2_SYS_CLK				190
 #define GCC_CMN_12GPLL_SYS_CLK				191
 #define GCC_NSSNOC_XO_DCD_CLK				192
-#define GCC_Q6SS_BOOT_CLK				193
 #define UNIPHY_SYS_CLK_SRC				194
 #define NSS_TS_CLK_SRC					195
 #define GCC_ANOC_PCIE0_1LANE_M_CLK			196

include/dt-bindings/clock/qcom,qcs8300-gcc.h

diff --git a/include/dt-bindings/clock/qcom,qcs8300-gcc.h b/include/dt-bindings/clock/qcom,qcs8300-gcc.h
new file mode 100644
index 0000000..a0083b1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs8300-gcc.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS8300_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS8300_H
+
+/* GCC clocks */
+#define GCC_GPLL0						0
+#define GCC_GPLL0_OUT_EVEN					1
+#define GCC_GPLL1						2
+#define GCC_GPLL4						3
+#define GCC_GPLL7						4
+#define GCC_GPLL9						5
+#define GCC_AGGRE_NOC_QUPV3_AXI_CLK				6
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				7
+#define GCC_AGGRE_USB2_PRIM_AXI_CLK				8
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				9
+#define GCC_AHB2PHY0_CLK					10
+#define GCC_AHB2PHY2_CLK					11
+#define GCC_AHB2PHY3_CLK					12
+#define GCC_BOOT_ROM_AHB_CLK					13
+#define GCC_CAMERA_AHB_CLK					14
+#define GCC_CAMERA_HF_AXI_CLK					15
+#define GCC_CAMERA_SF_AXI_CLK					16
+#define GCC_CAMERA_THROTTLE_XO_CLK				17
+#define GCC_CAMERA_XO_CLK					18
+#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK				19
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				20
+#define GCC_DDRSS_GPU_AXI_CLK					21
+#define GCC_DISP_AHB_CLK					22
+#define GCC_DISP_HF_AXI_CLK					23
+#define GCC_DISP_XO_CLK						24
+#define GCC_EDP_REF_CLKREF_EN					25
+#define GCC_EMAC0_AXI_CLK					26
+#define GCC_EMAC0_PHY_AUX_CLK					27
+#define GCC_EMAC0_PHY_AUX_CLK_SRC				28
+#define GCC_EMAC0_PTP_CLK					29
+#define GCC_EMAC0_PTP_CLK_SRC					30
+#define GCC_EMAC0_RGMII_CLK					31
+#define GCC_EMAC0_RGMII_CLK_SRC					32
+#define GCC_EMAC0_SLV_AHB_CLK					33
+#define GCC_GP1_CLK						34
+#define GCC_GP1_CLK_SRC						35
+#define GCC_GP2_CLK						36
+#define GCC_GP2_CLK_SRC						37
+#define GCC_GP3_CLK						38
+#define GCC_GP3_CLK_SRC						39
+#define GCC_GP4_CLK						40
+#define GCC_GP4_CLK_SRC						41
+#define GCC_GP5_CLK						42
+#define GCC_GP5_CLK_SRC						43
+#define GCC_GPU_CFG_AHB_CLK					44
+#define GCC_GPU_GPLL0_CLK_SRC					45
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				46
+#define GCC_GPU_MEMNOC_GFX_CENTER_PIPELINE_CLK			47
+#define GCC_GPU_MEMNOC_GFX_CLK					48
+#define GCC_GPU_SNOC_DVM_GFX_CLK				49
+#define GCC_GPU_TCU_THROTTLE_AHB_CLK				50
+#define GCC_GPU_TCU_THROTTLE_CLK				51
+#define GCC_PCIE_0_AUX_CLK					52
+#define GCC_PCIE_0_AUX_CLK_SRC					53
+#define GCC_PCIE_0_CFG_AHB_CLK					54
+#define GCC_PCIE_0_MSTR_AXI_CLK					55
+#define GCC_PCIE_0_PHY_AUX_CLK					56
+#define GCC_PCIE_0_PHY_AUX_CLK_SRC				57
+#define GCC_PCIE_0_PHY_RCHNG_CLK				58
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				59
+#define GCC_PCIE_0_PIPE_CLK					60
+#define GCC_PCIE_0_PIPE_CLK_SRC					61
+#define GCC_PCIE_0_PIPE_DIV_CLK_SRC				62
+#define GCC_PCIE_0_PIPEDIV2_CLK					63
+#define GCC_PCIE_0_SLV_AXI_CLK					64
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				65
+#define GCC_PCIE_1_AUX_CLK					66
+#define GCC_PCIE_1_AUX_CLK_SRC					67
+#define GCC_PCIE_1_CFG_AHB_CLK					68
+#define GCC_PCIE_1_MSTR_AXI_CLK					69
+#define GCC_PCIE_1_PHY_AUX_CLK					70
+#define GCC_PCIE_1_PHY_AUX_CLK_SRC				71
+#define GCC_PCIE_1_PHY_RCHNG_CLK				72
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				73
+#define GCC_PCIE_1_PIPE_CLK					74
+#define GCC_PCIE_1_PIPE_CLK_SRC					75
+#define GCC_PCIE_1_PIPE_DIV_CLK_SRC				76
+#define GCC_PCIE_1_PIPEDIV2_CLK					77
+#define GCC_PCIE_1_SLV_AXI_CLK					78
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				79
+#define GCC_PCIE_CLKREF_EN					80
+#define GCC_PCIE_THROTTLE_CFG_CLK				81
+#define GCC_PDM2_CLK						82
+#define GCC_PDM2_CLK_SRC					83
+#define GCC_PDM_AHB_CLK						84
+#define GCC_PDM_XO4_CLK						85
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				86
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				87
+#define GCC_QMIP_DISP_AHB_CLK					88
+#define GCC_QMIP_DISP_ROT_AHB_CLK				89
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				90
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				91
+#define GCC_QMIP_VIDEO_VCPU_AHB_CLK				92
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				93
+#define GCC_QUPV3_WRAP0_CORE_CLK				94
+#define GCC_QUPV3_WRAP0_S0_CLK					95
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				96
+#define GCC_QUPV3_WRAP0_S1_CLK					97
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				98
+#define GCC_QUPV3_WRAP0_S2_CLK					99
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				100
+#define GCC_QUPV3_WRAP0_S3_CLK					101
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				102
+#define GCC_QUPV3_WRAP0_S4_CLK					103
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				104
+#define GCC_QUPV3_WRAP0_S5_CLK					105
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				106
+#define GCC_QUPV3_WRAP0_S6_CLK					107
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				108
+#define GCC_QUPV3_WRAP0_S7_CLK					109
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				110
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				111
+#define GCC_QUPV3_WRAP1_CORE_CLK				112
+#define GCC_QUPV3_WRAP1_S0_CLK					113
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				114
+#define GCC_QUPV3_WRAP1_S1_CLK					115
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				116
+#define GCC_QUPV3_WRAP1_S2_CLK					117
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				118
+#define GCC_QUPV3_WRAP1_S3_CLK					119
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				120
+#define GCC_QUPV3_WRAP1_S4_CLK					121
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				122
+#define GCC_QUPV3_WRAP1_S5_CLK					123
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				124
+#define GCC_QUPV3_WRAP1_S6_CLK					125
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				126
+#define GCC_QUPV3_WRAP1_S7_CLK					127
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				128
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK				129
+#define GCC_QUPV3_WRAP3_CORE_CLK				130
+#define GCC_QUPV3_WRAP3_QSPI_CLK				131
+#define GCC_QUPV3_WRAP3_S0_CLK					132
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC				133
+#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC				134
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				135
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				136
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				137
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				138
+#define GCC_QUPV3_WRAP_3_M_AHB_CLK				139
+#define GCC_QUPV3_WRAP_3_S_AHB_CLK				140
+#define GCC_SDCC1_AHB_CLK					141
+#define GCC_SDCC1_APPS_CLK					142
+#define GCC_SDCC1_APPS_CLK_SRC					143
+#define GCC_SDCC1_ICE_CORE_CLK					144
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				145
+#define GCC_SGMI_CLKREF_EN					146
+#define GCC_UFS_PHY_AHB_CLK					147
+#define GCC_UFS_PHY_AXI_CLK					148
+#define GCC_UFS_PHY_AXI_CLK_SRC					149
+#define GCC_UFS_PHY_ICE_CORE_CLK				150
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				151
+#define GCC_UFS_PHY_PHY_AUX_CLK					152
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				153
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				154
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				155
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				156
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				157
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				158
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				159
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				160
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				161
+#define GCC_USB20_MASTER_CLK					162
+#define GCC_USB20_MASTER_CLK_SRC				163
+#define GCC_USB20_MOCK_UTMI_CLK					164
+#define GCC_USB20_MOCK_UTMI_CLK_SRC				165
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC			166
+#define GCC_USB20_SLEEP_CLK					167
+#define GCC_USB30_PRIM_MASTER_CLK				168
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				169
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				170
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			171
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		172
+#define GCC_USB30_PRIM_SLEEP_CLK				173
+#define GCC_USB3_PRIM_PHY_AUX_CLK				174
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				175
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				176
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				177
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				178
+#define GCC_USB_CLKREF_EN					179
+#define GCC_VIDEO_AHB_CLK					180
+#define GCC_VIDEO_AXI0_CLK					181
+#define GCC_VIDEO_AXI1_CLK					182
+#define GCC_VIDEO_XO_CLK					183
+
+/* GCC power domains */
+#define GCC_EMAC0_GDSC						0
+#define GCC_PCIE_0_GDSC						1
+#define GCC_PCIE_1_GDSC						2
+#define GCC_UFS_PHY_GDSC					3
+#define GCC_USB20_PRIM_GDSC					4
+#define GCC_USB30_PRIM_GDSC					5
+
+/* GCC resets */
+#define GCC_EMAC0_BCR						0
+#define GCC_PCIE_0_BCR						1
+#define GCC_PCIE_0_LINK_DOWN_BCR				2
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				3
+#define GCC_PCIE_0_PHY_BCR					4
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			5
+#define GCC_PCIE_1_BCR						6
+#define GCC_PCIE_1_LINK_DOWN_BCR				7
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				8
+#define GCC_PCIE_1_PHY_BCR					9
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			10
+#define GCC_SDCC1_BCR						11
+#define GCC_UFS_PHY_BCR						12
+#define GCC_USB20_PRIM_BCR					13
+#define GCC_USB2_PHY_PRIM_BCR					14
+#define GCC_USB2_PHY_SEC_BCR					15
+#define GCC_USB30_PRIM_BCR					16
+#define GCC_USB3_DP_PHY_PRIM_BCR				17
+#define GCC_USB3_PHY_PRIM_BCR					18
+#define GCC_USB3_PHY_TERT_BCR					19
+#define GCC_USB3_UNIPHY_MP0_BCR					20
+#define GCC_USB3_UNIPHY_MP1_BCR					21
+#define GCC_USB3PHY_PHY_PRIM_BCR				22
+#define GCC_USB3UNIPHY_PHY_MP0_BCR				23
+#define GCC_USB3UNIPHY_PHY_MP1_BCR				24
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				25
+#define GCC_VIDEO_BCR						26
+#define GCC_VIDEO_AXI0_CLK_ARES					27
+#define GCC_VIDEO_AXI1_CLK_ARES					28
+
+#endif

include/dt-bindings/clock/qcom,sa8775p-camcc.h

diff --git a/include/dt-bindings/clock/qcom,sa8775p-camcc.h b/include/dt-bindings/clock/qcom,sa8775p-camcc.h
new file mode 100644
index 0000000..38531ac
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sa8775p-camcc.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
+
+/* CAM_CC clocks */
+#define CAM_CC_CAMNOC_AXI_CLK					0
+#define CAM_CC_CAMNOC_AXI_CLK_SRC				1
+#define CAM_CC_CAMNOC_DCD_XO_CLK				2
+#define CAM_CC_CAMNOC_XO_CLK					3
+#define CAM_CC_CCI_0_CLK					4
+#define CAM_CC_CCI_0_CLK_SRC					5
+#define CAM_CC_CCI_1_CLK					6
+#define CAM_CC_CCI_1_CLK_SRC					7
+#define CAM_CC_CCI_2_CLK					8
+#define CAM_CC_CCI_2_CLK_SRC					9
+#define CAM_CC_CCI_3_CLK					10
+#define CAM_CC_CCI_3_CLK_SRC					11
+#define CAM_CC_CORE_AHB_CLK					12
+#define CAM_CC_CPAS_AHB_CLK					13
+#define CAM_CC_CPAS_FAST_AHB_CLK				14
+#define CAM_CC_CPAS_IFE_0_CLK					15
+#define CAM_CC_CPAS_IFE_1_CLK					16
+#define CAM_CC_CPAS_IFE_LITE_CLK				17
+#define CAM_CC_CPAS_IPE_CLK					18
+#define CAM_CC_CPAS_SFE_LITE_0_CLK				19
+#define CAM_CC_CPAS_SFE_LITE_1_CLK				20
+#define CAM_CC_CPHY_RX_CLK_SRC					21
+#define CAM_CC_CSI0PHYTIMER_CLK					22
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				23
+#define CAM_CC_CSI1PHYTIMER_CLK					24
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				25
+#define CAM_CC_CSI2PHYTIMER_CLK					26
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				27
+#define CAM_CC_CSI3PHYTIMER_CLK					28
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC				29
+#define CAM_CC_CSID_CLK						30
+#define CAM_CC_CSID_CLK_SRC					31
+#define CAM_CC_CSID_CSIPHY_RX_CLK				32
+#define CAM_CC_CSIPHY0_CLK					33
+#define CAM_CC_CSIPHY1_CLK					34
+#define CAM_CC_CSIPHY2_CLK					35
+#define CAM_CC_CSIPHY3_CLK					36
+#define CAM_CC_FAST_AHB_CLK_SRC					37
+#define CAM_CC_GDSC_CLK						38
+#define CAM_CC_ICP_AHB_CLK					39
+#define CAM_CC_ICP_CLK						40
+#define CAM_CC_ICP_CLK_SRC					41
+#define CAM_CC_IFE_0_CLK					42
+#define CAM_CC_IFE_0_CLK_SRC					43
+#define CAM_CC_IFE_0_FAST_AHB_CLK				44
+#define CAM_CC_IFE_1_CLK					45
+#define CAM_CC_IFE_1_CLK_SRC					46
+#define CAM_CC_IFE_1_FAST_AHB_CLK				47
+#define CAM_CC_IFE_LITE_AHB_CLK					48
+#define CAM_CC_IFE_LITE_CLK					49
+#define CAM_CC_IFE_LITE_CLK_SRC					50
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK				51
+#define CAM_CC_IFE_LITE_CSID_CLK				52
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC				53
+#define CAM_CC_IPE_AHB_CLK					54
+#define CAM_CC_IPE_CLK						55
+#define CAM_CC_IPE_CLK_SRC					56
+#define CAM_CC_IPE_FAST_AHB_CLK					57
+#define CAM_CC_MCLK0_CLK					58
+#define CAM_CC_MCLK0_CLK_SRC					59
+#define CAM_CC_MCLK1_CLK					60
+#define CAM_CC_MCLK1_CLK_SRC					61
+#define CAM_CC_MCLK2_CLK					62
+#define CAM_CC_MCLK2_CLK_SRC					63
+#define CAM_CC_MCLK3_CLK					64
+#define CAM_CC_MCLK3_CLK_SRC					65
+#define CAM_CC_PLL0						66
+#define CAM_CC_PLL0_OUT_EVEN					67
+#define CAM_CC_PLL0_OUT_ODD					68
+#define CAM_CC_PLL2						69
+#define CAM_CC_PLL3						70
+#define CAM_CC_PLL3_OUT_EVEN					71
+#define CAM_CC_PLL4						72
+#define CAM_CC_PLL4_OUT_EVEN					73
+#define CAM_CC_PLL5						74
+#define CAM_CC_PLL5_OUT_EVEN					75
+#define CAM_CC_SFE_LITE_0_CLK					76
+#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK				77
+#define CAM_CC_SFE_LITE_1_CLK					78
+#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK				79
+#define CAM_CC_SLEEP_CLK					80
+#define CAM_CC_SLEEP_CLK_SRC					81
+#define CAM_CC_SLOW_AHB_CLK_SRC					82
+#define CAM_CC_SM_OBS_CLK					83
+#define CAM_CC_XO_CLK_SRC					84
+#define CAM_CC_QDSS_DEBUG_XO_CLK				85
+
+/* CAM_CC power domains */
+#define CAM_CC_TITAN_TOP_GDSC					0
+
+/* CAM_CC resets */
+#define CAM_CC_ICP_BCR						0
+#define CAM_CC_IFE_0_BCR					1
+#define CAM_CC_IFE_1_BCR					2
+#define CAM_CC_IPE_0_BCR					3
+#define CAM_CC_SFE_LITE_0_BCR					4
+#define CAM_CC_SFE_LITE_1_BCR					5
+
+#endif

include/dt-bindings/clock/qcom,sa8775p-dispcc.h

diff --git a/include/dt-bindings/clock/qcom,sa8775p-dispcc.h b/include/dt-bindings/clock/qcom,sa8775p-dispcc.h
new file mode 100644
index 0000000..e2049e5
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sa8775p-dispcc.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
+
+/* DISP_CC_0/1 clocks */
+#define MDSS_DISP_CC_MDSS_AHB1_CLK				0
+#define MDSS_DISP_CC_MDSS_AHB_CLK				1
+#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC				2
+#define MDSS_DISP_CC_MDSS_BYTE0_CLK				3
+#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC				4
+#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC			5
+#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK			6
+#define MDSS_DISP_CC_MDSS_BYTE1_CLK				7
+#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC				8
+#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC			9
+#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK			10
+#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK				11
+#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC			12
+#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK			13
+#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC			14
+#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK			15
+#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC			16
+#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC		17
+#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			18
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK			19
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			20
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK			21
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			22
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK			23
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC			24
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK			25
+#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC			26
+#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK	27
+#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK				28
+#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC			29
+#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK			30
+#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC			31
+#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK			32
+#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC			33
+#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC		34
+#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			35
+#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK			36
+#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			37
+#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK			38
+#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			39
+#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK	40
+#define MDSS_DISP_CC_MDSS_ESC0_CLK				41
+#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC				42
+#define MDSS_DISP_CC_MDSS_ESC1_CLK				43
+#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC				44
+#define MDSS_DISP_CC_MDSS_MDP1_CLK				45
+#define MDSS_DISP_CC_MDSS_MDP_CLK				46
+#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC				47
+#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK				48
+#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK				49
+#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK			50
+#define MDSS_DISP_CC_MDSS_PCLK0_CLK				51
+#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC				52
+#define MDSS_DISP_CC_MDSS_PCLK1_CLK				53
+#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC				54
+#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK			55
+#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK				56
+#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK			57
+#define MDSS_DISP_CC_MDSS_VSYNC1_CLK				58
+#define MDSS_DISP_CC_MDSS_VSYNC_CLK				59
+#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC				60
+#define MDSS_DISP_CC_PLL0					61
+#define MDSS_DISP_CC_PLL1					62
+#define MDSS_DISP_CC_SLEEP_CLK					63
+#define MDSS_DISP_CC_SLEEP_CLK_SRC				64
+#define MDSS_DISP_CC_SM_OBS_CLK					65
+#define MDSS_DISP_CC_XO_CLK					66
+#define MDSS_DISP_CC_XO_CLK_SRC					67
+
+/* DISP_CC_0/1 power domains */
+#define MDSS_DISP_CC_MDSS_CORE_GDSC				0
+#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC			1
+
+/* DISP_CC_0/1 resets */
+#define MDSS_DISP_CC_MDSS_CORE_BCR				0
+#define MDSS_DISP_CC_MDSS_RSCC_BCR				1
+
+#endif

include/dt-bindings/clock/qcom,sa8775p-videocc.h

diff --git a/include/dt-bindings/clock/qcom,sa8775p-videocc.h b/include/dt-bindings/clock/qcom,sa8775p-videocc.h
new file mode 100644
index 0000000..e6325f6
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sa8775p-videocc.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK					0
+#define VIDEO_CC_AHB_CLK_SRC					1
+#define VIDEO_CC_MVS0_CLK					2
+#define VIDEO_CC_MVS0_CLK_SRC					3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC				4
+#define VIDEO_CC_MVS0C_CLK					5
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				6
+#define VIDEO_CC_MVS1_CLK					7
+#define VIDEO_CC_MVS1_CLK_SRC					8
+#define VIDEO_CC_MVS1_DIV_CLK_SRC				9
+#define VIDEO_CC_MVS1C_CLK					10
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC				11
+#define VIDEO_CC_PLL_LOCK_MONITOR_CLK				12
+#define VIDEO_CC_SLEEP_CLK					13
+#define VIDEO_CC_SLEEP_CLK_SRC					14
+#define VIDEO_CC_SM_DIV_CLK_SRC					15
+#define VIDEO_CC_SM_OBS_CLK					16
+#define VIDEO_CC_XO_CLK						17
+#define VIDEO_CC_XO_CLK_SRC					18
+#define VIDEO_PLL0						19
+#define VIDEO_PLL1						20
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0C_GDSC					0
+#define VIDEO_CC_MVS0_GDSC					1
+#define VIDEO_CC_MVS1C_GDSC					2
+#define VIDEO_CC_MVS1_GDSC					3
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR					0
+#define VIDEO_CC_MVS0_BCR					1
+#define VIDEO_CC_MVS0C_CLK_ARES					2
+#define VIDEO_CC_MVS0C_BCR					3
+#define VIDEO_CC_MVS1_BCR					4
+#define VIDEO_CC_MVS1C_CLK_ARES					5
+#define VIDEO_CC_MVS1C_BCR					6
+
+#endif

include/dt-bindings/clock/qcom,sar2130p-gcc.h

diff --git a/include/dt-bindings/clock/qcom,sar2130p-gcc.h b/include/dt-bindings/clock/qcom,sar2130p-gcc.h
new file mode 100644
index 0000000..69d2dd2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sar2130p-gcc.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H
+
+/* GCC clocks */
+#define GCC_GPLL0						0
+#define GCC_GPLL0_OUT_EVEN					1
+#define GCC_GPLL1						2
+#define GCC_GPLL9						3
+#define GCC_GPLL9_OUT_EVEN					4
+#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK				5
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				6
+#define GCC_BOOT_ROM_AHB_CLK					7
+#define GCC_CAMERA_AHB_CLK					8
+#define GCC_CAMERA_HF_AXI_CLK					9
+#define GCC_CAMERA_SF_AXI_CLK					10
+#define GCC_CAMERA_XO_CLK					11
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				12
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				13
+#define GCC_DDRSS_GPU_AXI_CLK					14
+#define GCC_DDRSS_PCIE_SF_CLK					15
+#define GCC_DISP_AHB_CLK					16
+#define GCC_DISP_HF_AXI_CLK					17
+#define GCC_GP1_CLK						18
+#define GCC_GP1_CLK_SRC						19
+#define GCC_GP2_CLK						20
+#define GCC_GP2_CLK_SRC						21
+#define GCC_GP3_CLK						22
+#define GCC_GP3_CLK_SRC						23
+#define GCC_GPU_CFG_AHB_CLK					24
+#define GCC_GPU_GPLL0_CLK_SRC					25
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				26
+#define GCC_GPU_MEMNOC_GFX_CLK					27
+#define GCC_GPU_SNOC_DVM_GFX_CLK				28
+#define GCC_IRIS_SS_HF_AXI1_CLK					29
+#define GCC_IRIS_SS_SPD_AXI1_CLK				30
+#define GCC_PCIE_0_AUX_CLK					31
+#define GCC_PCIE_0_AUX_CLK_SRC					32
+#define GCC_PCIE_0_CFG_AHB_CLK					33
+#define GCC_PCIE_0_MSTR_AXI_CLK					34
+#define GCC_PCIE_0_PHY_RCHNG_CLK				35
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				36
+#define GCC_PCIE_0_PIPE_CLK					37
+#define GCC_PCIE_0_PIPE_CLK_SRC					38
+#define GCC_PCIE_0_SLV_AXI_CLK					39
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				40
+#define GCC_PCIE_1_AUX_CLK					41
+#define GCC_PCIE_1_AUX_CLK_SRC					42
+#define GCC_PCIE_1_CFG_AHB_CLK					43
+#define GCC_PCIE_1_MSTR_AXI_CLK					44
+#define GCC_PCIE_1_PHY_RCHNG_CLK				45
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				46
+#define GCC_PCIE_1_PIPE_CLK					47
+#define GCC_PCIE_1_PIPE_CLK_SRC					48
+#define GCC_PCIE_1_SLV_AXI_CLK					49
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				50
+#define GCC_PDM2_CLK						51
+#define GCC_PDM2_CLK_SRC					52
+#define GCC_PDM_AHB_CLK						53
+#define GCC_PDM_XO4_CLK						54
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				55
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				56
+#define GCC_QMIP_GPU_AHB_CLK					57
+#define GCC_QMIP_PCIE_AHB_CLK					58
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				59
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				60
+#define GCC_QMIP_VIDEO_LSR_AHB_CLK				61
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				62
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				63
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				64
+#define GCC_QUPV3_WRAP0_CORE_CLK				65
+#define GCC_QUPV3_WRAP0_S0_CLK					66
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				67
+#define GCC_QUPV3_WRAP0_S1_CLK					68
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				69
+#define GCC_QUPV3_WRAP0_S2_CLK					70
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				71
+#define GCC_QUPV3_WRAP0_S3_CLK					72
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				73
+#define GCC_QUPV3_WRAP0_S4_CLK					74
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				75
+#define GCC_QUPV3_WRAP0_S5_CLK					76
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				77
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				78
+#define GCC_QUPV3_WRAP1_CORE_CLK				79
+#define GCC_QUPV3_WRAP1_S0_CLK					80
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				81
+#define GCC_QUPV3_WRAP1_S1_CLK					82
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				83
+#define GCC_QUPV3_WRAP1_S2_CLK					84
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				85
+#define GCC_QUPV3_WRAP1_S3_CLK					86
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				87
+#define GCC_QUPV3_WRAP1_S4_CLK					88
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				89
+#define GCC_QUPV3_WRAP1_S5_CLK					90
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				91
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				92
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				93
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				94
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				95
+#define GCC_SDCC1_AHB_CLK					96
+#define GCC_SDCC1_APPS_CLK					97
+#define GCC_SDCC1_APPS_CLK_SRC					98
+#define GCC_SDCC1_ICE_CORE_CLK					99
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				100
+#define GCC_USB30_PRIM_MASTER_CLK				101
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				102
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				103
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			104
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		105
+#define GCC_USB30_PRIM_SLEEP_CLK				106
+#define GCC_USB3_PRIM_PHY_AUX_CLK				107
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				108
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				109
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				110
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				111
+#define GCC_VIDEO_AHB_CLK					112
+#define GCC_VIDEO_AXI0_CLK					113
+#define GCC_VIDEO_AXI1_CLK					114
+#define GCC_VIDEO_XO_CLK					115
+#define GCC_GPLL4						116
+#define GCC_GPLL5						117
+#define GCC_GPLL7						118
+#define GCC_DDRSS_SPAD_CLK					119
+#define GCC_DDRSS_SPAD_CLK_SRC					120
+#define GCC_VIDEO_AXI0_SREG					121
+#define GCC_VIDEO_AXI1_SREG					122
+#define GCC_IRIS_SS_HF_AXI1_SREG				123
+#define GCC_IRIS_SS_SPD_AXI1_SREG				124
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_GPU_BCR						2
+#define GCC_PCIE_0_BCR						3
+#define GCC_PCIE_0_LINK_DOWN_BCR				4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5
+#define GCC_PCIE_0_PHY_BCR					6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7
+#define GCC_PCIE_1_BCR						8
+#define GCC_PCIE_1_LINK_DOWN_BCR				9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10
+#define GCC_PCIE_1_PHY_BCR					11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12
+#define GCC_PCIE_PHY_BCR					13
+#define GCC_PCIE_PHY_CFG_AHB_BCR				14
+#define GCC_PCIE_PHY_COM_BCR					15
+#define GCC_PDM_BCR						16
+#define GCC_QUPV3_WRAPPER_0_BCR					17
+#define GCC_QUPV3_WRAPPER_1_BCR					18
+#define GCC_QUSB2PHY_PRIM_BCR					19
+#define GCC_QUSB2PHY_SEC_BCR					20
+#define GCC_SDCC1_BCR						21
+#define GCC_USB30_PRIM_BCR					22
+#define GCC_USB3_DP_PHY_PRIM_BCR				23
+#define GCC_USB3_DP_PHY_SEC_BCR					24
+#define GCC_USB3_PHY_PRIM_BCR					25
+#define GCC_USB3_PHY_SEC_BCR					26
+#define GCC_USB3PHY_PHY_PRIM_BCR				27
+#define GCC_USB3PHY_PHY_SEC_BCR					28
+#define GCC_VIDEO_AXI0_CLK_ARES					29
+#define GCC_VIDEO_AXI1_CLK_ARES					30
+#define GCC_VIDEO_BCR						31
+#define GCC_IRIS_SS_HF_AXI_CLK_ARES				32
+#define GCC_IRIS_SS_SPD_AXI_CLK_ARES				33
+#define GCC_DDRSS_SPAD_CLK_ARES					34
+
+/* GCC power domains */
+#define PCIE_0_GDSC						0
+#define PCIE_0_PHY_GDSC						1
+#define PCIE_1_GDSC						2
+#define PCIE_1_PHY_GDSC						3
+#define USB30_PRIM_GDSC						4
+#define USB3_PHY_GDSC						5
+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_HF0_GDSC			6
+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_SF0_GDSC			7
+#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC				8
+#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC				9
+
+#endif

include/dt-bindings/clock/qcom,sar2130p-gpucc.h

diff --git a/include/dt-bindings/clock/qcom,sar2130p-gpucc.h b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h
new file mode 100644
index 0000000..a220436
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sar2130p-gpucc.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK				0
+#define GPU_CC_CRC_AHB_CLK			1
+#define GPU_CC_CX_FF_CLK			2
+#define GPU_CC_CX_GMU_CLK			3
+#define GPU_CC_CXO_AON_CLK			4
+#define GPU_CC_CXO_CLK				5
+#define GPU_CC_FF_CLK_SRC			6
+#define GPU_CC_GMU_CLK_SRC			7
+#define GPU_CC_GX_GMU_CLK			8
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		9
+#define GPU_CC_HUB_AON_CLK			10
+#define GPU_CC_HUB_CLK_SRC			11
+#define GPU_CC_HUB_CX_INT_CLK			12
+#define GPU_CC_MEMNOC_GFX_CLK			13
+#define GPU_CC_PLL0				14
+#define GPU_CC_PLL1				15
+#define GPU_CC_SLEEP_CLK			16
+
+/* GDSCs */
+#define GPU_GX_GDSC				0
+#define GPU_CX_GDSC				1
+
+#endif

include/dt-bindings/clock/r9a08g045-cpg.h

diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h
index 8281e9c..311521f 100644
--- a/include/dt-bindings/clock/r9a08g045-cpg.h
+++ b/include/dt-bindings/clock/r9a08g045-cpg.h
@@ -308,5 +308,6 @@
 #define R9A08G045_PD_DDR		64
 #define R9A08G045_PD_TZCDDR		65
 #define R9A08G045_PD_OTFDE_DDR		66
+#define R9A08G045_PD_RTC		67
 
 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */

include/dt-bindings/clock/renesas,r9a08g045-vbattb.h

diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
new file mode 100644
index 0000000..67774ea
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
+#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
+
+#define VBATTB_XC		0
+#define VBATTB_XBYP		1
+#define VBATTB_MUX		2
+#define VBATTB_VBATTCLK		3
+
+#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */

include/dt-bindings/clock/samsung,exynos8895.h

diff --git a/include/dt-bindings/clock/samsung,exynos8895.h b/include/dt-bindings/clock/samsung,exynos8895.h
new file mode 100644
index 0000000..27998c5
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos8895.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ *
+ * Device Tree binding constants for Exynos8895 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS8895_H
+#define _DT_BINDINGS_CLOCK_EXYNOS8895_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL			1
+#define CLK_FOUT_SHARED1_PLL			2
+#define CLK_FOUT_SHARED2_PLL			3
+#define CLK_FOUT_SHARED3_PLL			4
+#define CLK_FOUT_SHARED4_PLL			5
+#define CLK_MOUT_PLL_SHARED0			6
+#define CLK_MOUT_PLL_SHARED1			7
+#define CLK_MOUT_PLL_SHARED2			8
+#define CLK_MOUT_PLL_SHARED3			9
+#define CLK_MOUT_PLL_SHARED4			10
+#define CLK_MOUT_CP2AP_MIF_CLK_USER		11
+#define CLK_MOUT_CMU_ABOX_CPUABOX		12
+#define CLK_MOUT_CMU_APM_BUS			13
+#define CLK_MOUT_CMU_BUS1_BUS			14
+#define CLK_MOUT_CMU_BUSC_BUS			15
+#define CLK_MOUT_CMU_BUSC_BUSPHSI2C		16
+#define CLK_MOUT_CMU_CAM_BUS			17
+#define CLK_MOUT_CMU_CAM_TPU0			18
+#define CLK_MOUT_CMU_CAM_TPU1			19
+#define CLK_MOUT_CMU_CAM_VRA			20
+#define CLK_MOUT_CMU_CIS_CLK0			21
+#define CLK_MOUT_CMU_CIS_CLK1			22
+#define CLK_MOUT_CMU_CIS_CLK2			23
+#define CLK_MOUT_CMU_CIS_CLK3			24
+#define CLK_MOUT_CMU_CORE_BUS			25
+#define CLK_MOUT_CMU_CPUCL0_SWITCH		26
+#define CLK_MOUT_CMU_CPUCL1_SWITCH		27
+#define CLK_MOUT_CMU_DBG_BUS			28
+#define CLK_MOUT_CMU_DCAM_BUS			29
+#define CLK_MOUT_CMU_DCAM_IMGD			30
+#define CLK_MOUT_CMU_DPU_BUS			31
+#define CLK_MOUT_CMU_DROOPDETECTOR		32
+#define CLK_MOUT_CMU_DSP_BUS			33
+#define CLK_MOUT_CMU_FSYS0_BUS			34
+#define CLK_MOUT_CMU_FSYS0_DPGTC		35
+#define CLK_MOUT_CMU_FSYS0_MMC_EMBD		36
+#define CLK_MOUT_CMU_FSYS0_UFS_EMBD		37
+#define CLK_MOUT_CMU_FSYS0_USBDRD30		38
+#define CLK_MOUT_CMU_FSYS1_BUS			39
+#define CLK_MOUT_CMU_FSYS1_MMC_CARD		40
+#define CLK_MOUT_CMU_FSYS1_PCIE			41
+#define CLK_MOUT_CMU_FSYS1_UFS_CARD		42
+#define CLK_MOUT_CMU_G2D_G2D			43
+#define CLK_MOUT_CMU_G2D_JPEG			44
+#define CLK_MOUT_CMU_HPM			45
+#define CLK_MOUT_CMU_IMEM_BUS			46
+#define CLK_MOUT_CMU_ISPHQ_BUS			47
+#define CLK_MOUT_CMU_ISPLP_BUS			48
+#define CLK_MOUT_CMU_IVA_BUS			49
+#define CLK_MOUT_CMU_MFC_BUS			50
+#define CLK_MOUT_CMU_MIF_SWITCH			51
+#define CLK_MOUT_CMU_PERIC0_BUS			52
+#define CLK_MOUT_CMU_PERIC0_UART_DBG		53
+#define CLK_MOUT_CMU_PERIC0_USI00		54
+#define CLK_MOUT_CMU_PERIC0_USI01		55
+#define CLK_MOUT_CMU_PERIC0_USI02		56
+#define CLK_MOUT_CMU_PERIC0_USI03		57
+#define CLK_MOUT_CMU_PERIC1_BUS			58
+#define CLK_MOUT_CMU_PERIC1_SPEEDY2		59
+#define CLK_MOUT_CMU_PERIC1_SPI_CAM0		60
+#define CLK_MOUT_CMU_PERIC1_SPI_CAM1		61
+#define CLK_MOUT_CMU_PERIC1_UART_BT		62
+#define CLK_MOUT_CMU_PERIC1_USI04		63
+#define CLK_MOUT_CMU_PERIC1_USI05		64
+#define CLK_MOUT_CMU_PERIC1_USI06		65
+#define CLK_MOUT_CMU_PERIC1_USI07		66
+#define CLK_MOUT_CMU_PERIC1_USI08		67
+#define CLK_MOUT_CMU_PERIC1_USI09		68
+#define CLK_MOUT_CMU_PERIC1_USI10		69
+#define CLK_MOUT_CMU_PERIC1_USI11		70
+#define CLK_MOUT_CMU_PERIC1_USI12		71
+#define CLK_MOUT_CMU_PERIC1_USI13		72
+#define CLK_MOUT_CMU_PERIS_BUS			73
+#define CLK_MOUT_CMU_SRDZ_BUS			74
+#define CLK_MOUT_CMU_SRDZ_IMGD			75
+#define CLK_MOUT_CMU_VPU_BUS			76
+#define CLK_DOUT_CMU_ABOX_CPUABOX		77
+#define CLK_DOUT_CMU_APM_BUS			78
+#define CLK_DOUT_CMU_BUS1_BUS			79
+#define CLK_DOUT_CMU_BUSC_BUS			80
+#define CLK_DOUT_CMU_BUSC_BUSPHSI2C		81
+#define CLK_DOUT_CMU_CAM_BUS			82
+#define CLK_DOUT_CMU_CAM_TPU0			83
+#define CLK_DOUT_CMU_CAM_TPU1			84
+#define CLK_DOUT_CMU_CAM_VRA			85
+#define CLK_DOUT_CMU_CIS_CLK0			86
+#define CLK_DOUT_CMU_CIS_CLK1			87
+#define CLK_DOUT_CMU_CIS_CLK2			88
+#define CLK_DOUT_CMU_CIS_CLK3			89
+#define CLK_DOUT_CMU_CORE_BUS			90
+#define CLK_DOUT_CMU_CPUCL0_SWITCH		91
+#define CLK_DOUT_CMU_CPUCL1_SWITCH		92
+#define CLK_DOUT_CMU_DBG_BUS			93
+#define CLK_DOUT_CMU_DCAM_BUS			94
+#define CLK_DOUT_CMU_DCAM_IMGD			95
+#define CLK_DOUT_CMU_DPU_BUS			96
+#define CLK_DOUT_CMU_DSP_BUS			97
+#define CLK_DOUT_CMU_FSYS0_BUS			98
+#define CLK_DOUT_CMU_FSYS0_DPGTC		99
+#define CLK_DOUT_CMU_FSYS0_MMC_EMBD		100
+#define CLK_DOUT_CMU_FSYS0_UFS_EMBD		101
+#define CLK_DOUT_CMU_FSYS0_USBDRD30		102
+#define CLK_DOUT_CMU_FSYS1_BUS			103
+#define CLK_DOUT_CMU_FSYS1_MMC_CARD		104
+#define CLK_DOUT_CMU_FSYS1_UFS_CARD		105
+#define CLK_DOUT_CMU_G2D_G2D			106
+#define CLK_DOUT_CMU_G2D_JPEG			107
+#define CLK_DOUT_CMU_G3D_SWITCH			108
+#define CLK_DOUT_CMU_HPM			109
+#define CLK_DOUT_CMU_IMEM_BUS			110
+#define CLK_DOUT_CMU_ISPHQ_BUS			111
+#define CLK_DOUT_CMU_ISPLP_BUS			112
+#define CLK_DOUT_CMU_IVA_BUS			113
+#define CLK_DOUT_CMU_MFC_BUS			114
+#define CLK_DOUT_CMU_MODEM_SHARED0		115
+#define CLK_DOUT_CMU_MODEM_SHARED1		116
+#define CLK_DOUT_CMU_PERIC0_BUS			117
+#define CLK_DOUT_CMU_PERIC0_UART_DBG		118
+#define CLK_DOUT_CMU_PERIC0_USI00		119
+#define CLK_DOUT_CMU_PERIC0_USI01		120
+#define CLK_DOUT_CMU_PERIC0_USI02		121
+#define CLK_DOUT_CMU_PERIC0_USI03		122
+#define CLK_DOUT_CMU_PERIC1_BUS			123
+#define CLK_DOUT_CMU_PERIC1_SPEEDY2		124
+#define CLK_DOUT_CMU_PERIC1_SPI_CAM0		125
+#define CLK_DOUT_CMU_PERIC1_SPI_CAM1		126
+#define CLK_DOUT_CMU_PERIC1_UART_BT		127
+#define CLK_DOUT_CMU_PERIC1_USI04		128
+#define CLK_DOUT_CMU_PERIC1_USI05		129
+#define CLK_DOUT_CMU_PERIC1_USI06		130
+#define CLK_DOUT_CMU_PERIC1_USI07		131
+#define CLK_DOUT_CMU_PERIC1_USI08		132
+#define CLK_DOUT_CMU_PERIC1_USI09		133
+#define CLK_DOUT_CMU_PERIC1_USI10		134
+#define CLK_DOUT_CMU_PERIC1_USI11		135
+#define CLK_DOUT_CMU_PERIC1_USI12		136
+#define CLK_DOUT_CMU_PERIC1_USI13		137
+#define CLK_DOUT_CMU_PERIS_BUS			138
+#define CLK_DOUT_CMU_SRDZ_BUS			139
+#define CLK_DOUT_CMU_SRDZ_IMGD			140
+#define CLK_DOUT_CMU_VPU_BUS			141
+#define CLK_DOUT_CMU_SHARED0_DIV2		142
+#define CLK_DOUT_CMU_SHARED0_DIV4		143
+#define CLK_DOUT_CMU_SHARED1_DIV2		144
+#define CLK_DOUT_CMU_SHARED1_DIV4		145
+#define CLK_DOUT_CMU_SHARED2_DIV2		146
+#define CLK_DOUT_CMU_SHARED3_DIV2		147
+#define CLK_DOUT_CMU_SHARED4_DIV2		148
+#define CLK_DOUT_CMU_FSYS1_PCIE			149
+#define CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2		150
+#define CLK_DOUT_CMU_CMU_OTP			151
+#define CLK_GOUT_CMU_DROOPDETECTOR		152
+#define CLK_GOUT_CMU_MIF_SWITCH			153
+#define CLK_GOUT_CMU_ABOX_CPUABOX		154
+#define CLK_GOUT_CMU_APM_BUS			155
+#define CLK_GOUT_CMU_BUS1_BUS			156
+#define CLK_GOUT_CMU_BUSC_BUS			157
+#define CLK_GOUT_CMU_BUSC_BUSPHSI2C		158
+#define CLK_GOUT_CMU_CAM_BUS			159
+#define CLK_GOUT_CMU_CAM_TPU0			160
+#define CLK_GOUT_CMU_CAM_TPU1			161
+#define CLK_GOUT_CMU_CAM_VRA			162
+#define CLK_GOUT_CMU_CIS_CLK0			163
+#define CLK_GOUT_CMU_CIS_CLK1			164
+#define CLK_GOUT_CMU_CIS_CLK2			165
+#define CLK_GOUT_CMU_CIS_CLK3			166
+#define CLK_GOUT_CMU_CORE_BUS			167
+#define CLK_GOUT_CMU_CPUCL0_SWITCH		168
+#define CLK_GOUT_CMU_CPUCL1_SWITCH		169
+#define CLK_GOUT_CMU_DBG_BUS			170
+#define CLK_GOUT_CMU_DCAM_BUS			171
+#define CLK_GOUT_CMU_DCAM_IMGD			172
+#define CLK_GOUT_CMU_DPU_BUS			173
+#define CLK_GOUT_CMU_DSP_BUS			174
+#define CLK_GOUT_CMU_FSYS0_BUS			175
+#define CLK_GOUT_CMU_FSYS0_DPGTC		176
+#define CLK_GOUT_CMU_FSYS0_MMC_EMBD		177
+#define CLK_GOUT_CMU_FSYS0_UFS_EMBD		178
+#define CLK_GOUT_CMU_FSYS0_USBDRD30		179
+#define CLK_GOUT_CMU_FSYS1_BUS			180
+#define CLK_GOUT_CMU_FSYS1_MMC_CARD		181
+#define CLK_GOUT_CMU_FSYS1_PCIE			182
+#define CLK_GOUT_CMU_FSYS1_UFS_CARD		183
+#define CLK_GOUT_CMU_G2D_G2D			184
+#define CLK_GOUT_CMU_G2D_JPEG			185
+#define CLK_GOUT_CMU_G3D_SWITCH			186
+#define CLK_GOUT_CMU_HPM			187
+#define CLK_GOUT_CMU_IMEM_BUS			188
+#define CLK_GOUT_CMU_ISPHQ_BUS			189
+#define CLK_GOUT_CMU_ISPLP_BUS			190
+#define CLK_GOUT_CMU_IVA_BUS			191
+#define CLK_GOUT_CMU_MFC_BUS			192
+#define CLK_GOUT_CMU_MODEM_SHARED0		193
+#define CLK_GOUT_CMU_MODEM_SHARED1		194
+#define CLK_GOUT_CMU_PERIC0_BUS			195
+#define CLK_GOUT_CMU_PERIC0_UART_DBG		196
+#define CLK_GOUT_CMU_PERIC0_USI00		197
+#define CLK_GOUT_CMU_PERIC0_USI01		198
+#define CLK_GOUT_CMU_PERIC0_USI02		199
+#define CLK_GOUT_CMU_PERIC0_USI03		200
+#define CLK_GOUT_CMU_PERIC1_BUS			201
+#define CLK_GOUT_CMU_PERIC1_SPEEDY2		202
+#define CLK_GOUT_CMU_PERIC1_SPI_CAM0		203
+#define CLK_GOUT_CMU_PERIC1_SPI_CAM1		204
+#define CLK_GOUT_CMU_PERIC1_UART_BT		205
+#define CLK_GOUT_CMU_PERIC1_USI04		206
+#define CLK_GOUT_CMU_PERIC1_USI05		207
+#define CLK_GOUT_CMU_PERIC1_USI06		208
+#define CLK_GOUT_CMU_PERIC1_USI07		209
+#define CLK_GOUT_CMU_PERIC1_USI08		210
+#define CLK_GOUT_CMU_PERIC1_USI09		211
+#define CLK_GOUT_CMU_PERIC1_USI10		212
+#define CLK_GOUT_CMU_PERIC1_USI11		213
+#define CLK_GOUT_CMU_PERIC1_USI12		214
+#define CLK_GOUT_CMU_PERIC1_USI13		215
+#define CLK_GOUT_CMU_PERIS_BUS			216
+#define CLK_GOUT_CMU_SRDZ_BUS			217
+#define CLK_GOUT_CMU_SRDZ_IMGD			218
+#define CLK_GOUT_CMU_VPU_BUS			219
+
+/* CMU_PERIS */
+#define CLK_MOUT_PERIS_BUS_USER				1
+#define CLK_MOUT_PERIS_GIC				2
+#define CLK_GOUT_PERIS_CMU_PERIS_PCLK			3
+#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM		4
+#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS		5
+#define CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK		6
+#define CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK		7
+#define CLK_GOUT_PERIS_BUSIF_TMU_PCLK			8
+#define CLK_GOUT_PERIS_GIC_CLK				9
+#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK		10
+#define CLK_GOUT_PERIS_MCT_PCLK				11
+#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK		12
+#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK			13
+#define CLK_GOUT_PERIS_PMU_PERIS_PCLK			14
+#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK	15
+#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK	16
+#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK		17
+#define CLK_GOUT_PERIS_TZPC00_PCLK			18
+#define CLK_GOUT_PERIS_TZPC01_PCLK			19
+#define CLK_GOUT_PERIS_TZPC02_PCLK			20
+#define CLK_GOUT_PERIS_TZPC03_PCLK			21
+#define CLK_GOUT_PERIS_TZPC04_PCLK			22
+#define CLK_GOUT_PERIS_TZPC05_PCLK			23
+#define CLK_GOUT_PERIS_TZPC06_PCLK			24
+#define CLK_GOUT_PERIS_TZPC07_PCLK			25
+#define CLK_GOUT_PERIS_TZPC08_PCLK			26
+#define CLK_GOUT_PERIS_TZPC09_PCLK			27
+#define CLK_GOUT_PERIS_TZPC10_PCLK			28
+#define CLK_GOUT_PERIS_TZPC11_PCLK			29
+#define CLK_GOUT_PERIS_TZPC12_PCLK			30
+#define CLK_GOUT_PERIS_TZPC13_PCLK			31
+#define CLK_GOUT_PERIS_TZPC14_PCLK			32
+#define CLK_GOUT_PERIS_TZPC15_PCLK			33
+#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK		34
+#define CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK		35
+#define CLK_GOUT_PERIS_XIU_P_PERIS_ACLK			36
+
+/* CMU_FSYS0 */
+#define CLK_MOUT_FSYS0_BUS_USER				1
+#define CLK_MOUT_FSYS0_DPGTC_USER			2
+#define CLK_MOUT_FSYS0_MMC_EMBD_USER			3
+#define CLK_MOUT_FSYS0_UFS_EMBD_USER			4
+#define CLK_MOUT_FSYS0_USBDRD30_USER			5
+#define CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK		6
+#define CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK			7
+#define CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK		8
+#define CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK		9
+#define CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK		10
+#define CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK			11
+#define CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK			12
+#define CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK		13
+#define CLK_GOUT_FSYS0_DP_LINK_I_PCLK			14
+#define CLK_GOUT_FSYS0_ETR_MIU_I_ACLK			15
+#define CLK_GOUT_FSYS0_ETR_MIU_I_PCLK			16
+#define CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK			17
+#define CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK		18
+#define CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK		19
+#define CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK		20
+#define CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK		21
+#define CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK			22
+#define CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN			23
+#define CLK_GOUT_FSYS0_PMU_FSYS0_PCLK			24
+#define CLK_GOUT_FSYS0_BCM_FSYS0_ACLK			25
+#define CLK_GOUT_FSYS0_BCM_FSYS0_PCLK			26
+#define CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK	27
+#define CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK		28
+#define CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK			29
+#define CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO		30
+#define CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK		31
+#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK		32
+#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK		33
+#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK	34
+#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK		35
+#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK		36
+#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK		37
+#define CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK		38
+#define CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK			39
+#define CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK		40
+#define CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK			41
+
+/* CMU_FSYS1 */
+#define CLK_MOUT_FSYS1_BUS_USER								1
+#define CLK_MOUT_FSYS1_MMC_CARD_USER							2
+#define CLK_MOUT_FSYS1_PCIE_USER							3
+#define CLK_MOUT_FSYS1_UFS_CARD_USER							4
+#define CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN						5
+#define CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM						6
+#define CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK							7
+#define CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK						8
+#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK						9
+#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK						10
+#define CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK							11
+#define CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK							12
+#define CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK						13
+#define CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK							14
+#define CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK						15
+#define CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK						16
+#define CLK_GOUT_FSYS1_MMC_CARD_I_ACLK							17
+#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN							18
+#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0							19
+#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1							20
+#define CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK	21
+#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0							22
+#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1							23
+#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK			24
+#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK			25
+#define CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL			26
+#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0							27
+#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1							28
+#define CLK_GOUT_FSYS1_PMU_FSYS1_PCLK							29
+#define CLK_GOUT_FSYS1_BCM_FSYS1_ACLK							30
+#define CLK_GOUT_FSYS1_BCM_FSYS1_PCLK							31
+#define CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK					32
+#define CLK_GOUT_FSYS1_RTIC_I_ACLK							33
+#define CLK_GOUT_FSYS1_RTIC_I_PCLK							34
+#define CLK_GOUT_FSYS1_SSS_I_ACLK							35
+#define CLK_GOUT_FSYS1_SSS_I_PCLK							36
+#define CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK						37
+#define CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK							38
+#define CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK							39
+#define CLK_GOUT_FSYS1_UFS_CARD_I_ACLK							40
+#define CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO						41
+#define CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK						42
+#define CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK							43
+#define CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK							44
+
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_BUS_USER			1
+#define CLK_MOUT_PERIC0_UART_DBG_USER			2
+#define CLK_MOUT_PERIC0_USI00_USER			3
+#define CLK_MOUT_PERIC0_USI01_USER			4
+#define CLK_MOUT_PERIC0_USI02_USER			5
+#define CLK_MOUT_PERIC0_USI03_USER			6
+#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK		7
+#define CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK		8
+#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK		9
+#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK		10
+#define CLK_GOUT_PERIC0_PMU_PERIC0_PCLK			11
+#define CLK_GOUT_PERIC0_PWM_I_PCLK_S0			12
+#define CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK	13
+#define CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK			14
+#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK		15
+#define CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK		16
+#define CLK_GOUT_PERIC0_UART_DBG_PCLK			17
+#define CLK_GOUT_PERIC0_USI00_I_PCLK			18
+#define CLK_GOUT_PERIC0_USI00_I_SCLK_USI		19
+#define CLK_GOUT_PERIC0_USI01_I_PCLK			20
+#define CLK_GOUT_PERIC0_USI01_I_SCLK_USI		21
+#define CLK_GOUT_PERIC0_USI02_I_PCLK			22
+#define CLK_GOUT_PERIC0_USI02_I_SCLK_USI		23
+#define CLK_GOUT_PERIC0_USI03_I_PCLK			24
+#define CLK_GOUT_PERIC0_USI03_I_SCLK_USI		25
+
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_BUS_USER			1
+#define CLK_MOUT_PERIC1_SPEEDY2_USER			2
+#define CLK_MOUT_PERIC1_SPI_CAM0_USER			3
+#define CLK_MOUT_PERIC1_SPI_CAM1_USER			4
+#define CLK_MOUT_PERIC1_UART_BT_USER			5
+#define CLK_MOUT_PERIC1_USI04_USER			6
+#define CLK_MOUT_PERIC1_USI05_USER			7
+#define CLK_MOUT_PERIC1_USI06_USER			8
+#define CLK_MOUT_PERIC1_USI07_USER			9
+#define CLK_MOUT_PERIC1_USI08_USER			10
+#define CLK_MOUT_PERIC1_USI09_USER			11
+#define CLK_MOUT_PERIC1_USI10_USER			12
+#define CLK_MOUT_PERIC1_USI11_USER			13
+#define CLK_MOUT_PERIC1_USI12_USER			14
+#define CLK_MOUT_PERIC1_USI13_USER			15
+#define CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK		16
+#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK	17
+#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK		18
+#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK		19
+#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK		20
+#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK		21
+#define CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK		22
+#define CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK		23
+#define CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK		24
+#define CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK		25
+#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK		26
+#define CLK_GOUT_PERIC1_PMU_PERIC1_PCLK			27
+#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK	28
+#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK		29
+#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK		30
+#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK		31
+#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK		32
+#define CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK			33
+#define CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK		34
+#define CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK		35
+#define CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK		36
+#define CLK_GOUT_PERIC1_SPI_CAM0_PCLK			37
+#define CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK		38
+#define CLK_GOUT_PERIC1_SPI_CAM1_PCLK			39
+#define CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK		40
+#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK		41
+#define CLK_GOUT_PERIC1_UART_BT_EXT_UCLK		42
+#define CLK_GOUT_PERIC1_UART_BT_PCLK			43
+#define CLK_GOUT_PERIC1_USI04_I_PCLK			44
+#define CLK_GOUT_PERIC1_USI04_I_SCLK_USI		45
+#define CLK_GOUT_PERIC1_USI05_I_PCLK			46
+#define CLK_GOUT_PERIC1_USI05_I_SCLK_USI		47
+#define CLK_GOUT_PERIC1_USI06_I_PCLK			48
+#define CLK_GOUT_PERIC1_USI06_I_SCLK_USI		49
+#define CLK_GOUT_PERIC1_USI07_I_PCLK			50
+#define CLK_GOUT_PERIC1_USI07_I_SCLK_USI		51
+#define CLK_GOUT_PERIC1_USI08_I_PCLK			52
+#define CLK_GOUT_PERIC1_USI08_I_SCLK_USI		53
+#define CLK_GOUT_PERIC1_USI09_I_PCLK			54
+#define CLK_GOUT_PERIC1_USI09_I_SCLK_USI		55
+#define CLK_GOUT_PERIC1_USI10_I_PCLK			56
+#define CLK_GOUT_PERIC1_USI10_I_SCLK_USI		57
+#define CLK_GOUT_PERIC1_USI11_I_PCLK			58
+#define CLK_GOUT_PERIC1_USI11_I_SCLK_USI		59
+#define CLK_GOUT_PERIC1_USI12_I_PCLK			60
+#define CLK_GOUT_PERIC1_USI12_I_SCLK_USI		61
+#define CLK_GOUT_PERIC1_USI13_I_PCLK			62
+#define CLK_GOUT_PERIC1_USI13_I_SCLK_USI		63
+#define CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK		64
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS8895_H */

include/dt-bindings/clock/samsung,exynosautov920.h

diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index c720f34..0c681f2 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -160,6 +160,7 @@
 #define DOUT_CLKCMU_SNW_NOC		144
 #define DOUT_CLKCMU_SSP_NOC		145
 #define DOUT_CLKCMU_TAA_NOC		146
+#define DOUT_TCXO_DIV2			147
 
 /* CMU_PERIC0 */
 #define CLK_MOUT_PERIC0_IP_USER		1
@@ -188,4 +189,50 @@
 #define CLK_DOUT_PERIC0_USI_I2C		23
 #define CLK_DOUT_PERIC0_I3C		24
 
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_IP_USER		1
+#define CLK_MOUT_PERIC1_NOC_USER	2
+#define CLK_MOUT_PERIC1_USI09_USI	3
+#define CLK_MOUT_PERIC1_USI10_USI	4
+#define CLK_MOUT_PERIC1_USI11_USI	5
+#define CLK_MOUT_PERIC1_USI12_USI	6
+#define CLK_MOUT_PERIC1_USI13_USI	7
+#define CLK_MOUT_PERIC1_USI14_USI	8
+#define CLK_MOUT_PERIC1_USI15_USI	9
+#define CLK_MOUT_PERIC1_USI16_USI	10
+#define CLK_MOUT_PERIC1_USI17_USI	11
+#define CLK_MOUT_PERIC1_USI_I2C		12
+#define CLK_MOUT_PERIC1_I3C		13
+
+#define CLK_DOUT_PERIC1_USI09_USI	14
+#define CLK_DOUT_PERIC1_USI10_USI	15
+#define CLK_DOUT_PERIC1_USI11_USI	16
+#define CLK_DOUT_PERIC1_USI12_USI	17
+#define CLK_DOUT_PERIC1_USI13_USI	18
+#define CLK_DOUT_PERIC1_USI14_USI	19
+#define CLK_DOUT_PERIC1_USI15_USI	20
+#define CLK_DOUT_PERIC1_USI16_USI	21
+#define CLK_DOUT_PERIC1_USI17_USI	22
+#define CLK_DOUT_PERIC1_USI_I2C		23
+#define CLK_DOUT_PERIC1_I3C		24
+
+/* CMU_MISC */
+#define CLK_MOUT_MISC_NOC_USER		1
+#define CLK_MOUT_MISC_GIC		2
+
+#define CLK_DOUT_MISC_OTP		3
+#define CLK_DOUT_MISC_NOCP		4
+#define CLK_DOUT_MISC_OSC_DIV2		5
+
+/* CMU_HSI0 */
+#define CLK_MOUT_HSI0_NOC_USER		1
+
+#define CLK_DOUT_HSI0_PCIE_APB		2
+
+/* CMU_HSI1 */
+#define CLK_MOUT_HSI1_MMC_CARD_USER	1
+#define CLK_MOUT_HSI1_NOC_USER		2
+#define CLK_MOUT_HSI1_USBDRD_USER	3
+#define CLK_MOUT_HSI1_USBDRD		4
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */

include/dt-bindings/iio/adc/gehc,pmc-adc.h

diff --git a/include/dt-bindings/iio/adc/gehc,pmc-adc.h b/include/dt-bindings/iio/adc/gehc,pmc-adc.h
new file mode 100644
index 0000000..2f291e3
--- /dev/null
+++ b/include/dt-bindings/iio/adc/gehc,pmc-adc.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_IIO_ADC_GEHC_PMC_ADC_H
+#define _DT_BINDINGS_IIO_ADC_GEHC_PMC_ADC_H
+
+/* ADC channel type */
+#define GEHC_PMC_ADC_VOLTAGE	0
+#define GEHC_PMC_ADC_CURRENT	1
+
+#endif

include/dt-bindings/interconnect/qcom,qcs615-rpmh.h

diff --git a/include/dt-bindings/interconnect/qcom,qcs615-rpmh.h b/include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
new file mode 100644
index 0000000..84ae0d3
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,qcs615-rpmh.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS615_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS615_H
+
+#define MASTER_A1NOC_CFG		1
+#define MASTER_QDSS_BAM			2
+#define MASTER_QSPI			3
+#define MASTER_QUP_0			4
+#define MASTER_BLSP_1			5
+#define MASTER_CNOC_A2NOC		6
+#define MASTER_CRYPTO			7
+#define MASTER_IPA			8
+#define MASTER_EMAC_EVB			9
+#define MASTER_PCIE			10
+#define MASTER_QDSS_ETR			11
+#define MASTER_SDCC_1			12
+#define MASTER_SDCC_2			13
+#define MASTER_UFS_MEM			14
+#define MASTER_USB2			15
+#define MASTER_USB3_0			16
+#define SLAVE_A1NOC_SNOC		17
+#define SLAVE_LPASS_SNOC		18
+#define SLAVE_ANOC_PCIE_SNOC		19
+#define SLAVE_SERVICE_A2NOC		20
+
+#define MASTER_CAMNOC_HF0_UNCOMP	1
+#define MASTER_CAMNOC_HF1_UNCOMP	2
+#define MASTER_CAMNOC_SF_UNCOMP		3
+#define SLAVE_CAMNOC_UNCOMP		4
+
+#define MASTER_SPDM			1
+#define MASTER_SNOC_CNOC		2
+#define MASTER_QDSS_DAP			3
+#define SLAVE_A1NOC_CFG			4
+#define SLAVE_AHB2PHY_EAST		5
+#define SLAVE_AHB2PHY_WEST		6
+#define SLAVE_AOP			7
+#define SLAVE_AOSS			8
+#define SLAVE_CAMERA_CFG		9
+#define SLAVE_CLK_CTL			10
+#define SLAVE_RBCPR_CX_CFG		11
+#define SLAVE_RBCPR_MX_CFG		12
+#define SLAVE_CRYPTO_0_CFG		13
+#define SLAVE_CNOC_DDRSS		14
+#define SLAVE_DISPLAY_CFG		15
+#define SLAVE_EMAC_AVB_CFG		16
+#define SLAVE_GLM			17
+#define SLAVE_GFX3D_CFG			18
+#define SLAVE_IMEM_CFG			19
+#define SLAVE_IPA_CFG			20
+#define SLAVE_CNOC_MNOC_CFG		21
+#define SLAVE_PCIE_CFG			22
+#define SLAVE_PIMEM_CFG			23
+#define SLAVE_PRNG			24
+#define SLAVE_QDSS_CFG			25
+#define SLAVE_QSPI			26
+#define SLAVE_QUP_0			27
+#define SLAVE_QUP_1			28
+#define SLAVE_SDCC_1			29
+#define SLAVE_SDCC_2			30
+#define SLAVE_SNOC_CFG			31
+#define SLAVE_SPDM_WRAPPER		32
+#define SLAVE_TCSR			33
+#define SLAVE_TLMM_EAST			34
+#define SLAVE_TLMM_SOUTH		35
+#define SLAVE_TLMM_WEST			36
+#define SLAVE_UFS_MEM_CFG		37
+#define SLAVE_USB2			38
+#define SLAVE_USB3			39
+#define SLAVE_VENUS_CFG			40
+#define SLAVE_VSENSE_CTRL_CFG		41
+#define SLAVE_CNOC_A2NOC		42
+#define SLAVE_SERVICE_CNOC		43
+
+#define MASTER_CNOC_DC_NOC		1
+#define SLAVE_DC_NOC_GEMNOC		2
+#define SLAVE_LLCC_CFG			3
+
+#define MASTER_APPSS_PROC		1
+#define MASTER_GPU_TCU			2
+#define MASTER_SYS_TCU			3
+#define MASTER_GEM_NOC_CFG		4
+#define MASTER_GFX3D			5
+#define MASTER_MNOC_HF_MEM_NOC		6
+#define MASTER_MNOC_SF_MEM_NOC		7
+#define MASTER_SNOC_GC_MEM_NOC		8
+#define MASTER_SNOC_SF_MEM_NOC		9
+#define SLAVE_MSS_PROC_MS_MPU_CFG	10
+#define SLAVE_GEM_NOC_SNOC		11
+#define SLAVE_LLCC			12
+#define SLAVE_MEM_NOC_PCIE_SNOC		13
+#define SLAVE_SERVICE_GEM_NOC		14
+
+#define MASTER_IPA_CORE			1
+#define SLAVE_IPA_CORE			2
+
+#define MASTER_LLCC			1
+#define SLAVE_EBI1			2
+
+#define MASTER_CNOC_MNOC_CFG		1
+#define MASTER_CAMNOC_HF0		2
+#define MASTER_CAMNOC_HF1		3
+#define MASTER_CAMNOC_SF		4
+#define MASTER_MDP0			5
+#define MASTER_ROTATOR			6
+#define MASTER_VIDEO_P0			7
+#define MASTER_VIDEO_PROC		8
+#define SLAVE_MNOC_SF_MEM_NOC		9
+#define SLAVE_MNOC_HF_MEM_NOC		10
+#define SLAVE_SERVICE_MNOC		11
+
+#define MASTER_SNOC_CFG			1
+#define MASTER_A1NOC_SNOC		2
+#define MASTER_GEM_NOC_SNOC		3
+#define MASTER_GEM_NOC_PCIE_SNOC	4
+#define MASTER_LPASS_ANOC		5
+#define MASTER_ANOC_PCIE_SNOC		6
+#define MASTER_PIMEM			7
+#define MASTER_GIC			8
+#define SLAVE_APPSS			9
+#define SLAVE_SNOC_CNOC			10
+#define SLAVE_SNOC_GEM_NOC_SF		11
+#define SLAVE_SNOC_MEM_NOC_GC		12
+#define SLAVE_IMEM			13
+#define SLAVE_PIMEM			14
+#define SLAVE_SERVICE_SNOC		15
+#define SLAVE_PCIE_0			16
+#define SLAVE_QDSS_STM			17
+#define SLAVE_TCU			18
+
+#endif
+

include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h

diff --git a/include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h b/include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h
new file mode 100644
index 0000000..c5eeafa
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,qcs8300-rpmh.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS8300_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS8300_H
+
+#define MASTER_QUP_3				0
+#define MASTER_EMAC				1
+#define MASTER_SDC				2
+#define MASTER_UFS_MEM				3
+#define MASTER_USB2				4
+#define MASTER_USB3_0				5
+#define SLAVE_A1NOC_SNOC			6
+
+#define MASTER_QDSS_BAM				0
+#define MASTER_QUP_0				1
+#define MASTER_QUP_1				2
+#define MASTER_CNOC_A2NOC			3
+#define MASTER_CRYPTO_CORE0			4
+#define MASTER_CRYPTO_CORE1			5
+#define MASTER_IPA				6
+#define MASTER_QDSS_ETR_0			7
+#define MASTER_QDSS_ETR_1			8
+#define SLAVE_A2NOC_SNOC			9
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define MASTER_QUP_CORE_3			2
+#define SLAVE_QUP_CORE_0			3
+#define SLAVE_QUP_CORE_1			4
+#define SLAVE_QUP_CORE_3			5
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AHB2PHY_2				2
+#define SLAVE_AHB2PHY_3				3
+#define SLAVE_ANOC_THROTTLE_CFG			4
+#define SLAVE_AOSS				5
+#define SLAVE_APPSS				6
+#define SLAVE_BOOT_ROM				7
+#define SLAVE_CAMERA_CFG			8
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG		9
+#define SLAVE_CAMERA_RT_THROTTLE_CFG		10
+#define SLAVE_CLK_CTL				11
+#define SLAVE_CDSP_CFG				12
+#define SLAVE_RBCPR_CX_CFG			13
+#define SLAVE_RBCPR_MMCX_CFG			14
+#define SLAVE_RBCPR_MX_CFG			15
+#define SLAVE_CPR_NSPCX				16
+#define SLAVE_CPR_NSPHMX			17
+#define SLAVE_CRYPTO_0_CFG			18
+#define SLAVE_CX_RDPM				19
+#define SLAVE_DISPLAY_CFG			20
+#define SLAVE_DISPLAY_RT_THROTTLE_CFG		21
+#define SLAVE_EMAC_CFG				22
+#define SLAVE_GP_DSP0_CFG			23
+#define SLAVE_GPDSP0_THROTTLE_CFG		24
+#define SLAVE_GPU_TCU_THROTTLE_CFG		25
+#define SLAVE_GFX3D_CFG				26
+#define SLAVE_HWKM				27
+#define SLAVE_IMEM_CFG				28
+#define SLAVE_IPA_CFG				29
+#define SLAVE_IPC_ROUTER_CFG			30
+#define SLAVE_LPASS				31
+#define SLAVE_LPASS_THROTTLE_CFG		32
+#define SLAVE_MX_RDPM				33
+#define SLAVE_MXC_RDPM				34
+#define SLAVE_PCIE_0_CFG			35
+#define SLAVE_PCIE_1_CFG			36
+#define SLAVE_PCIE_TCU_THROTTLE_CFG		37
+#define SLAVE_PCIE_THROTTLE_CFG			38
+#define SLAVE_PDM				39
+#define SLAVE_PIMEM_CFG				40
+#define SLAVE_PKA_WRAPPER_CFG			41
+#define SLAVE_QDSS_CFG				42
+#define SLAVE_QM_CFG				43
+#define SLAVE_QM_MPU_CFG			44
+#define SLAVE_QUP_0				45
+#define SLAVE_QUP_1				46
+#define SLAVE_QUP_3				47
+#define SLAVE_SAIL_THROTTLE_CFG			48
+#define SLAVE_SDC1				49
+#define SLAVE_SECURITY				50
+#define SLAVE_SNOC_THROTTLE_CFG			51
+#define SLAVE_TCSR				52
+#define SLAVE_TLMM				53
+#define SLAVE_TSC_CFG				54
+#define SLAVE_UFS_MEM_CFG			55
+#define SLAVE_USB2				56
+#define SLAVE_USB3_0				57
+#define SLAVE_VENUS_CFG				58
+#define SLAVE_VENUS_CVP_THROTTLE_CFG		59
+#define SLAVE_VENUS_V_CPU_THROTTLE_CFG		60
+#define SLAVE_VENUS_VCODEC_THROTTLE_CFG		61
+#define SLAVE_DDRSS_CFG				62
+#define SLAVE_GPDSP_NOC_CFG			63
+#define SLAVE_CNOC_MNOC_HF_CFG			64
+#define SLAVE_CNOC_MNOC_SF_CFG			65
+#define SLAVE_PCIE_ANOC_CFG			66
+#define SLAVE_SNOC_CFG				67
+#define SLAVE_BOOT_IMEM				68
+#define SLAVE_IMEM				69
+#define SLAVE_PIMEM				70
+#define SLAVE_PCIE_0				71
+#define SLAVE_PCIE_1				72
+#define SLAVE_QDSS_STM				73
+#define SLAVE_TCU				74
+
+#define MASTER_CNOC_DC_NOC			0
+#define SLAVE_LLCC_CFG				1
+#define SLAVE_GEM_NOC_CFG			2
+
+#define MASTER_GPU_TCU				0
+#define MASTER_PCIE_TCU				1
+#define MASTER_SYS_TCU				2
+#define MASTER_APPSS_PROC			3
+#define MASTER_COMPUTE_NOC			4
+#define MASTER_GEM_NOC_CFG			5
+#define MASTER_GPDSP_SAIL			6
+#define MASTER_GFX3D				7
+#define MASTER_MNOC_HF_MEM_NOC			8
+#define MASTER_MNOC_SF_MEM_NOC			9
+#define MASTER_ANOC_PCIE_GEM_NOC		10
+#define MASTER_SNOC_GC_MEM_NOC			11
+#define MASTER_SNOC_SF_MEM_NOC			12
+#define SLAVE_GEM_NOC_CNOC			13
+#define SLAVE_LLCC				14
+#define SLAVE_GEM_NOC_PCIE_CNOC			15
+#define SLAVE_SERVICE_GEM_NOC_1			16
+#define SLAVE_SERVICE_GEM_NOC_2			17
+#define SLAVE_SERVICE_GEM_NOC			18
+#define SLAVE_SERVICE_GEM_NOC2			19
+
+#define MASTER_SAILSS_MD0			0
+#define MASTER_DSP0				1
+#define SLAVE_GP_DSP_SAIL_NOC			2
+
+#define MASTER_CNOC_LPASS_AG_NOC		0
+#define MASTER_LPASS_PROC			1
+#define SLAVE_LPASS_CORE_CFG			2
+#define SLAVE_LPASS_LPI_CFG			3
+#define SLAVE_LPASS_MPU_CFG			4
+#define SLAVE_LPASS_TOP_CFG			5
+#define SLAVE_LPASS_SNOC			6
+#define SLAVE_SERVICES_LPASS_AML_NOC		7
+#define SLAVE_SERVICE_LPASS_AG_NOC		8
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_ICP			1
+#define MASTER_CAMNOC_SF			2
+#define MASTER_MDP0				3
+#define MASTER_MDP1				4
+#define MASTER_CNOC_MNOC_HF_CFG			5
+#define MASTER_CNOC_MNOC_SF_CFG			6
+#define MASTER_VIDEO_P0				7
+#define MASTER_VIDEO_PROC			8
+#define MASTER_VIDEO_V_PROC			9
+#define SLAVE_MNOC_HF_MEM_NOC			10
+#define SLAVE_MNOC_SF_MEM_NOC			11
+#define SLAVE_SERVICE_MNOC_HF			12
+#define SLAVE_SERVICE_MNOC_SF			13
+
+#define MASTER_CDSP_NOC_CFG			0
+#define MASTER_CDSP_PROC			1
+#define SLAVE_HCP_A				2
+#define SLAVE_CDSP_MEM_NOC			3
+#define SLAVE_SERVICE_NSP_NOC			4
+
+#define MASTER_PCIE_0				0
+#define MASTER_PCIE_1				1
+#define SLAVE_ANOC_PCIE_GEM_NOC			2
+
+#define MASTER_GIC_AHB				0
+#define MASTER_A1NOC_SNOC			1
+#define MASTER_A2NOC_SNOC			2
+#define MASTER_LPASS_ANOC			3
+#define MASTER_SNOC_CFG				4
+#define MASTER_PIMEM				5
+#define MASTER_GIC				6
+#define SLAVE_SNOC_GEM_NOC_GC			7
+#define SLAVE_SNOC_GEM_NOC_SF			8
+#define SLAVE_SERVICE_SNOC			9
+
+#endif

include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h

diff --git a/include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h b/include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
new file mode 100644
index 0000000..aec7cbb
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define SLAVE_QUP_CORE_0			2
+#define SLAVE_QUP_CORE_1			3
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define MASTER_QDSS_DAP				2
+#define SLAVE_AHB2PHY_SOUTH			3
+#define SLAVE_AOSS				4
+#define SLAVE_CAMERA_CFG			5
+#define SLAVE_CLK_CTL				6
+#define SLAVE_CDSP_CFG				7
+#define SLAVE_RBCPR_CX_CFG			8
+#define SLAVE_RBCPR_MMCX_CFG			9
+#define SLAVE_RBCPR_MXA_CFG			10
+#define SLAVE_RBCPR_MXC_CFG			11
+#define SLAVE_CPR_NSPCX				12
+#define SLAVE_CRYPTO_0_CFG			13
+#define SLAVE_CX_RDPM				14
+#define SLAVE_DISPLAY_CFG			15
+#define SLAVE_GFX3D_CFG				16
+#define SLAVE_IMEM_CFG				17
+#define SLAVE_IPC_ROUTER_CFG			18
+#define SLAVE_LPASS				19
+#define SLAVE_MX_RDPM				20
+#define SLAVE_PCIE_0_CFG			21
+#define SLAVE_PCIE_1_CFG			22
+#define SLAVE_PDM				23
+#define SLAVE_PIMEM_CFG				24
+#define SLAVE_PRNG				25
+#define SLAVE_QDSS_CFG				26
+#define SLAVE_QSPI_0				27
+#define SLAVE_QUP_0				28
+#define SLAVE_QUP_1				29
+#define SLAVE_SDCC_1				30
+#define SLAVE_TCSR				31
+#define SLAVE_TLMM				32
+#define SLAVE_TME_CFG				33
+#define SLAVE_USB3_0				34
+#define SLAVE_VENUS_CFG				35
+#define SLAVE_VSENSE_CTRL_CFG			36
+#define SLAVE_WLAN_Q6_CFG			37
+#define SLAVE_DDRSS_CFG				38
+#define SLAVE_CNOC_MNOC_CFG			39
+#define SLAVE_SNOC_CFG				40
+#define SLAVE_IMEM				41
+#define SLAVE_PIMEM				42
+#define SLAVE_SERVICE_CNOC			43
+#define SLAVE_PCIE_0				44
+#define SLAVE_PCIE_1				45
+#define SLAVE_QDSS_STM				46
+#define SLAVE_TCU				47
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_APPSS_PROC			2
+#define MASTER_GFX3D				3
+#define MASTER_MNOC_HF_MEM_NOC			4
+#define MASTER_MNOC_SF_MEM_NOC			5
+#define MASTER_COMPUTE_NOC			6
+#define MASTER_ANOC_PCIE_GEM_NOC		7
+#define MASTER_SNOC_GC_MEM_NOC			8
+#define MASTER_SNOC_SF_MEM_NOC			9
+#define MASTER_WLAN_Q6				10
+#define SLAVE_GEM_NOC_CNOC			11
+#define SLAVE_LLCC				12
+#define SLAVE_MEM_NOC_PCIE_SNOC			13
+
+#define MASTER_CNOC_LPASS_AG_NOC		0
+#define MASTER_LPASS_PROC			1
+#define SLAVE_LPASS_CORE_CFG			2
+#define SLAVE_LPASS_LPI_CFG			3
+#define SLAVE_LPASS_MPU_CFG			4
+#define SLAVE_LPASS_TOP_CFG			5
+#define SLAVE_LPASS_SNOC			6
+#define SLAVE_SERVICES_LPASS_AML_NOC		7
+#define SLAVE_SERVICE_LPASS_AG_NOC		8
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_ICP			1
+#define MASTER_CAMNOC_SF			2
+#define MASTER_LSR				3
+#define MASTER_MDP				4
+#define MASTER_CNOC_MNOC_CFG			5
+#define MASTER_VIDEO				6
+#define MASTER_VIDEO_CV_PROC			7
+#define MASTER_VIDEO_PROC			8
+#define MASTER_VIDEO_V_PROC			9
+#define SLAVE_MNOC_HF_MEM_NOC			10
+#define SLAVE_MNOC_SF_MEM_NOC			11
+#define SLAVE_SERVICE_MNOC			12
+
+#define MASTER_CDSP_NOC_CFG			0
+#define MASTER_CDSP_PROC			1
+#define SLAVE_CDSP_MEM_NOC			2
+#define SLAVE_SERVICE_NSP_NOC			3
+
+#define MASTER_PCIE_0				0
+#define MASTER_PCIE_1				1
+#define SLAVE_ANOC_PCIE_GEM_NOC			2
+
+#define MASTER_GIC_AHB				0
+#define MASTER_QDSS_BAM				1
+#define MASTER_QSPI_0				2
+#define MASTER_QUP_0				3
+#define MASTER_QUP_1				4
+#define MASTER_A2NOC_SNOC			5
+#define MASTER_CNOC_DATAPATH			6
+#define MASTER_LPASS_ANOC			7
+#define MASTER_SNOC_CFG				8
+#define MASTER_CRYPTO				9
+#define MASTER_PIMEM				10
+#define MASTER_GIC				11
+#define MASTER_QDSS_ETR				12
+#define MASTER_QDSS_ETR_1			13
+#define MASTER_SDCC_1				14
+#define MASTER_USB3_0				15
+#define SLAVE_A2NOC_SNOC			16
+#define SLAVE_SNOC_GEM_NOC_GC			17
+#define SLAVE_SNOC_GEM_NOC_SF			18
+#define SLAVE_SERVICE_SNOC			19
+
+#endif

include/dt-bindings/power/mediatek,mt6735-power-controller.h

diff --git a/include/dt-bindings/power/mediatek,mt6735-power-controller.h b/include/dt-bindings/power/mediatek,mt6735-power-controller.h
new file mode 100644
index 0000000..6957075
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt6735-power-controller.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_MT6735_POWER_CONTROLLER_H
+#define _DT_BINDINGS_POWER_MT6735_POWER_CONTROLLER_H
+
+#define MT6735_POWER_DOMAIN_MD1		0
+#define MT6735_POWER_DOMAIN_CONN	1
+#define MT6735_POWER_DOMAIN_DIS		2
+#define MT6735_POWER_DOMAIN_MFG		3
+#define MT6735_POWER_DOMAIN_ISP		4
+#define MT6735_POWER_DOMAIN_VDE		5
+#define MT6735_POWER_DOMAIN_VEN		6
+
+#endif

include/dt-bindings/power/qcom-rpmpd.h

diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 608087f..df599bf 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -218,6 +218,7 @@
 /* SDM845 Power Domain performance levels */
 #define RPMH_REGULATOR_LEVEL_RETENTION		16
 #define RPMH_REGULATOR_LEVEL_MIN_SVS		48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3		50
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
@@ -238,6 +239,7 @@
 #define RPMH_REGULATOR_LEVEL_TURBO_L1		416
 #define RPMH_REGULATOR_LEVEL_TURBO_L2		432
 #define RPMH_REGULATOR_LEVEL_TURBO_L3		448
+#define RPMH_REGULATOR_LEVEL_TURBO_L4		452
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO 	464
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
 

include/dt-bindings/reset/aspeed,ast2700-scu.h

diff --git a/include/dt-bindings/reset/aspeed,ast2700-scu.h b/include/dt-bindings/reset/aspeed,ast2700-scu.h
new file mode 100644
index 0000000..d53c719
--- /dev/null
+++ b/include/dt-bindings/reset/aspeed,ast2700-scu.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for AST2700 reset controller.
+ *
+ * Copyright (c) 2024 Aspeed Technology Inc.
+ */
+
+#ifndef _MACH_ASPEED_AST2700_RESET_H_
+#define _MACH_ASPEED_AST2700_RESET_H_
+
+/* SOC0 */
+#define SCU0_RESET_SDRAM	0
+#define SCU0_RESET_DDRPHY	1
+#define SCU0_RESET_RSA		2
+#define SCU0_RESET_SHA3		3
+#define SCU0_RESET_HACE		4
+#define SCU0_RESET_SOC		5
+#define SCU0_RESET_VIDEO	6
+#define SCU0_RESET_2D		7
+#define SCU0_RESET_PCIS		8
+#define SCU0_RESET_RVAS0	9
+#define SCU0_RESET_RVAS1	10
+#define SCU0_RESET_SM3		11
+#define SCU0_RESET_SM4		12
+#define SCU0_RESET_CRT0		13
+#define SCU0_RESET_ECC		14
+#define SCU0_RESET_DP_PCI	15
+#define SCU0_RESET_UFS		16
+#define SCU0_RESET_EMMC		17
+#define SCU0_RESET_PCIE1RST	18
+#define SCU0_RESET_PCIE1RSTOE	19
+#define SCU0_RESET_PCIE0RST	20
+#define SCU0_RESET_PCIE0RSTOE	21
+#define SCU0_RESET_JTAG		22
+#define SCU0_RESET_MCTP0	23
+#define SCU0_RESET_MCTP1	24
+#define SCU0_RESET_XDMA0	25
+#define SCU0_RESET_XDMA1	26
+#define SCU0_RESET_H2X1		27
+#define SCU0_RESET_DP		28
+#define SCU0_RESET_DP_MCU	29
+#define SCU0_RESET_SSP		30
+#define SCU0_RESET_H2X0		31
+#define SCU0_RESET_PORTA_VHUB	32
+#define SCU0_RESET_PORTA_PHY3	33
+#define SCU0_RESET_PORTA_XHCI	34
+#define SCU0_RESET_PORTB_VHUB	35
+#define SCU0_RESET_PORTB_PHY3	36
+#define SCU0_RESET_PORTB_XHCI	37
+#define SCU0_RESET_PORTA_VHUB_EHCI	38
+#define SCU0_RESET_PORTB_VHUB_EHCI	39
+#define SCU0_RESET_UHCI		40
+#define SCU0_RESET_TSP		41
+#define SCU0_RESET_E2M0		42
+#define SCU0_RESET_E2M1		43
+#define SCU0_RESET_VLINK	44
+
+/* SOC1 */
+#define SCU1_RESET_LPC0		0
+#define SCU1_RESET_LPC1		1
+#define SCU1_RESET_MII		2
+#define SCU1_RESET_PECI		3
+#define SCU1_RESET_PWM		4
+#define SCU1_RESET_MAC0		5
+#define SCU1_RESET_MAC1		6
+#define SCU1_RESET_MAC2		7
+#define SCU1_RESET_ADC		8
+#define SCU1_RESET_SD		9
+#define SCU1_RESET_ESPI0	10
+#define SCU1_RESET_ESPI1	11
+#define SCU1_RESET_JTAG1	12
+#define SCU1_RESET_SPI0		13
+#define SCU1_RESET_SPI1		14
+#define SCU1_RESET_SPI2		15
+#define SCU1_RESET_I3C0		16
+#define SCU1_RESET_I3C1		17
+#define SCU1_RESET_I3C2		18
+#define SCU1_RESET_I3C3		19
+#define SCU1_RESET_I3C4		20
+#define SCU1_RESET_I3C5		21
+#define SCU1_RESET_I3C6		22
+#define SCU1_RESET_I3C7		23
+#define SCU1_RESET_I3C8		24
+#define SCU1_RESET_I3C9		25
+#define SCU1_RESET_I3C10	26
+#define SCU1_RESET_I3C11	27
+#define SCU1_RESET_I3C12	28
+#define SCU1_RESET_I3C13	29
+#define SCU1_RESET_I3C14	30
+#define SCU1_RESET_I3C15	31
+#define SCU1_RESET_MCU0		32
+#define SCU1_RESET_MCU1		33
+#define SCU1_RESET_H2A_SPI1	34
+#define SCU1_RESET_H2A_SPI2	35
+#define SCU1_RESET_UART0	36
+#define SCU1_RESET_UART1	37
+#define SCU1_RESET_UART2	38
+#define SCU1_RESET_UART3	39
+#define SCU1_RESET_I2C_FILTER	40
+#define SCU1_RESET_CALIPTRA	41
+#define SCU1_RESET_XDMA		42
+#define SCU1_RESET_FSI		43
+#define SCU1_RESET_CAN		44
+#define SCU1_RESET_MCTP		45
+#define SCU1_RESET_I2C		46
+#define SCU1_RESET_UART6	47
+#define SCU1_RESET_UART7	48
+#define SCU1_RESET_UART8	49
+#define SCU1_RESET_UART9	50
+#define SCU1_RESET_LTPI0	51
+#define SCU1_RESET_VGAL		52
+#define SCU1_RESET_LTPI1	53
+#define SCU1_RESET_ACE		54
+#define SCU1_RESET_E2M		55
+#define SCU1_RESET_UHCI		56
+#define SCU1_RESET_PORTC_USB2UART	57
+#define SCU1_RESET_PORTC_VHUB_EHCI	58
+#define SCU1_RESET_PORTD_USB2UART	59
+#define SCU1_RESET_PORTD_VHUB_EHCI	60
+#define SCU1_RESET_H2X		61
+#define SCU1_RESET_I3CDMA	62
+#define SCU1_RESET_PCIE2RST	63
+
+#endif  /* _MACH_ASPEED_AST2700_RESET_H_ */

include/dt-bindings/reset/mediatek,mt6735-infracfg.h

diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 0000000..9df9690
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+
+#define MT6735_INFRA_RST0_EMI_REG		0
+#define MT6735_INFRA_RST0_DRAMC0_AO		1
+#define MT6735_INFRA_RST0_AP_CIRQ_EINT		2
+#define MT6735_INFRA_RST0_APXGPT		3
+#define MT6735_INFRA_RST0_SCPSYS		4
+#define MT6735_INFRA_RST0_KP			5
+#define MT6735_INFRA_RST0_PMIC_WRAP		6
+#define MT6735_INFRA_RST0_CLDMA_AO_TOP		7
+#define MT6735_INFRA_RST0_USBSIF_TOP		8
+#define MT6735_INFRA_RST0_EMI			9
+#define MT6735_INFRA_RST0_CCIF			10
+#define MT6735_INFRA_RST0_DRAMC0		11
+#define MT6735_INFRA_RST0_EMI_AO_REG		12
+#define MT6735_INFRA_RST0_CCIF_AO		13
+#define MT6735_INFRA_RST0_TRNG			14
+#define MT6735_INFRA_RST0_SYS_CIRQ		15
+#define MT6735_INFRA_RST0_GCE			16
+#define MT6735_INFRA_RST0_M4U			17
+#define MT6735_INFRA_RST0_CCIF1			18
+#define MT6735_INFRA_RST0_CLDMA_TOP_PD		19
+
+#endif

include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h

diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
new file mode 100644
index 0000000..c489242
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H
+#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H
+
+#define MT6735_MFG_RST0_AXI		0
+#define MT6735_MFG_RST0_G3D		1
+
+#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */

include/dt-bindings/reset/mediatek,mt6735-pericfg.h

diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 0000000..a62bb19
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H
+#define _DT_BINDINGS_RESET_MT6735_PERICFG_H
+
+#define MT6735_PERI_RST0_UART0			0
+#define MT6735_PERI_RST0_UART1			1
+#define MT6735_PERI_RST0_UART2			2
+#define MT6735_PERI_RST0_UART3			3
+#define MT6735_PERI_RST0_UART4			4
+#define MT6735_PERI_RST0_BTIF			5
+#define MT6735_PERI_RST0_DISP_PWM_PERI		6
+#define MT6735_PERI_RST0_PWM			7
+#define MT6735_PERI_RST0_AUXADC			8
+#define MT6735_PERI_RST0_DMA			9
+#define MT6735_PERI_RST0_IRDA			10
+#define MT6735_PERI_RST0_IRTX			11
+#define MT6735_PERI_RST0_THERM			12
+#define MT6735_PERI_RST0_MSDC2			13
+#define MT6735_PERI_RST0_MSDC3			14
+#define MT6735_PERI_RST0_MSDC0			15
+#define MT6735_PERI_RST0_MSDC1			16
+#define MT6735_PERI_RST0_I2C0			17
+#define MT6735_PERI_RST0_I2C1			18
+#define MT6735_PERI_RST0_I2C2			19
+#define MT6735_PERI_RST0_I2C3			20
+#define MT6735_PERI_RST0_USB			21
+
+#define MT6735_PERI_RST1_SPI0			22
+
+#endif

include/dt-bindings/reset/mediatek,mt6735-vdecsys.h

diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
new file mode 100644
index 0000000..b6ae5d2
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H
+#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H
+
+#define MT6735_VDEC_RST0_VDEC			0
+#define MT6735_VDEC_RST1_SMI_LARB1		1
+
+#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */

include/dt-bindings/reset/qcom,ipq5424-gcc.h

diff --git a/include/dt-bindings/reset/qcom,ipq5424-gcc.h b/include/dt-bindings/reset/qcom,ipq5424-gcc.h
new file mode 100644
index 0000000..16a7277
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq5424-gcc.h
@@ -0,0 +1,310 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H
+
+#define GCC_QUPV3_BCR				0
+#define GCC_QUPV3_I2C0_BCR			1
+#define GCC_QUPV3_UART0_BCR			2
+#define GCC_QUPV3_I2C1_BCR			3
+#define GCC_QUPV3_UART1_BCR			4
+#define GCC_QUPV3_SPI0_BCR			5
+#define GCC_QUPV3_SPI1_BCR			6
+#define GCC_IMEM_BCR				7
+#define GCC_TME_BCR				8
+#define GCC_DDRSS_BCR				9
+#define GCC_PRNG_BCR				10
+#define GCC_BOOT_ROM_BCR			11
+#define GCC_NSS_BCR				12
+#define GCC_MDIO_BCR				13
+#define GCC_UNIPHY0_BCR				14
+#define GCC_UNIPHY1_BCR				15
+#define GCC_UNIPHY2_BCR				16
+#define GCC_WCSS_BCR				17
+#define GCC_SEC_CTRL_BCR			19
+#define GCC_TME_SEC_BUS_BCR			20
+#define GCC_ADSS_BCR				21
+#define GCC_LPASS_BCR				22
+#define GCC_PCIE0_BCR				23
+#define GCC_PCIE0_LINK_DOWN_BCR			24
+#define GCC_PCIE0PHY_PHY_BCR			25
+#define GCC_PCIE0_PHY_BCR			26
+#define GCC_PCIE1_BCR				27
+#define GCC_PCIE1_LINK_DOWN_BCR			28
+#define GCC_PCIE1PHY_PHY_BCR			29
+#define GCC_PCIE1_PHY_BCR			30
+#define GCC_PCIE2_BCR				31
+#define GCC_PCIE2_LINK_DOWN_BCR			32
+#define GCC_PCIE2PHY_PHY_BCR			33
+#define GCC_PCIE2_PHY_BCR			34
+#define GCC_PCIE3_BCR				35
+#define GCC_PCIE3_LINK_DOWN_BCR			36
+#define GCC_PCIE3PHY_PHY_BCR			37
+#define GCC_PCIE3_PHY_BCR			38
+#define GCC_USB_BCR				39
+#define GCC_QUSB2_0_PHY_BCR			40
+#define GCC_USB0_PHY_BCR			41
+#define GCC_USB3PHY_0_PHY_BCR			42
+#define GCC_QDSS_BCR				43
+#define GCC_SNOC_BCR				44
+#define GCC_ANOC_BCR				45
+#define GCC_PCNOC_BCR				46
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR		47
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR		48
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR		49
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR		50
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR		51
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR		52
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR		53
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR		54
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR		55
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR		56
+#define GCC_QPIC_BCR				57
+#define GCC_SDCC_BCR				58
+#define GCC_DCC_BCR				59
+#define GCC_SPDM_BCR				60
+#define GCC_MPM_BCR				61
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	62
+#define GCC_RBCPR_BCR				63
+#define GCC_CMN_BLK_BCR				64
+#define GCC_TCSR_BCR				65
+#define GCC_TLMM_BCR				66
+#define GCC_QUPV3_AHB_MST_ARES			67
+#define GCC_QUPV3_CORE_ARES			68
+#define GCC_QUPV3_2X_CORE_ARES			69
+#define GCC_QUPV3_SLEEP_ARES			70
+#define GCC_QUPV3_AHB_SLV_ARES			71
+#define GCC_QUPV3_I2C0_ARES			72
+#define GCC_QUPV3_UART0_ARES			73
+#define GCC_QUPV3_I2C1_ARES			74
+#define GCC_QUPV3_UART1_ARES			75
+#define GCC_QUPV3_SPI0_ARES			76
+#define GCC_QUPV3_SPI1_ARES			77
+#define GCC_DEBUG_ARES				78
+#define GCC_GP1_ARES				79
+#define GCC_GP2_ARES				80
+#define GCC_GP3_ARES				81
+#define GCC_IMEM_AXI_ARES			82
+#define GCC_IMEM_CFG_AHB_ARES			83
+#define GCC_TME_ARES				84
+#define GCC_TME_TS_ARES				85
+#define GCC_TME_SLOW_ARES			86
+#define GCC_TME_RTC_TOGGLE_ARES			87
+#define GCC_TIC_ARES				88
+#define GCC_PRNG_AHB_ARES			89
+#define GCC_BOOT_ROM_AHB_ARES			90
+#define GCC_NSSNOC_ATB_ARES			91
+#define GCC_NSS_TS_ARES				92
+#define GCC_NSSNOC_QOSGEN_REF_ARES		93
+#define GCC_NSSNOC_TIMEOUT_REF_ARES		94
+#define GCC_NSSNOC_MEMNOC_ARES			95
+#define GCC_NSSNOC_SNOC_ARES			96
+#define GCC_NSSCFG_ARES				97
+#define GCC_NSSNOC_NSSCC_ARES			98
+#define GCC_NSSCC_ARES				99
+#define GCC_MDIO_AHB_ARES			100
+#define GCC_UNIPHY0_SYS_ARES			101
+#define GCC_UNIPHY0_AHB_ARES			102
+#define GCC_UNIPHY1_SYS_ARES			103
+#define GCC_UNIPHY1_AHB_ARES			104
+#define GCC_UNIPHY2_SYS_ARES			105
+#define GCC_UNIPHY2_AHB_ARES			106
+#define GCC_NSSNOC_XO_DCD_ARES			107
+#define GCC_NSSNOC_SNOC_1_ARES			108
+#define GCC_NSSNOC_PCNOC_1_ARES			109
+#define GCC_NSSNOC_MEMNOC_1_ARES		110
+#define GCC_DDRSS_ATB_ARES			111
+#define GCC_DDRSS_AHB_ARES			112
+#define GCC_GEMNOC_AHB_ARES			113
+#define GCC_GEMNOC_Q6_AXI_ARES			114
+#define GCC_GEMNOC_NSSNOC_ARES			115
+#define GCC_GEMNOC_SNOC_ARES			116
+#define GCC_GEMNOC_APSS_ARES			117
+#define GCC_GEMNOC_QOSGEN_EXTREF_ARES		118
+#define GCC_GEMNOC_TS_ARES			119
+#define GCC_DDRSS_SMS_SLOW_ARES			120
+#define GCC_GEMNOC_CNOC_ARES			121
+#define GCC_GEMNOC_XO_DBG_ARES			122
+#define GCC_GEMNOC_ANOC_ARES			123
+#define GCC_DDRSS_LLCC_ATB_ARES			124
+#define GCC_LLCC_TPDM_CFG_ARES			125
+#define GCC_TME_BUS_ARES			126
+#define GCC_SEC_CTRL_ACC_ARES			127
+#define GCC_SEC_CTRL_ARES			128
+#define GCC_SEC_CTRL_SENSE_ARES			129
+#define GCC_SEC_CTRL_AHB_ARES			130
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES	131
+#define GCC_ADSS_PWM_ARES			132
+#define GCC_TME_ATB_ARES			133
+#define GCC_TME_DBGAPB_ARES			134
+#define GCC_TME_DEBUG_ARES			135
+#define GCC_TME_AT_ARES				136
+#define GCC_TME_APB_ARES			137
+#define GCC_TME_DMI_DBG_HS_ARES			138
+#define GCC_APSS_AHB_ARES			139
+#define GCC_APSS_AXI_ARES			140
+#define GCC_CPUSS_TRIG_ARES			141
+#define GCC_APSS_DBG_ARES			142
+#define GCC_APSS_TS_ARES			143
+#define GCC_APSS_ATB_ARES			144
+#define GCC_Q6_AXIM_ARES			145
+#define GCC_Q6_AXIS_ARES			146
+#define GCC_Q6_AHB_ARES				147
+#define GCC_Q6_AHB_S_ARES			148
+#define GCC_Q6SS_ATBM_ARES			149
+#define GCC_Q6_TSCTR_1TO2_ARES			150
+#define GCC_Q6SS_PCLKDBG_ARES			151
+#define GCC_Q6SS_TRIG_ARES			152
+#define GCC_Q6SS_BOOT_CBCR_ARES			153
+#define GCC_WCSS_DBG_IFC_APB_ARES		154
+#define GCC_WCSS_DBG_IFC_ATB_ARES		155
+#define GCC_WCSS_DBG_IFC_NTS_ARES		156
+#define GCC_WCSS_DBG_IFC_DAPBUS_ARES		157
+#define GCC_WCSS_DBG_IFC_APB_BDG_ARES		158
+#define GCC_WCSS_DBG_IFC_NTS_BDG_ARES		159
+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES	160
+#define GCC_WCSS_ECAHB_ARES			161
+#define GCC_WCSS_ACMT_ARES			162
+#define GCC_WCSS_AHB_S_ARES			163
+#define GCC_WCSS_AXI_M_ARES			164
+#define GCC_PCNOC_WAPSS_ARES			165
+#define GCC_SNOC_WAPSS_ARES			166
+#define GCC_LPASS_SWAY_ARES			167
+#define GCC_LPASS_CORE_AXIM_ARES		168
+#define GCC_PCIE0_AHB_ARES			169
+#define GCC_PCIE0_AXI_M_ARES			170
+#define GCC_PCIE0_AXI_S_ARES			171
+#define GCC_PCIE0_AXI_S_BRIDGE_ARES		172
+#define GCC_PCIE0_PIPE_ARES			173
+#define GCC_PCIE0_AUX_ARES			174
+#define GCC_PCIE1_AHB_ARES			175
+#define GCC_PCIE1_AXI_M_ARES			176
+#define GCC_PCIE1_AXI_S_ARES			177
+#define GCC_PCIE1_AXI_S_BRIDGE_ARES		178
+#define GCC_PCIE1_PIPE_ARES			179
+#define GCC_PCIE1_AUX_ARES			180
+#define GCC_PCIE2_AHB_ARES			181
+#define GCC_PCIE2_AXI_M_ARES			182
+#define GCC_PCIE2_AXI_S_ARES			183
+#define GCC_PCIE2_AXI_S_BRIDGE_ARES		184
+#define GCC_PCIE2_PIPE_ARES			185
+#define GCC_PCIE2_AUX_ARES			186
+#define GCC_PCIE3_AHB_ARES			187
+#define GCC_PCIE3_AXI_M_ARES			188
+#define GCC_PCIE3_AXI_S_ARES			189
+#define GCC_PCIE3_AXI_S_BRIDGE_ARES		190
+#define GCC_PCIE3_PIPE_ARES			191
+#define GCC_PCIE3_AUX_ARES			192
+#define GCC_USB0_MASTER_ARES			193
+#define GCC_USB0_AUX_ARES			194
+#define GCC_USB0_MOCK_UTMI_ARES			195
+#define GCC_USB0_PIPE_ARES			196
+#define GCC_USB0_SLEEP_ARES			197
+#define GCC_USB0_PHY_CFG_AHB_ARES		198
+#define GCC_QDSS_AT_ARES			199
+#define GCC_QDSS_STM_ARES			200
+#define GCC_QDSS_TRACECLKIN_ARES		201
+#define GCC_QDSS_TSCTR_DIV2_ARES		202
+#define GCC_QDSS_TSCTR_DIV3_ARES		203
+#define GCC_QDSS_TSCTR_DIV4_ARES		204
+#define GCC_QDSS_TSCTR_DIV8_ARES		205
+#define GCC_QDSS_TSCTR_DIV16_ARES		206
+#define GCC_QDSS_DAP_ARES			207
+#define GCC_QDSS_APB2JTAG_ARES			208
+#define GCC_QDSS_ETR_USB_ARES			209
+#define GCC_QDSS_DAP_AHB_ARES			210
+#define GCC_QDSS_CFG_AHB_ARES			211
+#define GCC_QDSS_EUD_AT_ARES			212
+#define GCC_QDSS_TS_ARES			213
+#define GCC_QDSS_USB_ARES			214
+#define GCC_SYS_NOC_AXI_ARES			215
+#define GCC_SNOC_QOSGEN_EXTREF_ARES		216
+#define GCC_CNOC_LPASS_CFG_ARES			217
+#define GCC_SYS_NOC_AT_ARES			218
+#define GCC_SNOC_PCNOC_AHB_ARES			219
+#define GCC_SNOC_TME_ARES			220
+#define GCC_SNOC_XO_DCD_ARES			221
+#define GCC_SNOC_TS_ARES			222
+#define GCC_ANOC0_AXI_ARES			223
+#define GCC_ANOC_PCIE0_1LANE_M_ARES		224
+#define GCC_ANOC_PCIE2_2LANE_M_ARES		225
+#define GCC_ANOC_PCIE1_1LANE_M_ARES		226
+#define GCC_ANOC_PCIE3_2LANE_M_ARES		227
+#define GCC_ANOC_PCNOC_AHB_ARES			228
+#define GCC_ANOC_QOSGEN_EXTREF_ARES		229
+#define GCC_ANOC_XO_DCD_ARES			230
+#define GCC_SNOC_XO_DBG_ARES			231
+#define GCC_AGGRNOC_ATB_ARES			232
+#define GCC_AGGRNOC_TS_ARES			233
+#define GCC_USB0_EUD_AT_ARES			234
+#define GCC_PCNOC_TIC_ARES			235
+#define GCC_PCNOC_AHB_ARES			236
+#define GCC_PCNOC_XO_DBG_ARES			237
+#define GCC_SNOC_LPASS_ARES			238
+#define GCC_PCNOC_AT_ARES			239
+#define GCC_PCNOC_XO_DCD_ARES			240
+#define GCC_PCNOC_TS_ARES			241
+#define GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES		242
+#define GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES		243
+#define GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES		244
+#define GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES		245
+#define GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES		246
+#define GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES		247
+#define GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES		248
+#define GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES		249
+#define GCC_Q6_AXIM_RESET			250
+#define GCC_Q6_AXIS_RESET			251
+#define GCC_Q6_AHB_S_RESET			252
+#define GCC_Q6_AHB_RESET			253
+#define GCC_Q6SS_DBG_RESET			254
+#define GCC_WCSS_ECAHB_RESET			255
+#define GCC_WCSS_DBG_BDG_RESET			256
+#define GCC_WCSS_DBG_RESET			257
+#define GCC_WCSS_AXI_M_RESET			258
+#define GCC_WCSS_AHB_S_RESET			259
+#define GCC_WCSS_ACMT_RESET			260
+#define GCC_WCSSAON_RESET			261
+#define GCC_PCIE0_PIPE_RESET			262
+#define GCC_PCIE0_CORE_STICKY_RESET		263
+#define GCC_PCIE0_AXI_S_STICKY_RESET		264
+#define GCC_PCIE0_AXI_S_RESET			265
+#define GCC_PCIE0_AXI_M_STICKY_RESET		266
+#define GCC_PCIE0_AXI_M_RESET			267
+#define GCC_PCIE0_AUX_RESET			268
+#define GCC_PCIE0_AHB_RESET			269
+#define GCC_PCIE1_PIPE_RESET			270
+#define GCC_PCIE1_CORE_STICKY_RESET		271
+#define GCC_PCIE1_AXI_S_STICKY_RESET		272
+#define GCC_PCIE1_AXI_S_RESET			273
+#define GCC_PCIE1_AXI_M_STICKY_RESET		274
+#define GCC_PCIE1_AXI_M_RESET			275
+#define GCC_PCIE1_AUX_RESET			276
+#define GCC_PCIE1_AHB_RESET			277
+#define GCC_PCIE2_PIPE_RESET			278
+#define GCC_PCIE2_CORE_STICKY_RESET		279
+#define GCC_PCIE2_AXI_S_STICKY_RESET		280
+#define GCC_PCIE2_AXI_S_RESET			281
+#define GCC_PCIE2_AXI_M_STICKY_RESET		282
+#define GCC_PCIE2_AXI_M_RESET			283
+#define GCC_PCIE2_AUX_RESET			284
+#define GCC_PCIE2_AHB_RESET			285
+#define GCC_PCIE3_PIPE_RESET			286
+#define GCC_PCIE3_CORE_STICKY_RESET		287
+#define GCC_PCIE3_AXI_S_STICKY_RESET		288
+#define GCC_PCIE3_AXI_S_RESET			289
+#define GCC_PCIE3_AXI_M_STICKY_RESET		290
+#define GCC_PCIE3_AXI_M_RESET			291
+#define GCC_PCIE3_AUX_RESET			292
+#define GCC_PCIE3_AHB_RESET			293
+#define GCC_NSS_PARTIAL_RESET			294
+#define GCC_UNIPHY0_XPCS_ARES			295
+#define GCC_UNIPHY1_XPCS_ARES			296
+#define GCC_UNIPHY2_XPCS_ARES			297
+#define GCC_USB1_BCR				298
+#define GCC_QUSB2_1_PHY_BCR			299
+
+#endif

include/dt-bindings/reset/qcom,sar2130p-gpucc.h

diff --git a/include/dt-bindings/reset/qcom,sar2130p-gpucc.h b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h
new file mode 100644
index 0000000..99ba5f0
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H
+#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H
+
+#define GPUCC_GPU_CC_GX_BCR			0
+#define GPUCC_GPU_CC_ACD_BCR			1
+#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR		2
+
+#endif