riscv: cache: Implement i/dcache [status, enable, disable]
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
new file mode 100644
index 0000000..6600ac2
--- /dev/null
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#include <common.h>
+
+void icache_enable(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+#ifdef CONFIG_RISCV_NDS
+ asm volatile (
+ "csrr t1, mcache_ctl\n\t"
+ "ori t0, t1, 0x1\n\t"
+ "csrw mcache_ctl, t0\n\t"
+ );
+#endif
+#endif
+}
+
+void icache_disable(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+#ifdef CONFIG_RISCV_NDS
+ asm volatile (
+ "fence.i\n\t"
+ "csrr t1, mcache_ctl\n\t"
+ "andi t0, t1, ~0x1\n\t"
+ "csrw mcache_ctl, t0\n\t"
+ );
+#endif
+#endif
+}
+
+void dcache_enable(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+#ifdef CONFIG_RISCV_NDS
+ asm volatile (
+ "csrr t1, mcache_ctl\n\t"
+ "ori t0, t1, 0x2\n\t"
+ "csrw mcache_ctl, t0\n\t"
+ );
+#endif
+#endif
+}
+
+void dcache_disable(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+#ifdef CONFIG_RISCV_NDS
+ asm volatile (
+ "fence\n\t"
+ "csrr t1, mcache_ctl\n\t"
+ "andi t0, t1, ~0x2\n\t"
+ "csrw mcache_ctl, t0\n\t"
+ );
+#endif
+#endif
+}
+
+int icache_status(void)
+{
+ int ret = 0;
+
+#ifdef CONFIG_RISCV_NDS
+ asm volatile (
+ "csrr t1, mcache_ctl\n\t"
+ "andi %0, t1, 0x01\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+#endif
+
+ return ret;
+}
+
+int dcache_status(void)
+{
+ int ret = 0;
+
+#ifdef CONFIG_RISCV_NDS
+ asm volatile (
+ "csrr t1, mcache_ctl\n\t"
+ "andi %0, t1, 0x02\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+#endif
+
+ return ret;
+}