tree fe337a4e09d6e9a10207d58c0f1f0dedb365013a
parent 0fd7c15f27e389a4567b9ac3d0a534a9e02200ab
author Axel Lin <axel.lin@ingics.com> 1424918722 +0800
committer Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 1427659969 +0530

spi: designware_spi: revisit FIFO size detection again

By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
  a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
     either 0 or 1 byte;
  b) FIFO size is incorrectly decreased by 1 which already done by meaning of
     TX Level register.

Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>