clk: mediatek: mt7986: reorder TOPCKGEN factor ID
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index f19948c..0048d18 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -16,60 +16,60 @@
/* TOPCKGEN */
#define CK_TOP_XTAL 0
-#define CK_TOP_CB_MPLL_416M 1
-#define CK_TOP_MPLL_D2 2
-#define CK_TOP_MPLL_D4 3
-#define CK_TOP_MPLL_D8 4
-#define CK_TOP_MPLL_D8_D2 5
-#define CK_TOP_MPLL_D3_D2 6
-#define CK_TOP_MMPLL_D2 7
-#define CK_TOP_MMPLL_D4 8
-#define CK_TOP_MMPLL_D8 9
-#define CK_TOP_MMPLL_D8_D2 10
-#define CK_TOP_MMPLL_D3_D8 11
-#define CK_TOP_MMPLL_U2PHYD 12
-#define CK_TOP_CB_APLL2_196M 13
-#define CK_TOP_APLL2_D4 14
-#define CK_TOP_NET1PLL_D4 15
-#define CK_TOP_NET1PLL_D5 16
-#define CK_TOP_NET1PLL_D5_D2 17
-#define CK_TOP_NET1PLL_D5_D4 18
-#define CK_TOP_NET1PLL_D8_D2 19
-#define CK_TOP_NET1PLL_D8_D4 20
-#define CK_TOP_CB_NET2PLL_800M 21
-#define CK_TOP_NET2PLL_D4 22
-#define CK_TOP_NET2PLL_D4_D2 23
-#define CK_TOP_NET2PLL_D3_D2 24
-#define CK_TOP_CB_WEDMCUPLL_760M 25
-#define CK_TOP_WEDMCUPLL_D5_D2 26
-#define CK_TOP_CB_SGMPLL_325M 27
-#define CK_TOP_XTAL_D2 28
-#define CK_TOP_RTC_32K 29
-#define CK_TOP_RTC_32P7K 30
-#define CK_TOP_NFI1X 31
-#define CK_TOP_USB_EQ_RX250M 32
-#define CK_TOP_USB_TX250M 33
-#define CK_TOP_USB_LN0_CK 34
-#define CK_TOP_USB_CDR_CK 35
-#define CK_TOP_SPINFI_BCK 36
-#define CK_TOP_I2C_BCK 37
-#define CK_TOP_PEXTP_TL 38
-#define CK_TOP_EMMC_250M 39
-#define CK_TOP_EMMC_416M 40
-#define CK_TOP_F_26M_ADC_CK 41
-#define CK_TOP_SYSAXI 42
-#define CK_TOP_NETSYS_WED_MCU 43
-#define CK_TOP_NETSYS_2X 44
-#define CK_TOP_SGM_325M 45
-#define CK_TOP_A1SYS 46
-#define CK_TOP_EIP_B 47
-#define CK_TOP_F26M 48
-#define CK_TOP_AUD_L 49
-#define CK_TOP_A_TUNER 50
-#define CK_TOP_U2U3_REF 51
-#define CK_TOP_U2U3_SYS 52
-#define CK_TOP_U2U3_XHCI 53
-#define CK_TOP_AP2CNN_HOST 54
+#define CK_TOP_XTAL_D2 1
+#define CK_TOP_RTC_32K 2
+#define CK_TOP_RTC_32P7K 3
+#define CK_TOP_NFI1X 4
+#define CK_TOP_USB_EQ_RX250M 5
+#define CK_TOP_USB_TX250M 6
+#define CK_TOP_USB_LN0_CK 7
+#define CK_TOP_USB_CDR_CK 8
+#define CK_TOP_SPINFI_BCK 9
+#define CK_TOP_I2C_BCK 10
+#define CK_TOP_PEXTP_TL 11
+#define CK_TOP_EMMC_250M 12
+#define CK_TOP_EMMC_416M 13
+#define CK_TOP_F_26M_ADC_CK 14
+#define CK_TOP_SYSAXI 15
+#define CK_TOP_NETSYS_WED_MCU 16
+#define CK_TOP_NETSYS_2X 17
+#define CK_TOP_SGM_325M 18
+#define CK_TOP_A1SYS 19
+#define CK_TOP_EIP_B 20
+#define CK_TOP_F26M 21
+#define CK_TOP_AUD_L 22
+#define CK_TOP_A_TUNER 23
+#define CK_TOP_U2U3_REF 24
+#define CK_TOP_U2U3_SYS 25
+#define CK_TOP_U2U3_XHCI 26
+#define CK_TOP_AP2CNN_HOST 27
+#define CK_TOP_CB_MPLL_416M 28
+#define CK_TOP_MPLL_D2 29
+#define CK_TOP_MPLL_D4 30
+#define CK_TOP_MPLL_D8 31
+#define CK_TOP_MPLL_D8_D2 32
+#define CK_TOP_MPLL_D3_D2 33
+#define CK_TOP_MMPLL_D2 34
+#define CK_TOP_MMPLL_D4 35
+#define CK_TOP_MMPLL_D8 36
+#define CK_TOP_MMPLL_D8_D2 37
+#define CK_TOP_MMPLL_D3_D8 38
+#define CK_TOP_MMPLL_U2PHYD 39
+#define CK_TOP_CB_APLL2_196M 40
+#define CK_TOP_APLL2_D4 41
+#define CK_TOP_NET1PLL_D4 42
+#define CK_TOP_NET1PLL_D5 43
+#define CK_TOP_NET1PLL_D5_D2 44
+#define CK_TOP_NET1PLL_D5_D4 45
+#define CK_TOP_NET1PLL_D8_D2 46
+#define CK_TOP_NET1PLL_D8_D4 47
+#define CK_TOP_CB_NET2PLL_800M 48
+#define CK_TOP_NET2PLL_D4 49
+#define CK_TOP_NET2PLL_D4_D2 50
+#define CK_TOP_NET2PLL_D3_D2 51
+#define CK_TOP_CB_WEDMCUPLL_760M 52
+#define CK_TOP_WEDMCUPLL_D5_D2 53
+#define CK_TOP_CB_SGMPLL_325M 54
#define CK_TOP_NFI1X_SEL 55
#define CK_TOP_SPINFI_SEL 56
#define CK_TOP_SPI_SEL 57