Tegra: Configure L2 cache control reg properly.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.
Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).
Signed-off-by: Tom Warren <twarren@nvidia.com>
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 8e95c7e..4e0301c 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -28,7 +28,7 @@
LIB = $(obj)libcputegra-common.o
SOBJS += lowlevel_init.o
-COBJS-y += ap.o board.o sys_info.o timer.o clock.o
+COBJS-y += ap.o board.o sys_info.o timer.o clock.o cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))