tree 9fe038dbbe9cec28b1f9e6af030d9ee719eb2ac6
parent 64b976a188cf887b502255692106f7c7fa3af861
author Troy Kisky <troy.kisky@boundarydevices.com> 1332417631 +0000
committer Albert ARIBAUD <albert.u.boot@aribaud.net> 1334580838 +0200

MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>