| commit | 81e65925137bc9e943341f1a0bdb5c3dcb552e41 | [log] [tgz] |
|---|---|---|
| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | Tue May 10 13:26:11 2022 +0200 |
| committer | Michal Simek <michal.simek@amd.com> | Fri Jun 24 14:11:05 2022 +0200 |
| tree | edefc1e856be4ed6127e398cba6fb843ecb4ea28 | |
| parent | cff1084f9dc3d03207db01cdcbce07030a9154df [diff] |
xilinx: Add CONFIG_DM_ETH_PHY config Enable CONFIG_DM_ETH_PHY to utilize shared MDIO bus support on all xilinx platforms. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/965981eb324d13a98aad8bd88eb8b50bc5147a7e.1652181968.git.michal.simek@amd.com
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 3142b46..7994110 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig
@@ -76,6 +76,7 @@ CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_EMACLITE=y CONFIG_SYS_NS16550=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 38747ff..c9ae018 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig
@@ -92,6 +92,7 @@ CONFIG_PHY_TI_DP83867=y CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_AXIMRMAC=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1f3e6a4..120bc29 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig
@@ -111,6 +111,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_REALTEK=y CONFIG_PHY_XILINX=y +CONFIG_DM_ETH_PHY=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 3589407..abaebb8 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -160,6 +160,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y CONFIG_XILINX_AXIEMAC=y CONFIG_ZYNQ_GEM=y CONFIG_DM_REGULATOR=y