commit 816979a32bf92bc00cc2e35d5f21708549712859
author Leo Yu-Chi Liang <ycliang@andestech.com> Mon Feb 06 16:10:44 2023 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Fri Feb 17 19:07:48 2023 +0800
tree 3340b10e62e06498421b39c15946c97a3dd6b477
parent 52d54e1837c8bca5ee5feb943ee1236987d7df7d

riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

arch/riscv/cpu/ax25/cache.c

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 35f23c7..1c0c377 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -67,106 +67,26 @@
 
 void icache_enable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"ori t0, t1, 0x1\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#endif
-#endif
 }
 
 void icache_disable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"fence.i\n\t"
-		"csrr t1, mcache_ctl\n\t"
-		"andi t0, t1, ~0x1\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#endif
-#endif
 }
 
 void dcache_enable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"ori t0, t1, 0x2\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#ifdef CONFIG_V5L2_CACHE
-	_cache_enable();
-#endif
-#endif
-#endif
 }
 
 void dcache_disable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"andi t0, t1, ~0x2\n\t"
-		"csrw mcache_ctl, t0\n\t"
-	);
-#endif
-#ifdef CONFIG_V5L2_CACHE
-	_cache_disable();
-#endif
-#endif
-#endif
 }
 
 int icache_status(void)
 {
-	int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"andi	%0, t1, 0x01\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	);
-#endif
-#endif
-
-	return ret;
+	return 0;
 }
 
 int dcache_status(void)
 {
-	int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	asm volatile (
-		"csrr t1, mcache_ctl\n\t"
-		"andi	%0, t1, 0x02\n\t"
-		: "=r" (ret)
-		:
-		: "memory"
-	);
-#endif
-#endif
-
-	return ret;
+	return 0;
 }