ARM: uniphier: refactor outer cache operation slightly
Improve readability without changing the behavior.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c
index b4ca8b6..4a79966 100644
--- a/arch/arm/mach-uniphier/cache_uniphier.c
+++ b/arch/arm/mach-uniphier/cache_uniphier.c
@@ -67,7 +67,9 @@
*/
start = start & ~(SSC_LINE_SIZE - 1);
- if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
+ size = end - start;
+
+ if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) {
/* this means cache operation for all range */
uniphier_cache_maint_all(operation);
return;
@@ -77,7 +79,7 @@
* If end address is not aligned to cache-line,
* do cache operation for the last cache-line
*/
- size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
+ size = ALIGN(size, SSC_LINE_SIZE);
while (size) {
u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?