tree 586da5b54fd7b952c6b792363e54b483ddf38bcb
parent 441a8d6aa80befd6817c0f9579210e973ad065d8
author Marek Vasut <marek.vasut+renesas@mailbox.org> 1738187690 +0100
committer Marek Vasut <marek.vasut+renesas@mailbox.org> 1738708320 +0100

remoteproc: renesas: Synchronize caches across cores

Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>