| commit | 7f9ccebee735a535baeb9c3978803db60922e687 | [log] [tgz] |
|---|---|---|
| author | Christian Marangi <ansuelsmth@gmail.com> | Fri Aug 02 15:45:05 2024 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Mon Aug 19 16:12:51 2024 -0600 |
| tree | c163177a06c363df5bde69e769e1fa282109d33d | |
| parent | b6ea620a42cd3294b3fc7973d6a15c23e6eccfa9 [diff] |
clk: mediatek: mt7623: remap peri clock ID and add MUX Upstream kernel linux makes use of peri clock MUX to setup UART. Add definition for these and add remap table as in the upstream clock ID order gates are before MUX but we require MUX first and then clocks in our downstream driver. Convert the peri clk tree to MUX + GATE implementation. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>