ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 6586015..1dd5d07 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -13,12 +13,13 @@
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
- CLOCK_OSC_FREQ_13_0,
- CLOCK_OSC_FREQ_19_2,
- CLOCK_OSC_FREQ_12_0,
- CLOCK_OSC_FREQ_26_0,
+ CLOCK_OSC_FREQ_13_0 = 0,
+ CLOCK_OSC_FREQ_16_8,
+ CLOCK_OSC_FREQ_19_2 = 4,
CLOCK_OSC_FREQ_38_4,
+ CLOCK_OSC_FREQ_12_0 = 8,
CLOCK_OSC_FREQ_48_0,
+ CLOCK_OSC_FREQ_26_0 = 12,
CLOCK_OSC_FREQ_COUNT,
};
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 77c8ad9..11bffc1 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -28,16 +28,23 @@
static unsigned pll_rate[CLOCK_ID_COUNT];
/*
- * The oscillator frequency is fixed to one of four set values. Based on this
+ * The oscillator frequency is fixed to one of seven set values. Based on this
* the other clocks are set up appropriately.
*/
static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
13000000,
+ 16800000,
+ 0,
+ 0,
19200000,
- 12000000,
- 26000000,
38400000,
+ 0,
+ 0,
+ 12000000,
48000000,
+ 0,
+ 0,
+ 26000000,
};
/* return 1 if a peripheral ID is in range */
@@ -766,6 +773,7 @@
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
break;
@@ -776,10 +784,13 @@
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
break;
+
case CLOCK_OSC_FREQ_19_2:
+ case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index 65b15b7..59ca8ae 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -55,11 +55,18 @@
*/
{
{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
- { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T25: 1.2 GHz
@@ -73,11 +80,18 @@
*/
{
{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
- { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T30: 600 MHz
@@ -91,11 +105,18 @@
*/
{
{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+ { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 16.8 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+ { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 38.4 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+ { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 48.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
- { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
- { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T114: 700 MHz
@@ -108,11 +129,18 @@
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
- { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
- { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
@@ -126,11 +154,18 @@
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
- { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
- { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
@@ -143,12 +178,19 @@
* PLLX_BASE m 7: 0 8
*/
{
- { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
- { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
- { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
- { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz */
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.0 MHz = 702 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz */
{ .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz */
{ .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* (N/A) */
+ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz */
},
};
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index 703a231..143f868 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -459,8 +459,7 @@
/*
* Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that T30/T114 support 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
+ * field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -469,12 +468,7 @@
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
+ return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
/* Returns a pointer to the clock source register for a peripheral */
@@ -674,6 +668,7 @@
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
@@ -684,10 +679,12 @@
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
case CLOCK_OSC_FREQ_19_2:
+ case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index bbfe184..da38b26 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -601,8 +601,7 @@
/*
* Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that Tegra30+ support 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
+ * field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -611,12 +610,7 @@
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
+ return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
/* Returns a pointer to the clock source register for a peripheral */
@@ -854,6 +848,7 @@
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
@@ -864,10 +859,12 @@
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
case CLOCK_OSC_FREQ_19_2:
+ case CLOCK_OSC_FREQ_38_4:
default:
/*
* These are not supported. It is too early to print a
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 3b50a81..8c12743 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -399,7 +399,9 @@
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
- return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+ reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+ return reg << 2;
}
/* Returns a pointer to the clock source register for a peripheral */
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 10c2478..330753f 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -672,8 +672,7 @@
/*
* Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that Tegra30+ support 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
+ * field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -682,22 +681,7 @@
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
- /*
- * 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
- * 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
- */
- if (reg == 5) {
- debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
- /* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
- return 4;
- }
-
- /*
- * Map to most common (T20) freqs (except 38.4, handled above):
- * 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
- */
- return reg >> 2;
+ return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
/* Returns a pointer to the clock source register for a peripheral */
@@ -986,6 +970,7 @@
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
@@ -996,6 +981,7 @@
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index c835cd0..449b66e 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -439,8 +439,7 @@
/*
* Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that T30 supports 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
+ * field. Note that T30+ supports 3 new higher freqs.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
@@ -449,12 +448,7 @@
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
+ return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
/* Returns a pointer to the clock source register for a peripheral */